Reconfigurable Digital Sequential System on Chip Design with Its Analysis of Various Parameters &

Power Reduction Using Dynamic Partial Reconfiguration

Navneet Agrawal1 Assistant Professor, Dept. of ECE, CTAE, Udaipur, India navneetctae@gmail.com

Mayuri Jain2 M.Tech Scholar, Dept. of ECE, CTAE, Udaipur, India mayurijn8@gmail.com

Abstract— In this paper, we have designed a Reconfigurable

Digital Sequential System on Chip design capable of transmitting and receiving data in parallel in 8 bits to 512 bits range. This circuit provides Reconfigurable point to point communication, data rate of 1.54 Gbits/sec to 277 Gbits/sec. The design comprises of two Sub Circuits: Transmitter/Receiver & Router. Our objective after developing Reconfigurable system was reduction of the power consumption in the circuit by exploiting Dynamic Partial Reconfiguration, which we get after results is nearly 5% - 10% of the total power consumption of the circuit and finally we have concluded the calculated parameters i.e. Power Consumption (Static and Dynamic), Delay, data rate and Resources Utilized by taking all the Reconfigurable Transreciever as platform on the various FPGA families by Xilinx and finally plot them on graph, so as to exploit respective family according to application, specification as well as constraints what is the best chosen parameter and family according to the analysis made. The complete circuit is programmed in VHDL, and synthesized and simulated on Xilinx design suite 14.4 ISE.

Keywords— Reconfigurable; FCT; EOP; EEP; Null-character; Got nul; control flag; credit error; Escape error; entrance; matrix; cell; full duplex.

I. INTRODUCTION The main data-handling networks for spacecraft are

designed in such a way so as to meet the requirements of the space applications, as we know that there is huge amount of data which has to be acknowledged from the satellite and moreover this data is highly variable in amount as well as in nature. Therefore a device is needed to accept data which is highly variable and unpredictable from the satellites and to connect together high data-rate sensors, processing units, memory sub-systems and the downlink telemetry sub- system, forming a comprehensive data-handling network. Transmitter and receiver link are used to transmit the data at a very high-speed (200Mbps to 2600 Mbps) on a directional, full-duplex data links, which interconnect equipment with interfaces of transmitter and receiver [1]. Application information is sent along a Transreceiver link in discrete packets, which can be of any size appropriate to the application.

The design comprises of two Sub Circuits: Transmitter/Receiver & Router. There are several modules of Transreceiver which comprises of a Transmitter, Transmitter First In First Out, Receiver, and Receiver First in First Out, Random Access Memory and State Machine [2]. Router provides the facility of the interconnection between two Trans receivers. There are three modules of Router, which includes Entrance, Matrix and Cell.

The paper is organized as in this way. The Reconfigurable Digital Sequential System on Chip Circuit Design in section I Signal description of Transreceiver in section II The modified architecture of Transmitter and Router in section III Signal Description of Transreciever in section IV Signal Description of Router in section V Result & Analysis in section VI Conclusion & Future Work in section VII Finally we show the references in section VIII.

II. RECONFIGURABLE DIGITAL SEQUENTIAL SYSTEM ON CHIP DESIGN MODULES

The Circuit connects host system to a satellite or remote network. Transmitter and Receiver are the fissionable components of the network and are source and destination of transmission link.

Fig. 2(a). Transreceiver [3]

1346978-1-4673-6217-7/13/$31.00 c©2013 IEEE

The design comprises of two sub circuits: Transmitter/Receiver & Router. There are several modules of Transreceiver which comprises of a Transmitter, Transmitter First In First Out, Receiver, and Receiver First in First Out, Random Access Memory and State Machine [3]. Router provides the facility of the interconnection between two Trans receivers. There are three modules of Router, which includes Entrance, Matrix and Cell. All these Modules are designed and coded in VHDL language and synthesized and simulated on Xilinx design suite 14.4.

State Machine:

Fig. 2(b). Various Modules in Reconfigurable Digital Sequential System On chip Design

The initial state is the “Error Reset” state, after an external reset is given, or if an error occurs during link initialization operation of the link, it is terminated. Both transmitter and receiver are resetted in “Error Reset” state. If reset is deasserted, this state will move into “Error Wait” state after 6.4 s. In this state, the receiver is enabled and it waits for 12.8 s. For this time period we have to make sure that both ends of the link are actually ready to receive data before any of the ends begins transmission. The “Ready” state checks if the interface has permission (Link Enable) to build up a link. If Link Enable is true the state machine moves on into “Started” state and waits for a time period equal to 12.8 s for NULL-characters. If during this time period NULL characters are received the state machine moves into “Connecting” state and waits 12.8 s for FCTs. If an FCT is received the state machine moves into “Run” state. In “Run” state normal operation i.e. the transmission and reception takes place.

III. ARCHITECTURE OF ROUTER, TRANSMITTER AND RECEIVER

The Transmitter module codes and transfers the user data and operates the handshake mechanisms. Additionally it calculates the parity bits in a 2-stage pipeline process. The

“tx_valid” signal indicates the validity of the data and is connected with “rx_valid” of the receiver. Figure 3(a) shows the state diagram. In idle mode the transmitter sets all bits, except the parity bit to ‘0’. The parity bit is set to ‘1’ to cover the odd parity. In “run” state the transmitter sends NULL character to sustain the link connection.

Fig. 2(c). State Machine

a) Transmitter First In First Out The transmitter FIFO can be accessed with the low

active “dat_write” signal”.

Fig. 3(b). Transmitter State Diagram

As soon as the FIFO is full the “dat_full” signal is ‘1’. FCTs received by the receiver are forwarded with the “fct_nwrite” signal to the transmitter. The “fct_nwrite” increments the credit counters. If the credit counter receives 7 FCTs the “fct_full” signal is set. For a bi-directional full-duplex transfer the FCTs have to be included in the data transfer. The tx FIFO does not require a dedicated RAM, because it just has to store 1 data word [3].

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b) Receiver: The receiver module receives the parallel data of the

l i n k since SoCWire is a synchronous implementation it requires additional signal to indicate the validation of the data. This is implemented with the high active “rx_valid” signal. The receiver is responsible to detect link errors. The errors are passed on to the state machine with various signals as “err_par” (parity error),”err_esc” (escape error),”err_dsc” (disconnection error),”err_nchar” (character error) and “err_fct” (fct error). A disconnection error is triggered if the link is inactive for disconnect _detections (generic in the VHDL model) after the first link connection was established. Inactive is related to the rx_valid low period. This state is implemented with a counter (dsc_count). The receiver communicates with the rx_FIFO, to transfer data with the “dat_dout” signal. A valid received N-Char is displayed with the “dat_empty” signal. Additional valid received FCTs are displayed with the “fct_empty” signal. The rx_FIFO signalize its internal FIFO fill state to the receiver. If the FIFO is full and still an N-Char is received a character error is triggered.

c) Receiver First In First Out: The rx_FIFO can be accessed from the host interface with

the low active “dat_nread” signal. [3] The fill state of the FIFO is indicated with the high active “dat_empty” signal. If “dat_empty” is ‘0’, data can be read from the FIFO. The “dat_dout” signal vector provides the user data. It is 1+ n bits width, n is data word width and the MSB is the Data Control Flag.

IV. SIGNAL DESCRIPTION FOR ROUTER MODULE The router enables The Router enables the transfer of

packets arriving at one link interface to another link interface on the switch. The Router provides a configurable number of ports, realized by internal Transreceiver.

Fig. 4(a). Router Structure

The Router comprises at least 5 modules. The numbers of Transreceiver are equivalent to the number of ports. Each cell module represents an inter-connection between two ports and

therefore a switch with 4 ports comprises 16 cells or with 32 ports 1024 cells.

Fig. 4(b). Router Design [3]

TABLE I. SIGNAL DESCRIPTION OF ROUTER MODULE [3]

Name Type Function Active

Rst I/P Reset High

Clk I/P Clock

Rx I/P SoCWire Switch receive Link

Rx_valid I/P When Active current receive link data is valid

High

tx O/P SoCWire Switch transmit link

Tx_valid O/P When Active current transmitter link data is valid

High

active O/P When Active, link is connected, running, transmission can start

High

a) Entrance: The entrance module analyzes the header of incoming

packets. If the packet destination port is valid the module deletes the header and forwards the cargo to the matrix with the destination port information. For each port an entrance module is instantiated, therefore a 4-port switch has 4 entrance two modules. This is necessary to provide an independent communication of each port. Additional the entrance module marks a port as “full” if a cargo is transferred. The entrance module itself does not receive information if the port is busy. The requested port of the current packet is therefore transferred to the matrix with the “wanted” signal. This signal tests autonomously if the connection to the destination port can be established. This information is provided to the entrance module with the “nwrite” signal. If it is ‘0’ the

Router

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transfer can be started. If the entrance receives an EOP or EPP, the header deletion is enabled and destination address is determined for the incoming next packet.

b) Matrix: The matrix (crossbar) manages the cargo transfer to the

destination port by cell modules. To provide parallel data transfer between different ports, the matrix conceives data transfers of all ports as bit vector. Therefore the bit width of the matrix is data wordwidth+1(data control flag) × number of ports.

V. SIGNAL DESCRIPTION FOR TRANSRECIEVER MODULE

TABLE II. SIGNAL DESCRIPTION OF TRANSRECEIVER MODULE [3]

VI. VI RESULTS AND ANALYSIS

A. Power Reduction Using Dynamic Partial Reconfiguration: We have designed a Reconfigurable Digital Sequential

System On chip design, the power consumed in the designing of such a circuit consist of Dynamic and static power. We have reduced the power consumed in the sequential circuit design by exploiting the feature of Partial Dynamic Reconfiguration in which we have individually powered off the modules in the Sub Circuits which are not in currently used by the system [4], [5], [6]. These modules include Transmitter, Transmitter FIFO and Receiver, Receiver FIFO and the components which are declared in the state machine. When the transmission of data is taking place and we are not in receipt of any data then there the modules of Receiver and Receiver FIFO can be individually powered off to save the static power, similarly when we receiving the data and no transmission of data is taking place, then we are individually powering off the transmitter, Transmitter FIFO during the operation. This depends upon the working of the state machine, in which there are seven states, only one state work at a time, powering off the components depends upon the activated components or elements in that state machine, only the elements active at that time in that particular state are supplied with power, rest all components are deactivated for that state. This deactivation is done by the use of two control signals for enabling and disabling the individual components in the state machine. Same technique is applied to all seven states and by employing this technique we are able to save the considerable amount of power as we increase the data width of our Transreceiver circuit. The following graph illustrates the power reduction for the data width of 8 bits - 512 bits, with Dynamic Partial Reconfiguration [7] and Without Dynamic Partial Reconfiguration. Automatically reconnection after update of a module makes it even more suitable for dynamic reconfigurable system. By exploiting the partial run-time reconfiguration of an FPGA, a large design can fit into a smaller device. As the hardware can be shared between various applications, the resource utilization is increased. Even though the power dissipation during reconfiguration cannot be neglected, the total Power consumption of the system is decreased by 5% - 10% (8bits - 512 bits) i.e. from 10mW (8bits) to 40mW (128bits). This ensures that we are getting better results than the one without Dynamic Partial Reconfiguration.

Fig. 6. Reduction in Power Consumption with Dynamic Partial Run Time Reconfiguration

Signal name Type Signal Function Active

Reset I/P Rst RESET High

Clock I/P clk CLOCK

SoCWire Enable

I/P socw_en LINK ENABLE-When assert codec can move to ready state

High

SoCWire Disable

I/P socw_dis Link Disable - When assert and in Run state CODEC moves immediately to Error Reset state

High

Receiver I/P Rx SoCWire CODEC receive link

Receiver Valid

I/P Rx_valid When assert current receiver link data is valid

High

Transmitter O/P Tx SoCWire CODEC transmit link

Transmitter Valid

O/P Tx_valid When assert current transmitter link data is valid

High

Data Full O/P Dat_full Input Data Interface - Indicates the input FIFO is full, write is rejected

High

Data Write I/P Dat_nwrite

Input Data Interface - Write data to CODEC

Low

Data Input I/P dat_din Input Data Interface - User data ( datawidth-1:0), Data control flag (data width)

Data Read I/P dat_nread

Read data from CODEC

Low

Data Empty O/P dat_empty

Indicates fifo empty, no data available

High

Data Out O/P dat_dout User data (datawidth-1:0), Data control Flag (data width)

Active O/P active When active, link is connected and running, transmission can start

High

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TABLE III. REDUCTION IN POWER CONSUMPTION WITH DYNAMIC PARTIAL RUN TIME RECONFIGURATION

Data Word Width 8 16 32 64 128 256 512

Power (in mW) 762 762 770 794 782

Power DPR (in mW) 752 752 751 749 744 755 749

B. Analysis of Various Parameters: 1) Power Consumption Analysis: We find that total power consumption (i.e. static and

dynamic) increases with increase in data word width and is minimum in Spartan 6 LP is equal to 11mW – 35mW.

Fig. 7(a). Power consumption vs. data word width

2) Resource Utilization Analysis: From the following graphs we analyse that the Utilization

of the resources increase as the data width increases, also the utilization or consumption of the memory is largest in Vertex 5 family of FPGA irrespective of the data width involved, and also the minimum memory requirements are in Spartan 3 Family of FPGA.

3) Delay Analysis: The minimum delay occurs in the Kintex-7 family of FPGA

irrespective of the data width used and calculated to be 1.843ms.

Data rate is given by:

Data Rate = Operated frequency × Data width

If data width increases than data rate also increases. We analyzed that as the data word width increases, data rate also increases, which indirectly increases the speed and minimizes the delay involved and finally also decreases the power consumed in the circuit. Data Rate is maximum with Kintex-7 calculated to be 277.8 GHz.

Here we have analysed various parameters: Resources Utilized, Delay, Data Rate and Power Consumption on all the available families in the circuit and found best results for minimum power consumption using the technique of Dynamic Partial Reconfiguration on Space Grade family of FPGA whose main application is in space [8],[9]. We find that delay is constant throughout and is independent of data word width, while the resources utilization and data rate increases.

Fig. 7(b). Resource Utilization vs. data word width

Fig. 7(c). Delay vs. Data Word Width

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Fig. 7(d). Data rate vs Data word Width

VII. CONCLUSION & FUTURE WORK In-flight r e -configurability enhances space applications

with more protection and performance improvement. Dynamic partial reconfiguration enables mission specific flexibility on request. In this Paper we presented the current available FPGAs for space.

Fig. 7(e). Analysis of various Parameters in Space Grade Vertex-4 family of FPGA

Applications and outline their suitability for dynamic partial reconfiguration. Here we have reduced the power utilized in the circuit designed for space application by using these techniques by an amount of 10mW- 50mW for Reconfigurable circuits designed for 8 bits to 512 bits. We

have outlined the requirements for this approach and compared various parameters such as, Power Consumption (Static and Dynamic), which is calculated to be minimum for Spartan-6 LP = 11 mW for 8 bit to 35mW for 128 bit. Total delay, is minimum for Kintex-7 =1.843, Resources Utilized, which is calculated to be minimum for Spartan 3A DSP = 204 Mbytes. Data Rate is maximum for Kintex-7which is equal to 277.8 GHz/sec by taking all the Reconfigurable Transreciever as platform on the various FPGA families by Xilinx, so that the user with the appropriate constraints can configure and find the best suitable family for transmission and reception of the data according to various specifications or parameters for which he needs best and interested in. The purpose of the this circuit is to simplify the construction of high-performance onboard data handling systems, to decrease system incorporation costs, to endorse compatibility between records handling apparatus and subsystems, and to encourage re-use of data handling equipment across several different applications. It ensures that equipment is compatible at both the component and sub-system levels. For future space applications the demands for high performance on-board processing increases enormously. High data rates are achieved with significantly small implementation efforts. Hardware error detection, hot-plug ability and support of adaptive macro-pipeline are provided. The high flexibility reference design allows the designer to adapt this system quickly to any possible basis architecture. Validation and verification are simplified by a low resource use.

REFERENCES [1] S.M. Parkes. Standard ECSS-E-50-12A, Spacewire, Links, Nodes,

Routers and Networks, European Cooperation for Space Standardization, 2003.

[2] European Space Agency, Space Wire Web Page, European Space Agency.

[3] Björn Osterloh, IDA SoCWire, Issue draft, Revision-1, SoCWire V1.0, 22 April 2009.

[4] Xilinx User Guide, Partial Reconfiguration, UG702, v14.5 April 26, 2013.

[5] Christian Kohn, Xilinx User Guide, Partial Reconfiguration of a Hardware Accelerator on Zynq-7000 All Programmable SoC Devices XAPP1159 , v1.0, January 21, 2013.

[6] K. Paulsson, M. H¨ubner, S. Bayar, and J. Becker, “Exploitation of Run- Time Partial Reconfiguration for Dynamic Power Management in Xilinx Spartan III-based Systems,” ReCoSoc2007, Montpellier, France, June2007.

[7] Vikas Gupta, Vivek Jain,”High Speed Reconfiguration Transreceiver for on Chip Network” in “Computational Intelligence and Communication Network”, MIR Labs, Gwalior, October 2011.

[8] Wang Lie, Wu Feng-yan, “Dynamic Partial Reconfiguration in FPGA”, Third International Symposium on Intelligent Information Technology Application, IEEE Computer Society, 2009.

[9] Xilinx User Guide, Space-Grade Virtex-4QV Family Overview, DS653, v2.0, April 12, 2010.

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