A CMOS Four-Quadrant Current Multiplier Using Electronically Tunable CCII

Montree Kumngern1, Somyot Junnapiya2 Department of Telecommunications Engineering, Faculty of Engineering,

King Mongkut’s Institute of Technology Ladkrabang, Bangkok 10520, Thailand E-mails: 1 kkmontre@kmitl.ac.th, 2 somyot@telecom.kmitl.ac.th

Abstract—This paper presents a new analogue four-quadrant current multiplier using electronically tunable second-generation current conveyor. The proposed structure is highly suitable for implementation in low cost technology as CMOS technology. PSPICE simulators using the 0.5 μm CMOS parameters are performed to confirm the workability of the proposed structure. The simulation results show that the proposed multiplier yields excellent temperature stability and good analogue multiplication.

Keywords–four-quadrant current multiplier, current-mode, analog circuit, second-generation current conveyor

I. INTRODUCTION Recently, the second-generation current conveyors (CCIIs)

have become very popular because of their high performance such as, simple circuitry, wide bandwidth, high linearity low-power consumption and wide dynamic range [1]. They have involved to their wide application for implementation of analog signal processing circuits, see, for example [2]-[5].

Multiplier is an nonlinear circuit that can be used in amplitude modulation, frequency multiplier, frequency divider, automatic gain control, square-rooter, phase-locked loops, adaptive filtering and RMS-to DC converter [6], [7]. Analogue multipliers using CCIIs as active elements were proposed [8]-[12]. However, these structures use MOS transistor operating in triode region which is suffer from the high-frequency limitation. One advantage of multipliers using active building block as active element is that a low complexity of circuit can be achieved. Thus, several active building blocks were used to realize analog multipliers, i.e., [13]-[18]. The circuit in [13] uses current differencing buffered amplifier (CDBA) and attached to MOS transistors operating in triode regions while the circuit in [14] uses operational amplifier (op-amp) and attached to resistors. However, these structures still suffer from the high-frequency limitation. Moreover, the use of floating resistors makes the circuit in [14] not ideal for integrated circuit implementation. The current-controlled current conveyor transconductance amplifier (CCCCTA) and current-controlled current differencing transconductance amplifier (CCCDTA) were also used to realize multipliers [15], [16]. However, these circuits are only suitable for implementation in bipolar technology. More recently, CCII with variable current gain [19] was used to realize current multipliers [17], [18]. Unfortunately, the structures are still only suitable for implementation in bipolar technology.

Therefore, a new four-quadrant current multiplier using electronically tunable CCII (CCII with variable current gain) which is suitable for implementation in CMOS technology is proposed in this paper. The electronically tunable CCII is realized by using differential difference current conveyor (DDCC)-based log-antilog amplifiers [20]. PSPICE simulation is used to confirm workability of the proposed circuit.

II. PROPOSED CIRCUIT In this paper, electronically tunable CCII (ECCII) can be

realized using CMOS technology [21] as shown in Fig. 1. It uses DDCC [10] and diodes. The input-output characteristics of ideal DDCC is described as

xy1

y1y2

y2y3

y3x

z

V 1 1 1 0 VI 0 0 0 0 VI 0 0 0 0

V0 0 0 0I

I0 0 0 1I

−

= (1)

Fig. 2 shows log-antilog current amplifier using DDCC as active element [20]. It consists of one DDCC and four diodes. For more suitable for implementation in CMOS technology, these diodes can be implemented by junction diode that realizes using CMOS technology [20].

Figure 1. Electrical symbol of DDCC.

Figure 2. DDCC-based log-antilog current amplifier [20].

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x

Ib2

MF3 MF4

Ib1

Ib3 Ib4 D3

D2

D1

D4

Ic1

DDCC1

y1

z-

xy3

y2

Io1Id1

D8

DDCC2

y1

z

x

y3

y2

Io2

D7

D6

D5

Ic2

Id2

zk-

Ic1

y

Id1

zk-

MF1 MF2

MF5 MF9

MF7 MF10 MF11 MF12

Ic2 Id2

ECCII

VDD

VSS

y

MF6

MF8

zx z

Iz- Iz+

Izk-

Figure 3. CMOS inplementation of the ECCII.

Figure 4. Proposed four-quadrant current multiplier using ECCII.

From Fig. 2, when input currents Iin, Ic, Id are supplied, using the logarithm property of the forward bias p-n junction of diode, the voltages VY1, VY2 and VY3, of DDCC can be expressed, respectively, as

iny1 T

S

IV V ln

I= (2)

dy2 T

S

IV V ln

I= (3)

cy3 T

S

IV V ln

I= (4)

where IS is the reverse saturation current and VT is the thermal voltage. Using (1), the voltage Vx can be obtained as

d cinx T T T

S S S

I IIV V ln V ln V ln

I I I= − + . (5)

Assume that diodes D1, D2, D3 and D4 are closely matched, the current output Io can be expressed as

co in

d

II I

I= . (6)

It is evident that the current Iin is amplified by current ratio Ic/Id. The current amplifier in Fig. 2 will be used to realize ECCII. Fig. 3 shows the ECCII. The transistors MF1-MF12 are operated as conventional CCII (Vx=Vy and Iz=Ix). The current gain of CCII can be obtained using two current amplifiers. The current gain CCII is explained as: when Ix<0, it is mirrored by MF7-MF10 as Iz-. This Iz- is amplified by current amplifier DDCC1 and D1-D4 as Io1. On the other hands, when Ix>0, it is

mirrored by MF5-MF9 and MF11-MF12 as Iz+. This Iz+ is amplified by current amplifier DDCC2 and D5-D8 as Io2. The currents Io1 and Io2 are summed and became to the current Izk at zk- terminal. Letting Ic1=Ic2=Ic and Id1=Id2=Id, the current Ix can be amplified by the ratio of Ic/Id (Izk=(Ic/Id)Ix).

The proposed multiplier using ECCII is shown in Fig. 4. This circuit is developed next from [22]. Using (6) and letting Ibias=Ic1=Ic2=Id1=Id2, the output current can be obtained as

in1 in2out

bias

i ii

I= − . (7)

It is evident from (7) that iout is a multiplication of iin1 and iin2 and division by current Ibias. In addition, the temperature effect in terms of any parameters such as μ and VTH is also compensated.

III. SIMULATION RESULTS The proposed four-quadrant multiplier in Fig. 4 was

simulated by PSPICE simulators. The ECCII in Fig. 3 and the DDCC in Fig. 5 were simulated using 0.5 μm CMOS from MIETEC. The transistor aspect ratios of Fig. 3 and MOS diodes were listed in Table I and transistor aspect ratios of Fig. 5 were listed in Table II. The supply voltages were VDD = VSS = 2.5 V. The biasing voltage Vb of DDCC was taken as 1.7 V. The biasing currents were selected as Ib1 = Ib2 = 20 A, Ib3 = 9.6 A, Ib4 = 10 A, Ic1 = Ic2= 10 A and Id1= Id2= 10 A. Fig. 6 shows the simulated DC transfer characteristics of the multiplier. Here, the current Iin1 was swept from -20 A to 20

A while the current Iin2 was changed in step from -10 A to 10 A. The power dissipation is about 6.4 mW. The linearity error

of multiplier is also shown in Fig. 7. To show this result, Iin2 was fixed as 10 A and Iin1 was swept from -20 A to 20 A. The linearity error was about 3.5 % at maximum input current.

TABLE I. TRANSISTORS ASPECT RATIO OF FIG. 3.

MOS transistors W/L(μm/μm) MF1, MF2, MF5, MF9 2.2/1 MF3, MF4, MF7, MF10, MF11, MF12 8/1 MF6 2/1 MF8 7.8/1 D1-D8 2/1

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Figure 5. Possible CMOS implementation for DDCC.

I out[

A]

Figure 6. Simulated DC transfer characteristic.

Line

arity

err

or [%

]

Figure 7. Simulated linearity error when Iin2 = 10μA.

I out[

A]

Figure 8. Output current for temperature was varied between 25 and 100°C.

0 0.25 0.75 1.25 1.75 2.25-15

-10

-5

0

5

-15

-5

5

15

0.50 1.00 1.50 2.502.00

iin

iout

A]

A]

Time [ s] Figure 9. Operation of current squarer of a 1MHz.

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A]

A]

A]

Figure 10. Simulated product of a 250 kHz and a 5 MHz sine waves.

TABLE II. TRANSISTORS ASPECT RATIO OF DDCC.

MOS transistors W/L(μm/μm) M1–M4 1.6/1 M5, M6 8/1 M7, M8, M16, M17, M18 20/1 M9, M10 29/1 M11, M14, M15 90/1 M13 of DDCC1 91.5/1 M12 of DDCC2 91/1 D1–D4 2/1

Fig. 8 shows the output waveforms when temperature was

varied between 25°C and 100°C. It is evident from Fig. 8 that excellent temperature stability was possessed. Fig. 9 shows the simulated result when the inputs iin1 and iin2 were applied by the same frequency of 1 MHz with amplitude of 20 μAP-P. The frequency of 2 MHz and total harmonic distortion of 2.5 % were obtained from Fig. 9. Fig. 10 shows the multiplier being used for product with the inputs of a 250 kHz and a 5 MHz sine wave and amplitude of 20 μAP-P.

IV. CONCLUSIONS In this paper, a new current-mode four-quadrant current

multiplier was presented. ECCII is the main active device of the proposed circuit. The structure is very suitable for implementation in CMOS technology. Unlike the previous works, this circuit provides four-quadrant multiplier using CMOS technology. The PSPICE simulation results are used to confirm workability of the proposed circuit. The simulation results show that the proposed circuit provides good linearity and excellent temperature stability.

REFERENCES [1] C. Toumazou, F. J. Lidgey, D. G. Haig, Analogue IC design: the current-

mode approach, Peter Peregrinus, 1990. [2] M. T. Abuelma’atti, A. A. Al-Ghumaiz, M. H. Khan “Novel CCII-based

single-element-controlled oscillators employing grounded resistors and capacitors,” International Journal of Electronics, vol. 78, pp. 1107-1112, 1995.

[3] A. Fabre, O. Saaid, C. Boucherron, “High frequency applications based on a new current controlled conveyor,” IEEE Transactions on Circuits and Systems–I, vol. 43, pp. 82-91, 1996.

[4] J.–W. Horng, C.–W. Chang, M.–H. Lee, “Single-element-controlled sinusoidal oscillators using CCIIs,” International Journal of Electronics, vol. 6, pp. 831–836, 1997.

[5] A. Monpapassorn, K. Dejhan, F. Cheevasuvit, “A full-wave rectifier using a current conveyor and current mirrors,” International Journal of Electronics, vol. 88, pp. 751-758, 2001.

[6] P. E. Allen, D. R. Holberg, CMOS Analog circuit design, Holt Rinehart and Winston, Inc., 1987.

[7] A. J. Peyton, V. Walsh, Analog electronics with op amps: a source book of practical circuits, Cambridge University Press, New York, 1993.

[8] C. Premont, N. Abouchi, R. Grisel, J. P. Chante, “A BiCMOS current conveyor based four-quadrant analog multiplier,” Analog Integrated Circuits and Signal Processing, vol. 19, pp. 159-162, 1999.

[9] C. Premont, N. Abouchi, R. Grisel, J. P. Chante, “A BiCMOS current conveyor based four-quadrant analog multiplier,” Analog Integrated Circuits and Signal Processing, vol. 19, pp. 159-162, 1999.

[10] W. Chiu, S.-I. Liu, H.-W. Tsao, J.-J. Chen, “CMOS differential difference current conveyors and their applications,” IEE Proceeding–Circuits Devices and Systems, vol. 143, pp. 91-96, 1996.

[11] C. Premont, N. Abouchi, R. Grisel, J. P. Chante, “A BiCMOS current conveyor based four-quadrant analog multiplier,” Analog Integrated Circuits and Signal Processing, vol. 19, pp. 159-162, 1999.

[12] I. Myderrizi, S. Mimari, E. Yuce, “CCII+ based fully CMOS four-quadrant multiplier,” in Proceedings of 2011 24th Canadian Conference on Electrical and Computer Engineering (CCECE), Canada, 2011, pp. 759-762.

[13] A. U. Keskin, “A four quadrant analog multiplier employing single CDBA,” Analog Integrated Circuits and Signal Processing, vol. 40, pp. 99-101, 2004.

[14] V. Riewruja, A. Rerkratn, “Four-quadrant analogue multiplier using operational amplifier,” International Journal of Electronics, vol. 98, pp. 459-474, 2011.

[15] M. Siripruchyanun, W. Jaikla, “Current controlled current conveyor transconductance amplifier (CCCCTA): a building block for analog signal processing,” Electrical Engineering, vol. 90, pp. 443-453, 2008.

[16] M. Siripruchyanuna, W. Jaikla, “A current-mode analog multiplier/divider based on CCCDTA,” International Journal of Electronics and Communications, vol. 62, pp. 223-227, 2008.

[17] W. Narksarp, P. Pawarangkoon, W. Kiranon, P. Wardkein, “A four-quadrant current-mode multiplier/divider building block,” in Proceedings of 6th International Conference on Electrical Engineering/Electronics Computer Telecommunications and Information Technology, (ECTI-CON 2009), Thailand, 2009, pp. 574-557.

[18] W. Petchakit, W. Kiranon, P. Wardkien, S. Petchakit, “A current-mode CCCII-based analog multiplier/divider,” in Proceedings of 10th International Conference on Electrical Engineering/Electronics Computer Telecommunications and Information Technology, (ECTI-CON 2010), Thailand, 2010, pp. 221-224.

[19] A. Fabre, N. Mimeche, “Class A/AB second generation current conveyor with controlled current gain,” Electronics Letters, vol. 43, pp. 82-91, 1996.

[20] U. Torteanchai, M. Kumngern, K. Dejhan, “A CMOS log-antilog current multiplier/divider circuit using DDCC,” in Proceedings of IEEE TENCON 2011, Indonesia, 2011, pp. 634-637.

[21] M. Kumngern, “A new CMOS second generation current conveyor with variable current gain,” in Proceedings of 2012 IEEE International Conference on Circuits & Systems (ICCAS 2012), Malaysia, 2012, pp. 272-275.

[22] M. Kumngern, U. Torteanchai, “A CMOS current-mode multiplier/divider using a current amplifier,” in Proceedings of 2013 IEEE 7th International of Power Engineering and Optimization Conference (PEOCO 2013), Malaysia, 2013, pp. 742-745.

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