An immune-algorithm-based dead-time elimination PWM control strategy in a single-phase inverter

Jiaxin Yuan, Jianbin Pan, WenLi Fei, Baichao Chen Wuhan University

Wuhan, Hubei Province, China E-mail: yjx98571@163.com

Jiabin Jia University of Leeds

Leeds, United Kingdom E-mail:prejj@leeds.ac.uk

Abstract—In this paper, an immune algorithm is developed for optimization of the harmonic performance of a single-phase inverter under a novel dead-time elimination PWM control strategy. The proposed scheme is based on the division of reference current and constraining switching states, and executes the conventional dead-time elimination in most of the reference current fundamental period but switches to the novel dead-time elimination around the zero crossing point. Meanwhile, the presented algorithm employs the immune approach as the search method for finding the best optimal control sequence to minimize the objective function (OB) of the Total Harmonic Distortion (THD) of the output voltage waveforms. Additionally, an experimental platform based on DSP and FPGA is built. The simulation and experimental results verify the best dead-time elimination control sequences generated by IA compared with the existing conventional control strategies, not only effectively and safely eliminate the effect of dead-time, but also significantly reduce the output waveforms of THD and increase the amplitude of the fundamental voltage.

I. INTRODUCTION Today as a result of the improvement of power electronics

technology for voltage source inverters (VSIs) PWM inverters have gained wide attention in modern industrial production, such as frequency control and smart grid many fields. The developed switching devices in the PWM inverter such as IGBT, MOSFET, and others have very fast switching frequency above tens of kilohertz. It is necessary to insert a switching delay time to avoid shoot-though. However, such a blanking time causes serious problems, such as output waveform distortion, torque pulsation and increase loss [2],especially when the voltage is low and the switching frequency is high [3].

Considerable studies have been discussed to reduce and eliminate the influence of the dead-time, such as: dead-time compensation [4]-[8], dead-time minimization [9]-[11] and dead-time elimination [12]-[15]. The authors of [4] presented a technique to adjust the switching frequency to avoid unfeasible pulse width of the gating signals, but its calculation is complicated. The literature of [5]-[6] proposed online compensation strategies which eliminated the effect of dead-

time compensation resulted by switching time and drop voltage existing in power devices. However, they highly rely upon motor parameters. Kim et al. [7] through superimposing a compensation vector upon the fundamental voltage vector to counteract the disturbance voltage caused by dead-time, but the hardware detection circuit brought uncertainty and complexity. He et al. [8] proposed a system to make the disturbance voltage vector caused by dead zone follow current vector synchronous rotation, but the minimum dead-time is variable and decided by the device and operating conditions. The dead-time minimization method has been proposed in [9]-[11] by forbidding providing gate drive signals to unnecessary switches. Most of the dead-time compensation and minimization methods are developed based upon the information of current polarities. However, the result is highly affected by the harmonics around the zero-crossing points, the A/D conversion error and the testing lag, particularly when the current is small. It will be difficult and inaccurate to detect the current polarities. Therefore, the dead-time effect cannot be completely eliminated under this circumstance.

The authors of [12]-[15] proposed the dead-time elimination strategy. The principle of the method is as follows: when the output current is in positive or negative in the half circle, each bridge arm is only one power device and parallel diode to conduct in practice, thus the drive signal of the unnecessary power device can be prohibited to make it in shut off state. In this way, the dead-time is no more needed. But this method also needs to know the knowledge of accurately current polarity and switch state. Peng et al. [12] detected the current polarity by conduction states of the anti-parallel diode of a power device. Lin et al. [13] proposed the scheme does not require separate power supplies for current detection circuit. However, introducing detection circuit would produce disadvantages, such as cost and reliability. Also, the strategy presented in [12]-[13] was not suitable for current with multiple zero-crossing points. When the output current polarity changes very quickly in the zero-crossing area, and the digital signal sampling time delay or calculation time delay that are more likely to cause the lack of driving signal, so these methods can't effectively eliminate the influence of dead-time. Wang et al. [14] - [15] proposed a mixed PWM

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control strategy to eliminate the dead-time, but these control methods are based on two level PWM control scheme. All the dead-time elimination methods were based on two-level PWM, and the PWM sequences are not optimized.

This paper presents a novel dead-time elimination method based on the three levels PWM control strategy, on the top of that, IA as the search method is applied in finding best control consequence to minimize OB. Without precise current polarity detection devices, the presented method can be implemented in a seamless transition in a complete cycle, particularly around the zero crossing point. The simulation responses and experimental results are also presented to show the validity of the analysis proposed in the paper.

II. NOVEL THREE-LEVEL PWM FOR DEAD-TIME ELIMINATION

A. Principle of Dead-time Elimination

Figure 1. Signal-phase full-bridge inverter.

Fig. 1 shows the topology of the signal-phase full-bridge inverter. The inverter consists of capacitor C, inductor L, resistor R, four full-controlled switch devices V1-V4 and four anti-parallel diodes VD1–VD4. The working condition of each full controlled switch device is either turned-on (s=1) or turned-off (s=0). A phase bridge arm can be decomposed into two equivalent switch cells shown in Fig. 2. When current is positive (i >0) and power device “V1” is on, the current comes out from the upper device “V1”. When “V1” is off and the current direction retains, the anti-parallel “VD2” will provide the current path. Therefore, there is no need to turn on the opposite power device “V2”. Similarly, When current is negative (i <0) and power device “V2” is on, the anti-parallel “VD1” will provide the current path. There is also no need to control the state of the opposite power device “V1”.

Figure 2. Decompose of a generic phase-leg into equivalent switch cells

Because either units is configured with a controllable switch in series with a uncontrollable diode, each bridge arm is only one power device and anti-parallel diode to conduct in

practice, the drive signal of the unnecessary power device can be prohibited to make it in shut off state. There is no question that dead-time is not required. As mentioned, current polarity detection method and the solution of commutation problem in zero-crossing point are gordian technique for dead-time elimination control strategy.

B. A Novel Scheme of Dead-time Elimination a. Three-Level PWM for Dead-time Elimination

As shown in Fig.1, the dead-time elimination method presented in this paper is based on the three-level PWM control scheme and the division of reference current. When full-controlled power device V1 and V4 or anti-parallel diode VD1 and VD4 are conducting，the output voltage of inverter U0 is equal to DC source voltage E, the inverter state is called State “1”. Similarly, when power device V2 and V3 or diode VD2 and VD3 are conducting，the output voltage U0=-E, the inverter state is called State “2”. When only one power device V1 and anti-parallel diode VD3 is on，the output voltage U0 is equal to 0, the inverter state is called State “0”. The output current waveform of inverter will increase gradually on State “1”. On the contrary, the current will decrease on State “2” and remain or slightly decrease on state “0”. These corresponding relations and limited condition are listed in Tab.1. Therefore, when current is positive or negative, the state “2” is determined by anti-parallel diode VD1 and VD4, but not the power device V2 and V3, It is a valid condition to have conducting simultaneously, as this could avoid to a short circuit.

The reference current is divided into several zones in this paper as shown in Fig.3. The zone “a” and “d” are defined as the zero-crossing zone. The zone “b”, “c”, “e” and “f” are defined as conventional zone. Similarly, “g” and “h” are a transition point.

Figure 3. The Reference Current of Divided Area Chart

According to the status of power devices “V1, V4” anti-parallel diodes “VD1, VD4”, and refer to the current zones (a-f), PWM sequence (Xi) and output voltage U0 can be acquired and shows in Tab. I.

TABLE I. THE STATUS OF THE SWITCH IN A COMPLETE PERIOD

Zone Sequence Xi (The status of the switch and diode)

U0

a 1(VD1、VD4 ON) or 1(V1、V4 ON) E

b 1(V1、V4 ON) or 0(V1、VD3 ON) E or 0

c 2(VD2、VD3 ON) or 0(V4、VD2 ON) -E or 0

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d 2 ( VD2、VD3 ON) or 2 ( V2、V3 ON) -E

e 2 ( V2、V3 ON ) or 0 ( V2、VD4 ON) -E or 0

f 1(VD1、VD4 ON) or 0 ( V3、VD1 ON) E or 0

g 0(V1、VD3 ON) 0

h 0 ( V2、VD4 ON) 0

Fig.4 shows the three level PWM signals without dead-time which strictly controlled by a sequential process based on Tab. I. V1-V4 are conventional PWM signals for upper and lower bridge arm in two level inverter, V1

’-V4’are

conventional PWM signals without dead-time for upper and lower bridge arm in two level inverter, V1”-V4” are novel PWM signals without dead-time for upper and lower bridge arm in three level inverter. Compared to conventional dead-time elimination controlled strategy, it is very different from switching signals. Moreover, consistent with positive complementarily, the conventional PWM signals must be opposite in a phase bridge arm. However, the power devices in the same phase can have different PWM signals which mean the signals for power device V1 can be different from V3. The three level PWM control scheme makes full use of the potential of the diodes that can conduct freewheeling current. At the same time, this paper considers the synergy between the switches in the same phase. The control process is shown in Tab.1 and Fig.4 in detail.

Figure 4. Signals for PWM generator.

b. Control Sequences in Conventional Zone When the load current is positive(i>0), the conventional

PWM sequence Xi may be ‘1’ (U0=E) , ‘2’ (U0=-E) or ‘0’(U0=0). However, if the current is on the rise stage e.g. in “b” zone, in order to eliminate the effect of dead-time, Xi only can be either ‘1’ or ‘0’. The sequence ‘Xi =2’ is not allowed. Similarity, when the current is on the decline stage (e.g. in “c” zone), the sequence ‘Xi =1’ is not allowed. Additionally, the state of PWM sequence ‘Xi =2’ is equal to the freewheel diode

VD2 and VD4 are conducting and replaces conventional state of power device V2 and V3. Furthermore, the sequences of ‘Xi =0’ have different switching status in different regions, such as in “e” zone (V2 and VD4 are on) and in “f” zone (V3and VD1 are on). There are several the following advantages to adopt the measures:

1) The switching situation can be distributed equally between power devices. Compared with only one switch operating in [12]-[13], the method can decreased number of switching operations and extend the life of the switches.

2) The method can make the switches to achieve a smooth transition. Assuming that the current flows through a complete cycle (a-b-c-d-e-f-a), the switch status can be simplified as ‘1’ (V1,V4)-‘0’(V1,VD3)-‘2’(VD2,VD3)-‘2’(V2,V3)-‘0’(V2,VD4)-‘1’ (VD1,VD4)-‘1’(V1,V4). We could see that the switching of power devices are seamless transition indirectly through the freewheeling diode.

3) The current fluctuation is smaller and more smooth. In other words, the waveform of output current is better.

c. Control Sequence in Transition Zone

As shown in Tab.1, the controlled sequence Xi can be either ‘1’ or ‘0’ in “ b” zone. Similarly, the Xi can be either ‘2’ or ‘0’ in “c” zone. Now assuming the sequence ‘Xi =1’ in transition point, the current will be on the rise stage. Then the current goes into “c” zone, according to the symmetry of current, the sequence Xi should be ‘2’ in zone “c”, the current is on the decline stage. In this occasion，the current error will increase when the current decreases from its rising maximum to decline a certain value. However, assuming the sequence ‘Xi =0’, the current will remain or slightly decrease, then the current goes into “c” zone, similarly, the sequence Xi should be ‘0’, the current still remains or slightly decrease. In comparison with the error analyzed before, setting Xi =0 during transition zone have a smaller error. Therefore, the PWM sequence Xi only should be ‘0’ in transition point “g” or “h”.

d. Control Sequence in Zero-Crossing Zone

When the current is around zero-crossing points, such as zone “d” in Fig.4, the signals may be wrong or missing due to the wrong or inaccurate current polarity in [12]-[13]. Therefore, the dead-time effect cannot be completely removed under this circumstance. The paper will adopt the dead-time elimination scheme by dividing the reference current into series region (in this paper, I <±5% imax is the threshold for zero-crossing zone) to solve the zero-crossing problem.

The PWM sequence of ‘…22…’ may be appeared in conventional zero-crossing zone in the literature [12-15]. In this case, the power device V1，V2，V3 and V4 is turned off and the diode “VD2,VD3” provides the current path. However, since the current is small, the reverse voltage generated by inductance probably can't achieve the threshold voltage of the diode (VF), it can be mathematically depicted as:

2o FU E V< + (1)

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if equation (1) is satisfied, the current will be cut off in the zero-crossing region, it will lead to the waveform distortion. In order to prevent this kind of cases, this paper presented a novel dead-time elimination scheme which change the switch status of the sequence ‘2’, but need to restrain the state prior of power devices. The novel method will use the switching of “V2,V3” instead of “VD2,VD3”. In order to avoid V1 and V2 conducting at the same time, the sequence ‘0’ is not allowed before the switching beginning to transform. In other words, this method gives enough preparation time to power device “V2, V3” during zone “d”. and the turned-on time is only decided by switch devices and the circuit.

Due to only change the switching statues, the direction of current is not change and its purpose is only to makes the current value rapidly decreased to zero, the output waveform will not be distorted. According to the limit in zero-crossing zone, the sequence can only be ‘1’ (when current is in zone “a”) or ‘2’ (when current is in zone “d”). The switch status is shown in Tab.1, the current achieves a seamless transition in ‘a-b-g-c-d-e-h-f-a’ and no short through will occur.

The presented method in the paper is based on the division of the reference current, it does not require a very accurate current polarity detection devices. Furthermore，it considers a series of problem related to dead-time ,such as zero-crossing point, transition point and switch utilization rate. In addition, IA is used to optimize the dead-time elimination PWM sequence. The proposed scheme is not only effectively eliminate the effect of dead-time, but also can significantly reduce the output waveforms of THD.

III. OPTIMAL DEAD-TIME ELIMINATION CONTROL STTRATEGY

A. Immune Algorithm The Immune algorithm is an adaptive global optimization

approach of stochastic algorithms for simulating the process of natural selection and mutation. The IA seeks to maximize the defined fitness function, such as the total harmonic distortion. The antibodies correspond to the feasible digital PWM control sequences (or solutions) in an optimization problem. The antigen is the objective function, and the affinity is used to explain the relationship between the antibody and the antigen, which indicates the degree of the combination between the objective and the digital PWM control sequence.

As previously stated, The method of dead-time elimination has its new gating pulse which is different from the conventional gating pulse of PWM control. In this paper, the IA is used to optimize the switching control of dead-time elimination.

B. Objective Function (OF) The objective of the optimization is to reduce the THD of

the output waveform on the basis of dead-time elimination control strategy, so it use THD as the OF. However, due to directly use the THD as the target to quantify calculation is more difficult, and the weight of aberration between practicable inverter output and theory calculation standard sinusoidal wave is defined as OF.

Due to symmetry of the output waveforms, the IA should not calculate all of the cycle (360 degrees). Only a quarter or a half of equal parts of the entire cycle (90 or 180 degrees) is sufficient. Therefore, the convergence and efficiency of the algorithm can be greatly improved. We divide T (the entire cycle) into N parts. Each segment time is 2 /t NπΔ = , where N is a natural number. Next, the output waveforms of the mth are expressed as:

11

* ( )*( ) ( ) *( ) (2)

0,1...

m mm m

k E I m t RI t I m t t m tL

m n

−−

− Δ= Δ + − Δ

= 1 1

1 20 0

i

m i

i

Xk X

X

=⎧⎪= − =⎨⎪ =⎩

So the fitness can be defined as flowing: 2( 1)

m0 0

( ) (m) (I ( ) ( ))n n m t

i sm tm m

f x f t I t dt+ Δ

Δ= =

= = −∑ ∑∫ (3)

Where Is(t) is standard sine wave.

The smaller fitness is, the more output waveform approaches to reference sine wave, and the lower harmonic content is. Since the aim of this paper is to optimize the harmonic performance of switching control in dead-time elimination, the associated switching losses are not included.

C. Flow of IA The Implementation of the IA contains the following steps,

Fig.3. Shows the flowchart of IA :

Figure 5. Flow chart of immune genetic algorithm

Step 1) Individual encoding and initial antibodies

The encoding operator is the first step of the IA application in the solution of practical problems, and the antibody coding structure for the IA is similar to previously published [17]. In this paper, the antibody refers to a string of digits that correspond to the inverter switching pattern, and each

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antibody is coded as a compound structure using VC++, which can be defined as the following:

1 2 3, , , nChrom X X X X= (5)

Due to current special limitation of the zero-crossing point and the transition point, the initial population will be no longer simple random generation. And the sequence of its vicinity of the zero crossings point must be state of '1 'or '2', the transition point must be '0 ', the other antibodies are created randomly in the feasible space.

Calculation the antibody of fitness value and density of the presented algorithm is similar to literature [17] in this paper.

Step 2) Clone selection and clone inhibition

The main purpose of clone selection and clone inhibition is to mimic the dramatic and complex interaction mechanisms of each antibody. Certain antibodies with relatively large affinity will be definitely selected into the next generation in a process known as the clone selection operator, i.e., the antibodies within the top %α affinity are selected into the offspring. On the contrary, certain antibodies with relatively lesser affinities will be definitely inhibited, in a process referred to as the clone inhibition operator, i.e., the antibodies in the smallest

%α affinity are eliminated.

Step 3) Crossover

The crossover operator which mixes substrings of various switching configurations to generate new two antibodies may be led to make an improvement in the value of the affinity function. Fig.7 shows the detail process of operation.

Figure 6. Crossover operation

However, the crossover point must be limited by the reference current zero-crossing point and the transition point. i.e., if random patterns of dots that is zero-crossing or transition point should be regenerated.

The definitions of mutation and inversion operation are the same with the literature [17], but their specific operations still need to follow the cross-operating restrictions. And the random addition operation is similar to the initial encoding restrictions.

After IA carries out above operations, it will achieve the latest generation. If the termination criterion was satisfied, the procedures end, otherwise, it will continue from the beginning.

IV. SIMULATION Figure 1 shows the main circuit simulation experiment, the

main parameters used by IA in simulations were set as follows: Frequency f=50Hz, voltage modulation m=1.0, the switching frequency 10 kHz, the DC voltage E =88V, inductance L=0.28H, Hysteretic control with band H = 3%. The main parameters used by IA in simulations were set as Tab Ⅱ.

TABLE II. VALUE OF THE IA PARAMETERS

Parameter Value

Maximum iteration number 5000

Population size 150

Population length 50

Cross-over probability 0.6

Mutation probability 0.005

Clone selection and inhibition probability

0.01

Swap-mutation probability 0.006

Selection function a=0.5, b=0.5

Random addition probability 0.01

Table.3，4，5 respectively show control sequence under different control strategies. The 2us dead-time is composed of switching signal delay turn-on 1us and early turn-off 1us.

TABLE III. THREE LEVEL CONVENTIONAL CONTROL SEQUENCE WITH 2US DEAD-TIME

1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 1 1 0 1 1 0 1 1 0 1 0 1 0 0 1 0 0 1 0 0 0 1 2 1 0 0 0 0 2 1 2 0 0 0 2 0 0 2 0 0 2 0 2 0 2 2 0 2 2 0 2 2 0 2 2 2 2 0 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0 2 2 0 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0 2 2 2 2 0 2 2 0 2 2 0 2 2 0 2 0 2 0 0 2 0 0 2 0 0 0 2 1 2 0 0 0 0 1 2 1 0 0 0 1 0 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 1 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1

TABLE IV. THREE- LEVEL CONVENTIONAL CONTROL SEQUENCE OF NO-DEAD-TIME CONTROL STRATEGY

1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 1 1 0 1 1 0 1 0 1 0 1 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 2 0 0 2 0 2 0 2 0 2 0 2 2 0 2 2 0 2 2 2 2 0 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0 2 2 2 2 2 2 0 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0 2 2 2 2 0 2 2 0 2 2 0 2 0 2 0 2 0 2 0 0 2 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1

TABLE V. OPTIMIZED NO-DEAD-TIME CONTROL SEQUENCE BY IA

1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 1 1 1 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 2 0 0 0 0 2 0 0 2 0 2 0 2 0 2 0 2 0 2 2 2 0 2 2 2 0 2 2 2 2 2 0 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0 2 2 2 2 2 0 2 2 2 0 2 2 2 0 2 0 2 0 2 0 2 0 2 0 0 2 0 0 0 0 2 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Fig.7 shows the different control strategies for switch drive signals and the output waveforms.

-0.5

0

0.5

1

1.5

V1

-0.5

0

0.5

1

1.5

V2

-0.5

0

0.5

1

1.5

V3

0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02-0.5

0

0.5

1

1.5

V4 (a) Signals of conventional 3-lev control strategy with 2us dead-time effect.

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-1

-0.5

0

0.5

1

t (s)

Current (A)

0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.0-100

-50

0

50

100

t (s)

Voltage

(V)

(b) Output waveforms of conventional 3-lev control strategy with 2us dead-

time effect.

-0.5

0

0.5

1

1.5

V1

-0.5

0

0.5

1

1.5

V2

-0.5

0

0.5

1

1.5

V3

0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.0-0.5

0

0.5

1

1.5

V4 (c) Signals of conventional 3-lev dead-time elimination control strategy

-1

-0.5

0

0.5

1

t (s)

Current (A)

0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02-100

-50

0

50

100

t (s)

Voltage

(V)

(d) Output waveforms of conventional 3-lev dead-time elimination

control strategy

-0.5

0

0.5

1

1.5

V1

-0.5

0

0.5

1

1.5

V2

-0.5

0

0.5

1

1.5

V3

0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02-0.5

0

0.5

1

1.5

V4 (e) Signals of 3-lev dead-time elimination controlled by IA

-1

-0.5

0

0.5

1

t (s)

Cur

rent

(A

)

0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02-100

-50

0

50

100

t (s)

Vol

tage

(V

)

(f) Output waveforms controlled by IA

Figure 7. Output waveforms controlled by different control Strategies

As Fig.7 shows, compared to the 3-level control of the conventional no dead-time and 2us dead-time, the output voltage waveform controlled by IA is relatively average and reasonable, and the current is relatively close to sinusoidal. Particularly in the vicinity of zero-crossing point, voltage, and current will not transition occurs, the transition process is relatively smooth. Table.6 shows the results of simulation.

TABLE VI. RESULTS OF SIMULATION UNDER DIFFERENT CONTROL STRATEGY

Parameter IA Conventional

no dead-time

With 2 us

dead-time

THD 0.98% 2.14% 2.48%

Magnitude of fundamental

0.998 0.9951 0.989

As shown in the experiment results of Table IV, compared with 2 us dead-time, the THD of the output waveforms controlled by IA is decreased by 60.48%. And the magnitude of fundamental has the certain extent enhancement.

V. EXPERIMENT

A. Experimental Platform Fig.8 shows the experimental platform which is composed

of the following parts:

1) Low-cost high speed Texas Instruments TMS320-F2812 digital signal processor (DSP) was used to send digital PWM control signals to control the inverter. The optically coupled isolators 4N25 are used to realize an electrical isolation between the DSP controller and the main circuit.

2) driver protection and trigger circuit.

Four high-voltage high-speed IGBT drivers (EXB841) were used to provide proper and conditioned gate signals to these power switches.

3) Main circuit of signal-phase inverter

Figure 8. Schematic diagram of experiment design

B. Experimental Result and Analysis In this paper, the topology of the main circuit is shown in

Fig. 1. And the experimental parameters are set as simulation section. Fig.9 shows inverter output waveforms under different control strategies.

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(a) Experiment output waveforms with 2us dead-time effect

(b) Experiment output waveforms of converntional dead-time

elimination

(c) Experiment output waveforms of optimal dead-time elimination

controlled by IA

Figure 9. Output of inverter in different control strategies

The experimental output voltage waveforms are acquired using a TEKTRONIX 1012B oscilloscope. Using NI's Signal Express signal processing software, any order of harmonics can be measured. Fig.8(a) obviously indicates that the output current has a distortion, and the abrupt changes of inverter output voltage waveform especially around zero-crossing point. Fig.8(b) shows that the effect of dead-time has been efficiently eliminate, but the current waveform is not smooth. Fig.8(c) shows the results of the optimal dead-time elimination control method, clearly shows that the output current is very close to a sinusoidal waveform.

TABLE VII. RESULTS OF EXPERIMENT UNDER DIFFERENT CONTROL STRATEGY

Parameter IA Conventional no dead-time

With 2 us dead-time

Affinity value 35791 18219 14280

THD 1.02% 2.26% 2.59%

Rate of fundamental

0.9882 0.9827 0.9769

Using Fourier analysis, Table 7 shows the THD value, magnitude of fundamental and affinity value of the output waveforms. The affinity of the inverter switch control law obtained from IA is increased by 150% over that of 2us dead-time control strategy, and the THD of output waveforms is decreased by 60.06%. Compared to the conventional PWM no

dead-time control, the affinity of the inverter is increased by 96.45%, the THD is decreased by 54.87%. This method significantly reduces the output distortion.

VI. CONCLUSION A novel method employing IA for the dead-time

elimination control sequences of the inverter which based on three levels is presented in this paper. Compared to the conventional and another method, it has the following improvements:

1) This method of determining the switching sequence by dividing the reference current region, it can effectively solve the problem of the zero-crossing point, and does not require a very accurate current polarity detecting means.

2) According to the results of the experiments and simulations, the presented method not only effectively eliminates bad influence of dead-time but also obviously reduces the THD of the waveform.

3) With the method of dead-time elimination, the inverter also reduces gate drive power and minimizes switching loss since switches are only active for half of each fundamental cycle, so it is conducive to improve the utilization of the device and extend the life cycle.

ACKNOWLEDGMENT The authors wish to express their gratitude to the National

Foundation of China and school of electrical engineering of Wuhan University, for support of this research effort (National Natural Science Foundation of China under Grant 50807041).

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