Characteristics and Sensitivity Analysis of GateInside Junctionless Transistor (GI-JLT)

Pankaj Kumar, P.N. Kondekar, Sangeeta Singh, Ishu AgrawalDepartment of Electronics and Communication Engineering,

PDPM IIITDM Jabalpur, MP, India.Email: (pankajjha, pnkondekar, sangeeta.singh, ishu.agrawal)@iiitdmj.ac.in

Abstract—In this paper, we have analyzed the impact ofgate dielectric, doping concentration and channel engineeringon the characteristics and sensitivity of Gate Inside JunctionlessTransistor (GI-JLT). A numerical TCAD device simulator 3-DATLAS version 2.10.18.R shows that GI-JLT can deplete thechannel carriers more effectively compared with tri-gate andGate-All-Around Junctionless Transistor (GAA-JLT). The GI-JLT transistor exhibits good transfer characteristics and reducesshort channel effect (SCE) than a conventional inversion modetransistor with a high ION /IOFF ratio of 1011 subthreshold swingof 64 mV/dec and DIBL of 35 mV for the channel length of 18nm with Aluminum Nitride (AlN) as gate dielectric materialof thickness 1 nm. The characteristics and sensitivity of GI-JLTare analyzed by varying dielectric material, dielectric thickness,doping concentration and channel length. The simulation resultsindicate the suitability of the proposed novel structure forreplacing the conventional CMOS inversion mode device.

Index Terms—Gated resistor, gate-inside junctionless transistor(GI-JLT), gate-all-around junctionless transistor (GAA-JLT),sensitivity, subthreshold swing (SS).

I. INTRODUCTION

Recent microelectronics trends, aim at the fabrication ofthe devices having nano-scale dimensions. As the devicedimensions get reduced, gate control on the channel chargecarriers also gets reduced due to proximity of source anddrain regions. For this, alternative device like JunctionlessTransistors (JLT) are being reported in literature [1] and[2] along with its analog applications [3] and physics basedmodeling [4]. It is basically a resistor in which mobile chargecarriers density can be modulated by gate. In the on statethere is a large body current because of relatively high dopingof the channel region. In the off state the channel is turned offby depletion of carriers as there is a workfunction differencebetween the channel and the gate material. To enhance thedevice characteristics by enhancing the gate controllabilityvarious types of JLTs are investigated like double gatejunctionless transistors (DGJLT) [5], bulk planar junctionlesstransistors (BPJLT) [6], multi-gated Junctionless transistors[7], gate-all-around junctionless transistor (GAA-JLT) [8]are proposed. In recent literatures, Gate Inside JunctionlessTransistor (GI-JLT) [9] and [10] has been introduced, it canbe regarded as a novel device structure for use in high speedand low power electronic devices owing to its excellentSCE, ideal subthreshold swing, excellent gate controllability,low leakage current and good carrier transport efficiency.Due to superior gate controllability, GI-JLT can be used to

extract the scaling limit which is facing serious challengeslike short channel effect, super steeped doping profile andincreasing gate leakage current in conventional MOSFET.It is uniformly doped with no PN junction between source/drain and channel, it has no overlap/underlap issue betweensource/drain and gate as well. It has a very thin layer ofsilicon as a channel with high doping profile, which is volumedepleted. In this paper, we have analyzed the the impactof gate dielectric, doping concentration and channel lengthon the characteristics and sensitivity of GI-JLT by usingthe procedure illustrated in [11] and [12]. Using numericaldevice simulator 3-D ATLAS version 2.10.18.R it is evidentthat GI-JLT can deplete the channel carriers more effectivelyas compared with tri-gate and GAA-JLT. It exhibits goodtransfer characteristics and SCE than a conventional inversionmode transistor with a high ION /IOFF ratio SS is near aboutthe ideal value and highly reduced DIBL for the channellength of 18 nm with AlN as gate dielectric material ofthickness 1 nm. The characteristics and sensitivity is analyzedby varying dielectric material, dielectric thickness, dopingconcentration and channel length.

In Section II, we incorporate the device structure alongwith the simulation set-up. Simulation results and discussionsabout the characteristics of GI-JLT are elaborated in Section IIIand sensitivity of various device parameters of GI-JLT havebeen studied in Section IV, Section V finally concludes thecharacteristics and sensitivity analysis of GI-JLT.

II. DEVICE STRUCTURE AND SIMULATION

Fig.1 shows device structure of for n-channel GIJLT. Crosssection area of gate electrode (p+ poly-silicon) is 7 nm ×7 nmand is surrounded by gate dielectric (AlN , SiO2 or HfO2) ofthickness 1 nm and 2 nm of silicon layer is surrounded overgate dielectric. Aluminum electrodes are used as source/draincontact on the top of silicon layer. 3-D numerical devicesimulations are performed for proposed device using thedevice simulator 3-D ATLAS version 2.10.18.R [13], [14] and[15]. The simulations are carried out using two carriers fermi-dirac model without impact ionization to account for highlydoped channel, band-gap narrowing (BGN), Schottky ReadHall (SRH) and Auger recombination models. The mobilitymodel includes both doping and transverse-field dependence.

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Fig. 1. Proposed GI-JLT (for p-channel analysis).

TABLE ITABLE I. PARAMETERS USED DURING THE DEVICE

SIMULATIONS

Parameters GI-JLTChannel length (Lg) 14nm, 18nm and 22nm

Device layer Doping(Nd)

1.5×1019cm−3, 2×1019cm−3

and 2.5× 1019cm−3

Device layer thickness(TSi)

2nm

Gate-oxide material AlN , SiO2 and HfO2

Gate-oxide thickness(tox)

1nm

Gate bias 0.0V to 0.9V

Drain bias 0.04V & 0.9V

III. CHARACTERISTICS OF DEVICE

In this section, we have analyzed the various device char-acteristics of the GI-JLT such as DIBL, threshold voltageVth, ION/IOFF ratio and subthreshod swing (SS) by vary-ing the channel length, doping concentration, gate dielectricthickness and gate dielectric materials. Fig. 2 depicts theDIBL variations at channel length of 14 nm, 18 nm and22 nm taking three gate dielectric SiO2 , AlN and HfO2

with doping concentration of 1.5×1019 cm−3 (Fig. 2 (a)),2.0×1019 cm−3 (Fig. 2 (b)) and 2.5×1019 cm−3 (Fig. 2 (c)).It clearly shows HfO2 is having the minimum DIBL out ofthe three dielectrics. Fig. 3 shows the threshold voltage Vth

variations at channel length of 14 nm, 18 nm and 22 nm takingthree gate dielectric SiO2 , AlN and HfO2 with dopingconcentration of 1.5×1019 cm−3 (Fig. 3 (a)), 2.0×1019 cm−3

(Fig. 3 (b)) and 2.5×1019 cm−3 (Fig. 3 (c)). It is evidentthat HfO2 is having highest Vth out of the three materialas it is having highest dielectric constant. Fig. 4 explores theION/IOFF ratio variations at channel length of 14 nm, 18nm and 22 nm taking three gate dielectric SiO2 , AlN andHfO2 with doping concentration of 1.5×1019 cm−3 (Fig. 4(a)), 2.0×1019 cm−3 (Fig. 4 (b)) and 2.5×1019 cm−3 (Fig. 4(c)). HfO2 is having the highest ION/IOFF ratio out of thethree dielectric material as the off current reduces significantlyby using the HfO2. Fig. 5 depicts the SS variation at

channel length of 14 nm, 18 nm and 22 nm taking three gatedielectric SiO2 , AlN and HfO2 with doping concentrationof 1.5×1019 cm−3 (Fig. 5 (a)), 2.0×1019 cm−3 (Fig. 5 (b))and 2.5×1019 cm−3 (Fig. 5 (c)). Table II. elaborates the effectof various device parameters on the device characteristics. Itshows that SS and DIBL decrease with increase in channellength and dielectric constant, where as they increase withthe increase in the doping concentration. In addition to this,it depicts that Vth and ION/IOFF increase with the channellength and dielectric constant, and they decrease with dopingconcentration. Hence, SS and DIBL shows similar propertyin variation, and Vth and ION/IOFF have similar kind ofvariation. The optimum simulation result are SS 62 mV/ decapproaches the ideal value, DIBL, defined as the differencein Vth between Vd= 0.04 V and Vd= 0.9 V equals 35 mVand ION/IOFF 1.37×1011, is achieved under the condition ofchannel length 18 nm, doping concentration 1.5×1019 cm−3

and AlN as a gate dielectric material. These parameters hasbeen taken as reference parameter for comparison of resultwith other JLTs and conventional CMOS devices. The gatecapacitance and threshold voltage of the GI-JLT is reduced dueto the less dielectric surface area. The optimized simulationresults of proposed device show improved characteristics ascompared with other tri gate, multi gate, gate-all-around JLTand conventional CMOS device [1], [3] and [11].

Fig. 2. DIBL at different channel length and doping concentration

TABLE IICHARACTERISTICS ANALYSIS

Parameters Channel ↑ Doping↑ Dielectric↑Length Concentration Constant

SS ↓ ↑ ↓DIBL ↓ ↑ ↓Vth ↑ ↓ ↑ION/IOFF ↑ ↓ ↑

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Fig. 3. Threshold voltage (Vth) at different channel length and dopingconcentration

Fig. 4. ION/IOFF at different channel length and doping concentration

Fig. 5. Subthreshold Swing at different channel length and doping concen-tration

IV. SENSITIVITY OF THE DEVICE

This Section shows the sensitivities of the device withvariation in channel length (L), dielectric thickness (tox),

doping concentration and with different dielectric materials.The simulation results are summarized in Table III, where(∆ION/IOFF /ION/IOFF ) = ∆Iratio/Iratio , (∆SS/SS),(∆DIBL/DIBL) and (∆Vth/Vth), signify the ratio of in-cremental change in parameters to the parameters calculatedfor the reference values of GI-JLT. Fig. 6 shows vary slightvariation in parameters for change in channel length ± 22%and keeping doping concentration constant as 1.5×1019 cm−3,gate dielectric (AlN) thickness 1 nm. In Fig. 7 changing thegate dielectric material thickness ± 20% for the referencevalues of GI-JLT, shows that there is more effect on the offcurrent and Vth but a weaker effect on the other parameters ofthe device. Fig. 8 indicates great impact on the Vth for changeof doping concentration ± 33% for reference n-type GI-JLT.

TABLE IIISENSITIVITY ANALYSIS FOR (A) CHANNEL LENGTH, (B) DIELECTRIC

THICKNESS T (C) DOPING CONC. AND (D) DIFFERENT GATE DIELECTRICMATERIAL

n-type GI-JLT Channel Dielectric Doping DielectricLength Thickness profile Material

∆Iratio/Iratio 5.4% 3.75% 6.50% 31.82%∆SS/SS 0.12% 0.42% 0.005% 0.36%∆Vth/Vth 0.08% 0.09% 0.23% 0.37%∆DIBL/DIBL 1.06% 0.32% 0.29% 1.42%

Fig. 6. Sensitivity analysis for Channel Length

Similarly, Fig. 9 shows the variations in parameters forreference GI-JLT at different gate dielectric material and weobserved that there is great effect on off current of thedevice for high-K gate dielectric material which leads tomore deviation in ON to OFF current ratio of the device.Table III shows the slight effect on the parameters withchange in L, tox, doping concentration and dielectric materialin comparison with gate-all-around JLT indicating excellentcontrol of the short channel effect, because of the GI-JLTstructure as compared with [3] and [8].

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Fig. 7. Sensitivity analysis for dielectric thickness

Fig. 8. Sensitivity analysis for Doping concentration

Fig. 9. Sensitivity analysis for Different gate dielectric material

V. CONCLUSION

In this paper, we have analyzed the impact of gate di-electric, doping concentration and channel engineering oncharacteristics and sensitivity of GI-JLT by using a numerical

TCAD device simulator 3-D ATLAS version 2.10.18.R. Thesimulation results show very high Ion/Ioff current ratio, idealSS, reduced DIBL with excellent short channel characteristicsand scalability factor which makes it a promising candidatefor replacing conventional CMOS inversion mode device fornext generation high speed and low power applications.

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