978-1-4673-5292-5/12/$31.00 ©2012 IEEE

Standard CMOS Implementation of Schottky Barrier Diodes for Biomedical RFID

Sebastiao Cabral, Leonardo Zoccal, Paulo Crepaldi and Tales Pimenta

Universidade Federal de Itjauba - UNIFEI Itajuba - Brazil

Abstract — This paper presents and discusses the implementation

of a Schottky Barrier Diode (SBD) in standard CMOS technology

as a way to optimize the overall performance of a passive Radio-

Frequency Identification (RFID) based biomedical implants. It is

essential to limit the transmitted power in passive tags, mainly

for biomedical applications in order to avoid damaging the

human tissues due to local overheating. The implementation of

the SBD was obtained by changing the mask flow without any

modification to the CMOS fabrication process. The procedure

maintains the transistors functionality and adds a new device to a

standard CMOS technology. The fabricated SBD structures

present a low turn on voltage of approximately 300 mV and low

capacitance that are important parameters for passive RFID.

Keywords - RFID; passive tag; SBD; Schottky diode

I. INTRODUCTION

This cost, size, lifetime and safety are important requirements on the design of an RFID based biomedical system, especially if the receiver is an implanted device. In order to attain size reduction and extended lifetime, the receiver can be implemented without batteries, thus characterizing a passive tag.

In a passive tag, the energy is transferred from the external unit to the implanted device by inductive coupling. Besides energy, the RF link is also used to make the communication path between the base unit and the transponder, so that information can be exchanged and energy can be delivered to the implant for its activation. Figure 1 shows a typical RFID topology for biomedical applications [1].

Base Unit

Sensors +

Aquisition

+

Signal

Conditioning

+Processing

Energy + Information

Information

RF

DC

Transponder (tag)

Implanted Device

Skin

RF to DC

Rectification

Antennas

Figure 1. Typical RFID System.

The energy is transferred by a pair of coupled coils. Nevertheless, patient safety requires keeping the induced electromagnetic fields at lower levels, in order to avoid tissue damage by raising the local temperature. The Specific Absorption Rate (SAR) represents a direct measurement of the electric field (indirect measurement of the magnetic field) and induced current density over the human tissue at the implant location. The temperature variation over the time indicates the local heating factor. Both relations are given by equations (1) and (2) [2]:

This Cost, size, lifetime and safety are important requirements on the design of an RFID based biomedical system, especially if the receiver is an implanted device. In order to attain size reduction and extended lifetime, the receiver can be implemented without batteries, thus characterizing a passive tag.

Kg

WρEσ

SAR

2

(1)

s

Cc

SAR

dt

dT 0 (2)

where σ. ρ and c represent the conductivity, the human tissue mass density and specific heat capacity, respectively, at the implant location. E is the incident electric field intensity (RMS). Based on equations (1) and (2), a safe value for the power transferrable by the RF link is 10mW/cm2 [2].

Transponder front-end circuits include a rectifier used to implement the AC-DC conversion in order to provide the tag unregulated power supply. In CMOS technology, NMOS and PMOS transistors are used in different topologies to implement the rectifier circuit. These devices, however, have the disadvantage of presenting a threshold voltage (Vth) to turn on that can need a raising in the induced voltage at the receiver coil. Although the CMOS technology has been minimizing the transistors geometries, the Vth voltage does not follow the same scale of reduction. The use of a SBD is an alternative way to design the rectifier circuit in order to improve its efficiency. A more efficient rectifier will reduce the voltage drop between the tag input and the rest of the system thus reducing the power demand of the transmitter. For low current levels, as it is the case of implantable devices, the SBD voltage drop can be lower than a single Vth voltage.

2012 24th International Conference on Microelectronics (ICM)

The SBD is not readily available in standard CMOS technology but it is possible to implement it after a few adjusts in the masking process. In this work, a mask sequence is presented to implement SBDs in CMOS process along with a simple device model. It is also presented the measurement data from a few die samples.

II. SCHOTTKY BARRIER DIODE

The metal-semiconductor contact offers some features that can find use in high frequency applications and systems that must operate at low voltage levels. These features are, basically, the low level of minority charge accumulation during commutation, which leads to high switching speeds and the low voltage drop between its terminals [3].

Lower turn on voltage, faster recovery time and lower junction capacitance are advantages offered by SBD structure when compared to other types of PN diodes. Those are the main reasons the SBDs are so popular in RF applications. As a consequence of high switching speed, ability to operate at high frequencies and low turn on voltage, SBDs are applied to RF mixer and detector diodes [4].

Considering the series resistance, the IxV function of Schottky diode can be expressed as [5]:

)exp(.Vt

VIsI (3)

where, V is the bias voltage, Is is the saturation current, Vt is the thermal voltage, equals to KT/q (25,9 mV at T=300K), and η is the SBD ideality factor which can be calculated as:

Vt

vdid

).10ln(

)())(log(

(4)

The series resistance can be calculated as:

)(I

VRs

(5)

The Schottky barrier height ϕB can be calculated as:

)²*.*.

ln(.TAA

IsVtB (2)

where, A* is the effective Richardson constant (110 cm-2K-2 A).

III. SBD MASK FLOW

Ideally, the SBD would be implemented by a metal layer deposition over a low doping N or P type semiconductor well as shown in Fig. 2.

In order to reduce the series resistance to improve the efficiency, the SBD, actually, is an arrangement of fingers as can be seen in Fig. 3 and Fig. 4. The whole SBD structure is surrounded by a guard ring, which is used basically to avoid latch-up and to separate the SBD from the other tag circuits that present different analog and/or digital functions.

In this design we have used 0.5µm CMOS TSMC process through MOSIS educational program.

N+

Nwell

P+

P+

Substrate P Figure 2. SBD structure cross section view.

Figure 3. Five fingers SBD structure.

Figure 4. Nine fingers SBD layout.

In order to implement the metal-semiconductor junction it

is necessary the following mask sequence. First, an NWELL (layer #42, TSMC) and an ACTIVE (#43) are used to delimit the area that will contain the multi-finger SBD and guard ring. Then an NPLUS layer (#45) is used to indicate N+ regions that will be the SBD ohmic contacts (cathode). The next step is the CONTATCT layer (#48) that will be filled with METAL 1.

It is necessary to define the Schottky and guard ring contacts, and the contacts must reach the N well and the active regions directly. Others contacts must coincide with the previous N+ diffusions to effectively make the ohmic contacts. With the METAL1 layer (#49), the SBD is complete. Additionally, a VIA layer (#50) is used to provide interconnections between the metal levels. Finally, the METAL 2 layer (# 51) is applied to metal 2 to provide access to the ring guard. Fig. 5 shows a 3D view of layers of the basic SBD structure without PADS and interconnections (MASK #42 to #49).

It is important to observe that it is not necessary to modify the CMOS process in terms of doping levels, metal type or other process parameters.

Figure 5. 3D layers view for the complete SBD structure.

Fig. 6 shows the actual silicon implementation of 5 fingers array (SBD5), 9 fingers (SBD9) and 17 fingers (SBD17).

Figure 6. Actual SBD implementation in 0.5µm technology.

Fig. 7 shows the zoom out of the 17 fingers array (SBD17) along with the dummy structures.

Figure 7. Zoom out of the seventeen fingers SBD implementation.

IV. THE IXV PERFORMANCE

The measured I-V curve is shown in Fig. 8 for a set of 40 samples of the nine fingers (SBD9) implementation. Fig. 9 shows the Log(I)xV measurements for the five (SBD5), nine (SBD9) and seventeen (SBD17) finger implementations. As expected, the larger number of fingers corresponds to a larger current capacity.

0,0E+00

5,0E-03

1,0E-02

1,5E-02

2,0E-02

2,5E-02

3,0E-02

3,5E-02

4,0E-02

4,5E-02

-1,0 0,0 1,0 2,0 3,0 4,0

Cu

rre

nt

(A

)

Bias (V)

Average15

Avarage10

Avarage5

0,0E+00

2,0E-04

4,0E-04

6,0E-04

8,0E-04

1,0E-03

0,10 0,20 0,30 0,40 0,50

Figure 8. IxV measurements for the three SBD topologies.

Figure 9. Log(I)xV measurements for the three SBD topologies.

By using the equations (item II) and the measured data from a set of 40 samples, the SBD parameters can be compiled as in Table 1.

TABLE I. SBD PARAMETERS

Area

(um²) Rs

(Ohms) Is

(uA) ΦB (eV)

η

SBD5 431 208 0.04 0.152 0.063

SBD9 753.25 117 0.7 0.101 0.13

SBD17 1.408 75 6 0.053 0.63

V. SBD SMALL-SIGNAL MODEL

The most important difference between Schottky and PN structures is the lack junction capacitance that eliminates the electron recovery time. The equivalent small signal circuit model of the SBD, as shown in the Fig. 10.

CT

RD

RS

CGEOM

LS

Figure 10. SBD small-signal equivalent circuit.

In SBD small-signal equivalent circuit there is the capacitance (CGEOM) that arises from the device geometry. It can range between 0.1 and 1pF [6,7].

The contact resistance RD and capacitance CT both come from the depletion region, and CT can be calculated as:

2/1

2

VV

qNAC

bi

sD

T

(4)

where q is the electric charge and the V is the voltage applied across the SBD.

Finishing the model, the series resistance RS represents the depletion region, the contacts resistance and the neutral region of the semiconductor. The parasitic impedance LS influences the device operation at high frequencies [8,9]. Table 2 summarizes the SBD small signal parameters measured data.

TABLE II. SBD SMALL-SIGNAL PARAMETERS.

CT

(F)

RD

(Ohms)

RC

(Ohms)

SBD5 4*10-10 208 1.53

SBD9 8*10-10 117 0.81

SBD17 1.2*10-9 75 0.41

The presented data arises from the average of 40 samples. Those parameters will be used in future work to optimize the final geometry of the SBD.

VI. CONCLUSIONS

In this work, a diffusion of Schottky Barrier Diode in CMOS standard process is presented and discussed. This component is very attractive for RFID applications such as biomedical tags, where efficiency and power consumption are important boundary conditions to avoid patient tissue damage by overheating.

ACKNOWLEDGMENT

The authors acknowledge CAPES, CNPq and FAPEMIG for their financial support.

REFERENCES

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[3] Janam Ku and Seonghearn Lee, “Novel SPICE Macro Modeling for an Integrated Si Schottky Barrier Diode”, EGAAS 2005.

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[5] Rhoderick E H. Metal-semiconductor contacts. Second Edition. Oxford University Press, 1988.

[6] A. Pintar, J. Razinger, “Metalization of power schottky diodes”, Vacuum, vol. 40, nº. 1/2, pp. 205-207, 1990.

[7] S. V. Averin, “Fast-Response Photo-detectors with a Large Active Area, Based on Schottky-Barrier Semiconductor Structure", Kvantovaya Electronika, vol. 23(3), 284, (1996).

[8] Streetman, “Solid State Eletronic Devices”, Vol.2, pp. 185-190 (1980).

[9] Pascal Philippe, Walid El-Kamali and Vlad Pauker, “Physical Equivalent Circuit Model for Planar Schottky Varactor Diode”, Microwave Theory and Techniques: Jorunals, IEEE Transactions Volume 36, Issue 2, August 2002 Page(s): 250 - 255.