978-1-4673-5292-5/12/$31.00 ©2012 IEEE

A low power thermal protection topology

Alex Pivoto, Paulo Crepaldi and Tales Pimenta

Universidade Federal de Itajuba - UNIFEI Itajuba, Brazil

Abstract — Many circuits are subject to excessive heating such

as digital and power switching circuits. Overheating may cause

permanent damage to the circuits and devices. In this article we

present a temperature monitor the temperature variation and

once a certain limit is reached, a protection mechanism could

shut off the circuit operation or at least signalize for a specific

operation. The circuit offers linear operation from -25 ºC to

+120ºC, and it can be adjusted to detect any temperature in that

range. The proposed circuit was developed for low voltage and

low power operation, and the prototyped was designed in TSMC

0.35um technology.

I. INTRODUCTION

Heating is the largest bottleneck of power and digital switching circuits. In fact heating is the cause of concern in most circuits.

Currently, power management circuits are used in most integrated circuits applied to power switching. Thermal protection or thermal shutdown circuit is one of them, and in this paper we propose an alternative topology.

The proposed topology can be used in any circuit that requires temperature management, in order to identify and flag excessive temperatures, thus avoiding irreversible damage to the component.

The proposed topology of thermal protection can be used in any integrated circuit, including industrial and remote applications, where low power consumption is necessary.

II. CONVENTIONAL CIRCUITS

The present thermal protection circuits currently use comparators. Fig. 1 shows a widely used thermal protection circuit [1].

From the analysis of the circuit in Fig. 1 it is possible to verify that Vbe of transistor Q1 is responsible for sensing the temperature variations. It is known that a temperature variation will cause a Vbe variation on bipolar transistors. Therefore if it is known the Vbe variation for the desired temperature variation, resistors R1 and R2 can be selected so that the comparator toggle once the desired temperature has been reached. Transistor M1 is responsible for the generation of a hysteresis required by the comparator.

Depending on the Vbe variation and the comparator response time, that topology can be used on the detection of high temperatures and can present good stability [1].

VCC

R1

Vout

M1

Q1

R2

+

_

Figure 1. Conventional thermal protection circuit.

Nevertheless, that topology suffers two disadvantages. The current supplied by the Q1 branch is not stable for different power supply voltages. Additionally, the bipolar transistors also dissipate power.

III. PROPOSED CIRCUIT

The proposed circuit was developed using CMOS transistor technology that allows low power consumption, small layout area and low voltage operation.

The proposed circuit will be dived into smaller block in order to ease its understanding.

A. Biasing and PTAT

Fig. 2 shows the PTAT circuit. It is implemented using both single and composed, NMOS and PMOS transistors. The circuit is responsible to provide a voltage on C4 that is linearly dependent on the temperature variation.

The composite MOS transistor used in the PTAT circuit offers an expressive increase in the output impedance (or correspondingly decrease in the conductance) as compared to a saturated simple transistor. At the same time, the composite transistor requires the same biasing as the simple transistor, and thus does not require extra quiescent current.

Consequently, the composite transistor offers a behavior close to the ideal transistor, modeled as an ideal current source, as compared to the simple transistor [2].

2012 24th International Conference on Microelectronics (ICM)

Figure 2. Biasing and PTAT circuit.

Under a 1V power supply voltage the circuit requires current in the range of few nA. The circuit offers a highly linear behavior to temperature variations. Transistors M1, M2 and M3are responsible to provide a reference voltage of 333mV at the gate of composite transistor M3, thus forcing it to weak inversion operation. The composite transistors M4, M5 and M6 are current mirrors responsible to provide enough current to the PTAT circuit, as its biasing current. That current is adjusted by the composite transistor M7 ratio. The values of (W/L) for M7a and M7b were calculated and adjusted for a biasing current of approximately 72nA.

In order to maintain M7a under weak inversion saturation, the voltage VDSM7a must be higher than 3kT/q [2]. Consequently, the dimensions of transistor M7b required to maintain M7a under weak inversion saturation are given by equations (1) and (2).

ab L

We

L

W

13 (1)

ab L

W

L

W

19 (2)

Nevertheless, it is required a large area (W-L) for

transistor M7b in order to maintain M7a under weak inversion saturation. The same rule should also be valid for the other mirror transistors.

Transistors composite M8a and M8b work as a low power thermistor, so that VGSM9 varies linearly with the temperature. The circuit also requires a simple current source, obtained by the previous current mirror. Nevertheless the current source does not require special attention since VGSM9 does not depend on that current [9].

Transistors implemented in the same subtract are subject to expression (3), and transistors implemented in different substrates are subject to expression (4).

b

aDSa

LW

LW

q

kTV 1ln (3)

n

b

aDSa

LW

LW

q

kTV 1ln (4)

The single transistor M9 is responsible to elevate the value

of PTAT, capacitor C3 is used for the start up and capacitor C4 is used to eliminate or at least reduce the influences of ripple or any power supply voltage variation.

B. Voltage Reference

In the proposed circuit, the voltage reference is implemented by stacking PMOS transistors, as shown in Fig. 3. The stacking is necessary in order to provide a reference value for comparison with the PTAT, which refers to the temperature variation. The transistor stacking was designed in order to obtain a reference capable of detecting whenever the temperature reaches 100ºC.

Figure 3. Voltage reference.

We are currently working on a programmable reference so that few temperatures can be selected.

C. Buffer

Fig. 4 shows the buffer implementation used to isolate the comparator reference source. It was used an OTA Miller, one of the most popular operational amplifier architectures.

The operational amplifier in a voltage follower connection or buffer isolates the input signal from the load by a unit gain stage. It provides no phase inversion or signal shifting, high input impedance and low output impedance.

M1

M2

M3

M7a

M7b

M4a

M4b M5b

M5a

M8b

M8a M9

M6b

M6a

M34

M35

M36

M37

100 [°C]

VCC

C3

C4

VCC

Figure 4. Bulk driven buffer.

The operational amplifier in a voltage follower connection or buffer isolates the input signal from the load by a unit gain stage. It provides no phase inversion or signal shifting, high input impedance and low output impedance.

The bulk driven unit gain OTA Miller allows a rail-to-rail swing with shutting off the transistors [1].

D. Voltage Comparator

Current and voltage comparators are used whenever a signal needs to be compared to another one or to a specific value.

Fig. 5 shows the voltage comparator that will be used to compare the PTAT signal that varies according to the temperature variation and the reference corresponding to the desired temperature.

Figure 5. Voltage comparator.

It was used a bulk driven OTA Miller capable of 5uA output current. The comparator presents a 4ºC hysteresis that was obtained by expressions (5) and (6). The hysteresis corresponds to 11mV.

SATSAT VVn

H 1 (5)

SATVn

H2 (6)

IV. SIMULATION RESULTS

Figure 6 shows the simulation results of PTAT against the temperature. It can be observed a linear behavior, ranging from -20 ºC to 120 ºC.

Figure 6. PTAT simulation response.

As can be observed from Fig. 06, the PTAT voltage variation is limited to a few tens of millivolts. Therefore it is necessary to raise the PTAT signal before the comparator. It was used just a PMOS transistor to implement it. Fig. 7 shows the PTAT signal at C4, which is after the voltage raise.

Figure 7. PTAT at C4.

Fig. 8 presents the circuit response to biasing at start up at the gate of M3 & M4 (a), at the gate of M8 (b) and at the source of M8 (c).As it can be observed, the circuit takes approximately 150us to stabilize. The delay is promoted by the capacitor C3.

Fig. 9 illustrates the global operation of the thermal sensor. In this work, the voltage reference was set for the operation at 100ºC (Fig 9.a). If the temperature is under 100ºC, the comparator output is at logic level 1, and if the temperature raises over 100ºC, the comparator toggles to 0. The signal from the PTAT (Fig. 9.b), already raised, continues to vary along with the temperature, even after the comparison point.

TEMP [°C] -20 0 20 40 60 80 100 120

200mV

300mV

400mV

500mV

600mV

700mV

VDSM9

TEMP [°C]

-20 0 20 40 60 80 100 120 60mV

70mV

80mV

90mV

100mV

110mV

VDSM8a

M11 M10

M15 M16

M12 M13

M17

M19 M20

M18

M14

M21 Ibias 100nA

VCC

VOUT

M22

Ibias 130nA

R1

M32

VCC

R3

M23

M27 M28

M26

C2 M33

M24 M25

M29 M30

M31

R2

Figure 8. Circuit biasing at start up: (a) Gate of M4 & M5,

(b). Gate of M8a and M8b, (c) Drain of M8a.

Figure 9. Global circuit operation: (a) Voltage from the reference circuit,

(b) Raised PTAT signal.

We are currently working on a circuit in which the operation point can be adjusted to the desired temperature, on a limited range. Fig. 10 shows both the PTAT signal and the comparator output along with the reference voltage used to set up the temperature operation at 100ºC. Fig. 10.a and Fig. 10.b are basically the same as Fig 9.a and Fig. 9.b, respectively. Fig. 10.c corresponds to the output of the comparator. In this case, it was used a 280K and 15pF to represent a load corresponding to the next stage considered in the simulation.

Figure 10. PTAT circuit operation: (a) Voltage from the reference circuit,

(b) Raised PTAT signal. (c) Comparator output.

Fig. 11 presents the layout of the entire PTAT circuit. It was implemented in standard TSMC 0.35um technology.

Figure 11. Layout of the global circuit.

ACKNOWLEDGMENT

The authors acknowledge CAPES, CNPq and FAPEMIG for their financial support.

REFERENCES

[1] Zhang Bin and Feng Quan-yuan, “A Novel thermal-shutdown Protection Circuit”, 3rd International Conference on Anti-counterfeiting, Security, and Identification in Communication, 2009.

[2] L. H. Ferreira, T. Pimenta and R. Moreno, “An Ultra-Low-Voltage Ultra-Low-Power Weak Inversion Composite MOS Transistor: Concept and Applications”, IEICE Transactions on Electronics, v. E91-C, p. 662-665, 2008.

[3] Gerard C. M. Meijer and A. W. Herwaarden, Thermal Sensors, Taylor & Francis; 1st edition, 1994.

[4] L.H.C. Ferreira and T.C. Pimenta, “A CMOS voltage reference for ultra low-voltage applications,” 12th IEEE International Conference on Electronics, Circuits and Systems, Dec. 2005.

[5] David J. Comer, d Donald T. Comer, “Operation of Analog MOS Circuits in the Weak or Moderate Inversion Region”, IEEE Transactions on Education, Vol. 47, No. 4, November 2004.

[6] L. H. C. Ferreira, T. C. Pimenta, and R. L. Moreno, “An ultra-low-voltage ultra-low-power CMOS miller OTA with rail-to-rail input/output swing”, IEEE Trans. Circuits Syst. II, 843–847, Oct. 2007.

[7] Ken Ueno, Tetsuya Hirose, Tetsuya Asai and Yoshihito Amemiya, “Ultra low-Power Smart Temperature Sensor with Subthreshold CMOS Circuits”, International Symposium on Intelligent Signal Processing and Communication Systems – ISPACS, 2006.

[8] Y. Cheng and C. Hu, MOSFET Modeling & BSIM3 User’s Guide, Kluwer, 1999.

[9] Micheal A.P. Pertijs and Johan Huijsing, Precision Temperature Sensors in CMOS Technology, Springer, 1st ed, Nov, 2010.

[10] P. Crepaldi, T. Pimenta and R. Moreno, “ A CMOS low-voltage low-power temperature sensor. Microelectronics”, Microelectronics Journal), v. 41, p. 594-600, 2010.

[11] P. Crepaldi, R. Moreno, T. Pimenta, “Low-voltage, low-power, high linearity front-end thermal sensing element”,. El Letters, v. 46, p. 1271.

[12] P. Crepaldi, L. H. Ferreira, R. Moreno, Leonardo B. Zoccal; T. Pimenta, “A Vt Independent Voltage Reference Based on Composite Transistor Operating in Weak Inversion”, 10th IEEE Faible Tension Faible Consommation – FTFC, 2011, Marrakech - Marrocos. p. 12-14.

TEMP [°C] -20 0 20 40 60 80 100 120

0V

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1.0V

c

a

b

VCC

TEMP [°C] -20 0 20 40 60

80 100 120

200mV

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700mV

a

b

VCC

TIME

0s 50μs 100μs 150μs 200μs 250μs 300μs 350μs 400μs 0V

0.2V

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