2011 IEEE Nuclear Science Symposium Conference Record MICI5.S-53

The Electronics Hardware Aspects of a Prototype Experimental SPECT System

Goran Panjkovic and Matthew Richard Dimmock, Members, IEEE

Abstract-The paper discusses various features of the

electronic hardware for a single photon emission imaging (SPEI)

experimental system. The key design requirements and

constraints are determined by considering the following:

intended application and functional and technological aspects.

Specifically, the design needed to deliver high performance mixed signal hardware. The design also needed to satisfy the following

additional constraints: high density PCB design, high voltage segregation, high immunity to switching noise originating from

isolated DC/DC converters, negligible crosstalk between digital

and analogue signals, the need to fit in a confined space, achieve

high density detector stacking and provide analogue output signals with low noise. This paper describes the design concepts

and specific measures applied to achieve the following: low

parasitic capacitance on the sections of the PCB artwork used for

detector interfacing, sufficient segregation of circuits at different

potentials, adequate suppression of switching noise and isolated

high speed digital buses with small skew. For example, the reduction in parasitic capacitance is achieved by controlling both

interlayer and fringe capacitances. Further, high stacking density

is achieved by careful selection of components by their sizes and

3D planning. The need for mechanical heat-sinks is eliminated by distributing heat dissipation over a number of components and

PCB surfaces. The PCB type is selected by comparing benefits and drawbacks of rigid and flex-rigid technologies. Finally,

several factors regarding the wire-bonding of the ASIC and the

detectors are discussed.

I. INTRODUCTION

THE Pixelated Emission Detector for RadiOisotopes (PEDRO) is a hybrid imaging system designed for the

measurement of single photon emission from small animals. The proof-of-principle device consists of a Compton-camera situated behind a mechanical collimator and is intended to provide optimal detection characteristics over a broad spectral range, from 30 keY to 511 keY [1]. The system electronics comprises the following functional elements: (A) Silicon Double Sided Strip Detectors (Si-DSSD) [2, 3]; (B) PCBs with readout electronics (ROE), based on GM-Ideas V A64TAI ASICs [4]; (C) MotherBoard (MB) used to electrically and mechanically integrate all components into one system; and (D) Data AcQuisition (DAQ) system.

Manuscript received November 15, 2011. This work has been supported by the Cooperative Research Centre for Biomedical Imaging Development Ltd (CRC-BID), established and supported under the Australian Government's Cooperative Research Centres Programme.

Goran Panjkovic is with Monash Node of CRCBID, Monash University, Australia (e-mail: goran.panjkovic@monash.edu).

Matthew Dimmock is with Monash Node of CRCBID, Monash University, Australia and Australian Synchrotron (e-mail: matthew.dimmock @monash.edu) . .

Each detector is equipped with 2 ROE PCBs (one per side). The detector was developed in two phases. For the existing version (Phase 1 ), commercial pre-packaged detectors are used as they are low cost and offer a development-time efficient approach [2]. The detector is mounted on a PCB and uses a common connector type to interface with readout electronics. The key disadvantage of this option is that notable parasitic capacitance is introduced by the connectors and associated PCB patterns, degrading the signal to noise ratio (SNR) of the readout signals. The second version (Phase 2), which is being manufactured, has been designed to eliminate unnecessary parasitic capacitances - that is achieved by avoiding mechanical connectors and by using direct wire bonding to a custom built Si-DSSD [3]. A motherboard hosts all detectors and associated readout PCBs, and through a number of galvanically isolated busses integrates all components into one system, which includes HV biasing source and DAQ.

The following are key constraints that set apart design of this hardware from a typical PCB design: (1) the need to reduce capacitance at the analogue signal inputs to the practically achievable minimum; (2) the need to reliably operate mixed signal circuits at different potential levels (in excess of 100V); (3) extremely low noise operation in the presence of DC/DC converters; (4) the interfacing of the majority of signals to the external equipment through isolating circuits; (5) restricted sizes and height for components and boards; and (6) the need to segregate circuits on PCBs with restricted sizes.

II. CONCEPT

Principles of operation and the essential elements of the system are symbolically shown in Fig. 1 and further details

can be found in [1]. Selection of the readout ASICs [4] for the Si-DSSD has been based on designs described in [5], [6].

While the Si-DSSDs in Fig.l are symbolically shown as rectangular (based on the shape of the detection medium

only), the actual detector module for PEDRO Phase 2 is L­shaped (Fig. 2). The module is assembled by sandwiching a Si-DSSD between two PCBs with readout ASICs. Each PCB is used to read signals from strip electrodes from one side of the detector. A spacer is used as a part of the assembly and its key role is to protect the detector from mechanical stress. It fits as a frame around the detector, keeps the ROE PCBs apart

and increases the overall rigidity (e.g. prevents warping and bending).

A stack is formed by placing up to 8 L-shaped detector modules in a manner shown in Fig. 3. In order to place detectors as close as practically possible, detector modules are

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positioned in two alternating orientations (rotated by 1800 relative one to another). Such positioning frees up the required headroom above each ROE PCB, which is effectively doubled, compared with the headroom achieved with all modules stacked in the same orientation. The headroom IS

required to accommodate the components on the PCBs. The stack, as shown in Fig. 3, is placed above a

motherboard and connected to it by a set of ribbon or FFC cables. Yet another benefit of alternating module orientations is that connectors are distributed along all four rather than only two edges, making wiring less dense and complex.

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Fig. I. a) Si-DSSD module mounted on a motherboard with 4 ASIC boards for readout (Phase I). b) A single ASIC board (Phase I) with VA64T A. c) Schematic representation of the experimental PEDRO configuration. Two photon trajectories are shown, one for a photon that undergoes photoelectric absorption and one for a photon that undergoes Compton scattering.

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Fig. 2. An 'exploded' schematic representation of 'L-shaped' detector module (Phase 2).

Fig. 3. A schematic representation of 8 L-shaped detector modules use to construct the PEDRO detector array. (Phase 2)

III. PCBS AND WIRING

As shown in Fig. 2 a detector module is made by sandwiching a detector between two PCBs with read-out ASICs. Each ASIC PCB needs to be connected to a DAQ,

indirectly via a motherboard. The connection needs to cater for: a bidirectional digital bus, analog output signal and power supplies. For Phase 2, detector modules need to be stacked as closely as practicably possible, which imposed severe constraints on connectors choice. We experimented initially with flex-rigid PCB technology, as it eliminates the need for any connectors on the ASIC PCB (Fig. 4). While this is a very elegant technical solution, the manufacturing cost was considered as excessive for a full prototype that will have 8 detector modules. Yet another detrimental factor was that flexible section (effectively a flat ribbon cable) would have the same length on all PCBs, which could become a problem for stacking detectors and connecting them to the motherboard in a confined space (i.e. inside the cooling box). An alternative solution, based on FFC cables and connectors has been successfully implemented (Fig. 5). The height of the connectors is sufficiently small, and FFC cables with different lengths are available, which is an advantage for stacking and system physical integration.

The low profile surface mount components are selected and placed on PCBs in a way that enables tight stacking of detector modules. The key placement requirement is that there is sufficient clearance between components on PCBs located one above another to allow an isolation gap that prevents sparking.

A motherboard is used to provide connectivity between all detector modules and the DAQ. One of the key challenges for design of the motherboard was to maintain segregation between circuits at significantly different potentials and at the same time fit the entire design on a high density PCB with a relatively large number of connectors. Fig. 6 shows the PCB design, while Fig. 7 shows realization of the PCB (PEDRO Phase 2).

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Fig. 4. Flex-rigid PCBs (top) were initially evaluated for detector/ASIC modules.

Fig. 5. Assembled detector module that uses rigid PCB technology, FFC cables and low profile connectors. This alternative proved to be adequate and a lower cost substitute for flex-rigid PCBs.

As well as facilitating power supply and readout, the motherboard is also part of the base used to mechanically stack detector modules. The size of the board cannot be increased and it fits tightly inside the cooling box. The recesses along the edges are used to pass FFC cables from one side of the motherboard to another, i.e. between the PCB and

inner walls of the cooling box. In order to ensure that the cable bending radius is not too small (i.e. to prevent cable damage), detector modules are located above the motherboard side without FFC connectors (they are on the opposite side).

Wiring to the DAQ is through a set of ribbon cables and

headers. A bank of digital isolators is included on the motherboard to isolate the DAQ and ASIC PCB sides of the busses. Similarly, analog signals are isolated by using RF

transformers which are also placed on the motherboard.

Fig. 6. PCB layout of a motherboard for a stack of 8 detector modules. Because of the detectors HV bias, it is necessary to segregate PCB tracks at different potentials. The segregation is achieved diagonally from the top-left to bottom-right comers -no PCB track crosses that imaginary diagonal line. The board has 6 layers and is made from 1.6mm FR4 stack.

Fig. 7. Photo of a motherboard for a stack of 8 detector modules. The wiring shown is for 3 power supplies, each with galvanic isolation. The three power supplies are for the 10 signals on the DAQ side, and the two ASICs required to read out the opposing orthogonal DSSD strips, respectively. The motherboard can accommodate up to 8 detector assemblies, i.e. 16 ASIC PCBs. The board includes 16 FFC connector pairs (in 4 clusters), one for each ASIC PCB (one for analog signals and power, while the second is for digital lOs).

IV. INDIRECT DETECTOR-ASIC WIRE BONDING

There is a significant difference between the detector strip pitch and the pitch of the ASIC input pads. Therefore, it was not possible to directly wire bond a detector to an ASIC. Instead, PCB tracks are used to fan-out connections and boding was done indirectly via the PCB, i.e. detector - PCB -

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ASIC. For the PEDRO Phase 1, only 32 channels from the ASIC were used (from a total of 64 channels) and it was possible to rout them on a single layer (Fig. 8). The routing uses PCB track width and clearance of 100flm and that is close to the minimum that can be reliably used on an FR4 type substrate.

For PEDRO Phase 2 connections for all 64 channels were needed and based on the previous experience (Phase 1) it seemed unachievable through the PCB routing method used previously. Among other factors, this was also due to a mechanical stability issue for the longer wire bonds that connect the outer channels (Fig. 8). A two tier bonding system

was utilized as an alternative [7] and has been successfully implemented (Fig. 9). Essentially, connections were divided into odd and even tracks, where odd ones were routed on the main PCB and the even on an auxiliary PCB glued on the top of the main board. With this mechanism, a two layer routing has been achieved without use of vias. In addition, the two tier wire-bonding system is shown to offer a significant reduction of fan-out angles.

There is one drawback of this solution, namely parasitic capacitances of odd and even channels are different, which makes the SNR different for odd and even channels. Although it is detectable, it is of a tolerable magnitude. The difference is caused by the dielectric constant of the PCB. Namely, the odd tracks on the main board are sandwiched between two PCBs,

while the even tracks are sandwiched between PCB and air.

Fig. 8. PCB with single tier bonding (PEDRO Phase I) could not achieve density needed for PEDRO Phase 2. In addition, reliability of bonds has been compromised due to large fan-out angle for pads closer to the end.

Fig. 9. Two tier approach has been used to achieve higher density and reliability. An auxiliary PCB is glued on the top of the main PCB (PEDRO Phase 2).

V. INPUT CAPACITANCE

Careful PCB design is critical if the input parasitic capacitance needs to be minimized. By reducing the input capacitance, noise gain is reduced too, so that the SNR is increased. Any capacitance caused by PCB features has two major components. One is fringe capacitance (between copper features on the same PCB layer) and other is interlayer capacitance (between features on different layers). The fringe

component can be reduced by increasing separation between tracks (if possible). Interlayer capacitance at the analog inputs is reduced by routing tracks on one layer only ( Fig. 10, top) and by removing ground and power planes under this section (Fig. 10, bottom).

Fig. 10. PCB tracks between wire bonding pads for ASIC and detector (top photo). GND and power planes should be removed underneath (bottom photo) in order to reduce interlayer capacitance.

VI. GALVANIC ISOLATION

The design uses DC coupling between the detector strips and the ROE. Because of HV biasing used for depleting the detection volume, the electronics connected to the top and bottom strips of the detector need to be galvanically isolated.

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In addition, all signals from DAQ need to be isolated from electronics connected to either side of the detector. This is achieved by using: a) DC/DC converters to isolate power rails; b) transformers to isolate analog signals and c) digital 10

couplers to isolate digital signals. In addition, it is important that isolation is not compromised by PCB routing.

A. Analog Signals

Analog outputs are sent to the DAQ trough RF

transformers. Since the signals are broadband, the transformers introduce distortion that prevents direct reading of signals originating from ASICs. Therefore, DAQ firmware

uses digital signal processing to remove that distortion before readings are recorded. In addition, termination resistors need to be used to reduce distortion that may be caused by signals

reflections. A fully differential amplifier is used to amplify analog signals from the ASIC since the ASIC output stage is not capable of driving the transformer and capacitive loads imposed by coaxial cables.

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Fig. 12. The photo shows four SMD transfonners from one of the clusters.

B. Digital Signals

Galvanic isolation of digital signals is achieved thorough high speed inductively coupled active isolators (HCPL-900J). In addition to providing isolation, the coupler has sufficient capabilities to drive loads such as relatively long ribbon cables.

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Fig. 14. Photo shows digital isolators from one cluster. No tracks, GND or power planes are routed under the isolators (on any of 6 PCB layers).

VII. POWER SUPPLIES

A number of supply voltages need to be delivered over power rails and galvanic isolation is required between some of them. All voltages are generated from an external 5V power supply by using a set of DC/DC converters. They are part of a power conversion module which also includes a set of passive LC filters to reduce switching noise. However, the voltage regulation circuits are part of the mother board.

A. DC/DC Converters and Filters

The power conversion module includes five DCIDC converters. The main reason to realize this stage as a separate module is the noise introduced by the converters. Distribution of switching noise over power rails and planes is likely, but it is hard to predict its intensity at all spots or its effects on ASIC performance. Since the power circuits are on a separate PCB, it would be easier to modify or replace it with an improved version (e.g. better filtering). Yet another factor in favor of a separate power conversion module with filters is that the size

of the motherboard is strictly limited, and hence the limited space would restrict complexity of filters and effective noise attenuation. The schematic of the converters and filters are shown in Fig. IS, while its realization is shown in Fig. 16. It delivers 3 supplies with galvanic isolation, two with ±3.3V (one for readout electronics on each side of the detector) and one 3.3V for isolators on DAQ busses.

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Fig. 15. The power supply has three galvanically isolated and floating outputs. Two deliver ±3.3V and one 3.3V, which are used as input voltages for voltage regulators on the motherboard.

Fig. 16. A photo of the power supply. The red components are DC/DC converters, while the filters are realized by SMD inductors and capacitors. In addition, fuses and diodes are used for overload and reverse input polarity protection.

B. Voltage Regulators

The voltage regulators are used to deliver rail voltages for the ASICs and electronics on the readout PCBs. The required voltages are + 1.5V and -2.0V, relative to local GND. They are

derived from +3.3V and -3.3V respectively. Single stage

regulators were considered initially, however the physical sizes of voltage regulator ICs and the need for heat sinks make this impractical. Instead cascaded double stage circuits are used, where intermediate voltage of +2V and -2.5V respectively are used (Fig. 17). In that way, the heat dissipation caused by load current and voltage drops across regulators is split across two rcs. Consequently, ICs with lower power ratings and smaller packages (low profile) could be used. Heat dissipation is further enhanced by copper

polygons on the PCB, which helps to distribute heat over a larger area (Fig. 18).

Fig. 17. A schematic representation of a cascaded double stage voltage regulator for one of the voltage rails. Each regulator has two stages so that power dissipation is distributed on two active regulators.

Fig. 1 8. In this example, the power dissipation is split over two regulators, U27 and U2 8. In addition, the heat dissipation is further enhanced by copper polygons on the PCB, which helps to distribute heat over a larger area.

VIII. TEST FEATURES

The objective was to consider, plan and include

requirements for functional testing and performance verification early into the design process. Needs for partial verification (e.g. of individual units, such as: ASIC PCBs, DAQ-ASIC communication and DAQ lOs) and system

verification were both analyzed and addressed. Whenever possible, test connectors and test pads were

integrated into the design. In addition, purpose specific test boards and fixtures were designed and built.

Each ASIC board was tested individually before it was used for assembling detector modules. Considering that each module has one detector sandwiched between two ASIC PCBs, it would be too risky and potentially costly to use untested ASIC PCBs, e.g. if one ASIC was faulty, a potentially good ASIC and a detector will be wasted. Note that ASICs are delivered untested and with the yield estimated to be around 70% (although the delivered batch had better yield). To do that, a test PCB has been designed and used to connect single ASIC PCB to the DAQ which generated a test pattern and captured response.

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Several other PCBs used for testing and evaluation only are shown in Figs. 19 - 21.

Fig. 19. Test PCB used to verify that DAQ signals are correct.

Fig. 20. An interposing board used to connect digital signals from an ASIC PCB to a logic analyzer.

Fig. 21. This board is connected between an ASIC PCB (digital bus) and a motherboard, providing connectivity to a logic analyzer and without loading.

The entire system needs to be verified before cooling, which is critical considering that hardware troubleshooting is almost impossible once the unit is installed into the cooling box.

Testing options are also restricted whenever HV bias is applied. Because local GNDs are at significantly different potentials, it is not possible to observe signals from top and bottom ASIC PCBs simultaneously on test instruments such as oscilloscopes and logic analyzers since they share GND connections.

IX. CONCLUSION

Electronics for an experimental SPEI prototype detector stack has been designed and a number of specific constraints addressed. The system has been assembled primarily by using very common electronic parts and manufacturing processes, which reduced design time and manufacturing expenses. Two­tier wire bonding provides for high density ASIC-detector connectivity with small fan-out angle, while keeping side effects such as non-uniform parasitic capacitance at a tolerable level. Close stacking of detector has been made possible by using surface-mount components and by placing them in a way that ensures sufficient clearance between components on

the neighboring PCBs. The need for mechanical heat sinks is eliminated by implementing distributed power dissipation. Since this is still an experimental system, a degree of functional flexibility is needed, which has been achieved through modular design, so that functional entities could be substituted if specific improvements or alternative solutions

are needed. Testing and verification considerations were included early into the design process, covering both individual blocks and the entire system. A number of auxiliary PCBs have been designed and used to enhance testing and verification. Access to all critical signals is available, either

directly or via the auxiliary test boards.

ACKNOWLEDGMENT

We thank the following individuals and organizations that assisted us with their expertise and specialist services:

Prof Hiroyasu Tajima, SLAC, Stanford University, US - for extensive consultations and advice about detectors and GM­Idea ASICs;

Dr Matthew Solomon, MiniF AB, Australia - for guidance regarding practical aspects of high density wire bonding and delivering ASIC-PCB wire bonding;

Dr. Giulio Pellegrini, Centro Nacional de Microelectr6nia Spain - for manufacturing detectors and integration of detector modules for Phase 2; and

Greg Nolan, Aviation Data Systems (now with Uniridge), Australia - for design of the motherboard PCB for Phase 2.

REFERENCES

[I] M. R. Dimmock, et. al. "Design of a prototype hybrid small animal imaging system", Nuclear Science Symposium Conference Record (IEEE NSSIMICj, pp. 3163 -3165, 2009

[2] M15-5 Micron Semiconductor BB5 detector with 0.5 mm strip pitch, data sheet

[3] Si-DSSD, Custom designed and manufactured by Centro Nacional de Microelectronica, Spain.

[4] GM-Ideas VA64TAI, data sheet. [5] H. Tajima et. aI., "Performance of a Low Noise Front-End ASIC for

Si/CdTe Detectors in Compton Gamma-Ray Telescope", IEEE Trans. Nucl. Sci. vol. 51, no. 3, pp. 842 - 847, June 2004

[6] S. Takeda et aI., "Development of double-sided silicon strip detectors (DSSD) for a Compton telescope", Nuclear Instruments and Methods in Physics Research A 579, pp. 859-865,2007

[7] Dr Matthew Solomon, MiniFAB (Aust) Pty Ltd, Australia, personal communication, 2011

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