Abstract

In this paper, we explore use of the Power Distribution Network (PDN) of a microprocessor as a communication channel for testing, debug, and diagnosis purposes. Feasibility of the proposed communication method is studied through direct measurements of microprocessor PDNs. Decoupling capacitors attached to the package make the PDN a low pass filter. However, the parasitic inductance of a decoupling capacitor becomes more significant beyond the self-resonant frequency, and our measurements on Intel microprocessor PDNs indicate that pass bands exist at frequencies beyond several 100 MHz. Impulse ultra wideband signals are a good candidate for communications over PDNs. Index Terms: Power line communication, Testing, Debug, Design-for-testability, Power distribution network, Microprocessor, Ultra wideband

I. INTRODUCTION The power distribution network (PDN) of a

microprocessor is ubiquitous, i.e. a power line is accessible to any internal node. If the power line can be used to communicate with the external world, it can avoid preplanned routing of a data path from an internal node to an external data pin. This is a highly attractive feature for testing, debug, and diagnosis, as the routing of data paths is expensive in design time as well as in silicon area.

The use of power lines in an IC environment was introduced by the author’s group in [1] and extended to massive scan-chains in [2]. As noted in [1]-[2], power line communications (PLC) in a microprocessor faces a different set of technical

challenges from that of traditional PLC as described below [3]. Most importantly, the noise characteristics of the PDN are different from a traditional PLC. Secondly, the signal power level in the PDN should be sufficiently small not to disturb the correct operation of the circuit, which makes the recovery of data from a noisy power line difficult. Finally, a microprocessor PDN is a low pass filter to suppress ideally any signal except DC.

However, the parasitic inductance of a decoupling capacitor becomes significant beyond the self-resonant frequency. Also, the PDN is essentially a distributed circuit at high frequencies, and there exists some frequency band(s), where the attenuation through the PDN is low [1],[2],[4]. This frequency band(s) can be used for communication over the PDN. Although high frequency modeling of PDNs indicates possible existence of pass bands over a PDN, it is essential to verify it through direct measurements.

The rest of the paper is organized as follows. Section II describes preliminaries necessary to understand the proposed PLC method. Section III describes the feasibility study carried out through direct measurements of Intel microprocessors. Section IV concludes the paper.

II. PRELIMINARIES This section describes the proposed PLC method

over microprocessor PDNs, an overview of the system, and impulse based UWB signaling.

A. Proposed PLC Method The proposed PLC method is shown in Figure 1.

A logic 1 (0) is a positive (negative) pulse superimposed on the supply voltage. For example, the input values on power Pin 1 are 1100 in the figure. The impulse modulated data applied to a power pin (or C4 bump) reaches the PDN, which is

FEASIBILITY STUDY FOR COMMUNICATION OVER POWER DISTRIBUTION NETWORKS OF MICROPROCESSORS

Rajesh Thirugnanam and Dong Sam Ha

Center for Embedded Systems for Critical Applications (CESCA) Bradley Department of Electrical and Computer Engineering

Virginia Tech, Blacksburg Virginia, 24061, USA E-mail: ha@vt.edu

978-1-4577-1617-1/11/$26.00 ©2011 IEEE 118

received by the corresponding Data Recovery (DR) block. A DR block translates received impulses into logic values, and refer to [5] or [6] for such a DR block. DR blocks are placed at the boundary of the PDN in the figure, and the proximity to corresponding power pins reduces noise and interference. However, a DR block may locate at any internal place, as long as it is connected to the PDN. Multiple input data are applied to power pins simultaneously in the figure, and individual DR blocks receive the data applied to the corresponding power pins. A multiple access technique such as Code Division Multiple Access (CDMA) should be employed to send and receive multiple data simultaneously.

DR1

DR2

DR3

DR44

DR43

DR42

Pin1

Pin2

Pin3

Pin44 Pin43 Pin42

1

0

1

0 1 0

…

…

Fig. 1: Simplified overall architecture of the proposed PLC method

B. Overview of the System

The proposed PLC over microprocessor PDNs allows both control and monitoring of internal nodes, and the two-way communication scenario is shown in Figure 2. In order to control an internal node value, an input data is applied to the test/control module. The data propagates through a system board (or PCB), ground/power planes, power pins, the PDN and eventually reaches the intended controlling node or the receiver. Each controlling node has a unique identification number to allow control of individual nodes.

A sensing node enables to monitor the internal node value. A signal transmitted from the transmitter of a sensing node propagates through the opposite direction to reach the test/control module.

SystemBoard

Voltage Regulator

Board Decoupling Capacitor

Test/Control ModuleDie

Package Decoupling Capacitor

SystemBoard

SystemBoard

SystemBoard

Two-way Communication

Tx/Rx#1

Rx#3

Tx/Rx#2

Rx#3

Sensing Node

Sensing Node

Controlling Node

Power Distribution Network

Inside the Die

Fig. 2: Overview of the system

C. Impulse-based UWB signaling Compared to narrowband communication

systems, UWB signaling has several advantages such as high data rate, low average power, and simple RF circuitry [7]. Shannon’s theorem states that the channel capacity C is given as B×log2 (1+SNR), where B is the bandwidth. As the bandwidth B is much larger (on the order of several GHz) for UWB than for a narrowband signal, the SNR can be much smaller for UWB to achieve the same data rate. Therefore, with UWB communications one can recover data, even if the signal power is close to the noise level. In other words, the power level of UWB signals could be at the noise level of a PDN to have little impact to the power integrity.

UWB signaling can be carrier-based or impulse-based, and impulse UWB is more suitable for the proposed application due to its simple hardware [7]. Impulse UWB is based on a train of narrow pulses (which are typically a few hundreds picoseconds). The permissible variations of the power supply voltage for microprocessors are typically within ± 5 %, which is necessary to maintain data integrity. Say, for a microprocessor with 1 V power supply, the amplitude of pulses on the PDN should be less than ±50 mV [8].

III. FEASIBILITY STUDY THROUGH A MEASUREMENT This section describes our feasibility studies

conducted through measurements of Intel microprocessors.

A. Measurement Setup The PDN channel was characterized in the

frequency domain through measurements. Appropriate fixtures required to connect a network analyzer to the PDN is quite complicate. Fortunately, we were able to piggyback on a measurement setup typically used for power supply noise measurements and modify it slightly to suit our needs.

119

The measurement setup is shown in Figure 3. A microprocessor is mounted on a tester board. One port of the network analyzer was connected to a core power supply pin on the tester board and the other port of the network analyzer was connected to a node on the PDN. This setup ensures the measurements to include the power planes in the tester board, the package power planes, the PDN, and all the different decoupling capacitors. A launcher needle used in Time Domain Reflectometer (TDR) measurements to characterize tester board power planes was used to connect one port of the network analyzer to the tester board’s core power supply pin. A probing node was created using Focused Ion Bean (FIB) to expose a node on the PDN. An RF probe connected to the second port of the network analyzer was used to make a contact with the exposed PDN node. Since the microprocessors used for our measurements are in a flip-chip package, the probing node created through the back of the die exposes the second level metal layer (M2) of the PDN, thereby characterizing the PDN channel up to the location, where a transmitter/receive block would be eventually located.

Pentium 4 Tester Board

Core Power Supply Pin

Die

Vcc

RF Probe Adapter

Network Analyzer

Fig. 3: Measurement setup

B. Measurements on Cold 65 nm Pentium and Cold 45 nm Core 2 Duo Dies

The measured scattering parameters (S-parameters) are expressed as the voltage ratio |Vout/Vin| (in percentage) for readability. The transfer function measured on a single sample of a cold 65 nm Pentium processor’s PDN is shown in Figure 4. The transfer function shows the existence of narrow sporadic pass bands above 200 MHz. The largest

pass band and peak propagation is observed around 2 GHz over a 200 MHz band. As expected, the PDN is quite lossy with only about 5~7 % of the signal passing through the PDN in narrow sporadic bands. The signal over 2.5 GHz is nearly completely suppressed to form a stop band.

Fig. 4: Transfer function of a cold 65 nm Pentium PDN

Measurements were carried out on three different

samples of cold 45 nm Core 2 Duo processors and two randomly picked locations on the PDNs. On one sample, one exposed node on the on-chip power grid was damaged during measurements, and therefore only five different transfer functions were measured.

The averaged transfer function is shown in Figure 5. The averaged transfer function shows narrow sporadic pass bands, where about 5~7 % of the input signal passes through the PDN.

Fig. 5: Average transfer function of the cold 45 nm Core 2

Duo PDNs

0 1 2 3 4 5 60

1

2

3

4

5

6

7

8

Frequency (GHz)V ou

t/Vin

(%)

0 1 2 3 4 5 60

1

2

3

4

5

6

7

8

Frequency (GHz)

V out/V

in (%

)

120

There is a very little correlation between the

transfer function measured on the 65 nm Pentium PDN and that for the 45 nm Core 2 Duo PDNs. Further, the large pass band around 2 GHz on the 65 nm Pentium PDN does not exist for the 45 nm Core 2 Duo PDNs. Expectedly, the pass bands move from one generation of processors to the next because of the difference in the package power plane design, the PDN design as well as the difference in the thickness of the metal layers in different process technologies.

C. Spatial and Intra-die Variations The five transfer functions obtained through the

measurements described above and the average transfer function are superimposed in Figure 6. Across different parts and different locations, the transfer functions essentially remain the same with minor differences.

Fig. 6: Spatial and intra-die variation of the transfer functions of cold 45 nm Core 2 Duo (Individual transfer functions are shown in light shade and the average shown in a dark shade)

D. Observations Made from the Measurements Transfer functions of microprocessors are

dependent on whether the part is mounted on the tester board, the tester, or the mother board. Further, since the pass bands can move from one generation of processors to the next as well as depending on the setup, we can conclude that the pulses used for communication should cover entire spectrum of sporadic pass bands observed across different processors and setups. Hence, it is desirable for the pulses to have the bandwidth of about 2 – 2.5 GHz.

IV. CONCLUSION Feasibility of PLC over microprocessor PDNs has

been studied through measurements on Intel Pentium and Core 2 Duo microprocessors. Narrow sporadic pass bands were observed on the PDNs. Pass bands move from one generation of microprocessors to the next generation and depends on the setup. Hence, we conclude that PLC over a microprocessor’s PDN is feasible without disrupting the normal operation by adopting UWB pulses with about 2 – 2.5 GHz of bandwidth.

Our feasibility study for PDNs as a communication channel opens up a myriad of opportunities in testing and debugging. Future study at the system level as well as at the circuit level is necessary to fully exploit the opportunities.

ACKNOWLEDGEMENT This material is based upon work supported by the

National Science Foundation under Grant No. 0811706.

REFERENCES [1] W.C. Chung, D.S. Ha, and H.J. Lee, ‘Dual use of

power lines for data communications in a system-on-chip environment,” Proceedings of IEEE International Symposium on Circuits and Systems, vol. 4, pp. 3355-3358, May 2005.

[2] W.C. Chung, and D.S. Ha, “A new approach for massive parallel scan design,” Proceedings of IEEE International Test Conference, pp. 497-506, November 2005.

[3] S. Galli, A. Scaglione, and K. Dostert, “Guest Editorial - Broadband is power: Internet access through the power line network,” IEEE Communications Magazine, Vol. 41, No. 5, pp. 82-83, May 2003.

[4] R. Thirugnanam, D. S. Ha, and T.M. Mak “On Channel Modeling for Impulse-Based Communications over Microprocessor’s Power Distribution Network,” IEEE International Symposium on Power Line Communications and Its Applications, pp. 355-359, March 2007.

[5] R. Thirugnanam, D.S. Ha, and T. M. Mak, "Data Recovery Block Design for Impulse Modulated Power Line Communications in a Microprocessor," IEEE Computer Society Annual Symposium on VLSI, pp. 153-158, May 2007.

[6] V. Chawla and D.S. Ha, “Dual Use of Power Lines for Data Communications in Microprocessors,” IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pp. 23-28, April 2011.

[7] J. H. Reed (Editor), “An introduction to ultra wideband communication systems,” Prentice Hall, 2005.

[8] Qing K. Zhu, “Power Distribution Network Design for VLSI,” John Wiley & Son, 2004.

0 1 2 3 4 5 60

2

4

6

8

10

12

Frequency (GHz)

V out/V

in (%

)

121