Fast Near-Field Characterization of Integrated Circuits Electromagnetic Interference

Ond ej HARWOT

Dept. of Microelectronics, Czech Technical University in Prague, Technická 2, 166 27 Praha, Czech Republic

ondrej.harwot@fel.cvut.cz

Abstract. This paper describes method for speed improvement of electromagnetic near-field scanning. Using the technique described in this paper both high spatial resolution and high speed of measurement can be achieved. Some applications of near-field scanning are presented and discussed. Near-field scan technique is used for measurement of magnetic field distribution above a passive structure and for analysis of electromagnetic emission of integrated circuit operating in different regimes. Results show good reliability of presented method and its effectiveness for investigation of electromagnetic interference in integrated structures.

Keywords Near-Field Scanning, IC, EMC, IEC 61967, Magnetic Field Probe.

1. Introduction Contemporary integrated circuits (IC) are achieving

extreme level of integration, internal clock frequencies and translation rates. As a result, electromagnetic compatibility (EMC) has gained more significance. The EMC must be considered during IC design as well as later qualification of the IC. Poor EMC design of IC can lead to problem with whole device EMC qualification.

Most of today methods of IC's EMC measurement give only global information about the EMI problem. This approach leads to high speed of measurement, but makes impossible to localize places which generate high EMI or have weak susceptibility. Therefore it is very hard to localize these places and eliminate the problem [1].

The near-field scan method is based on local measurement of field strength at a specific point above the emitting structure [2, 3]. Matrix of measured data can be later transformed to the map of electromagnetic field distribution for particular frequency. Nowadays, this method is part of the IEC 61967 standard [4].

The problem of the method is trade-off between spatial resolution and speed of the test. Especially for large

structures, measurement with high spatial resolution can be very time consuming [5].

Improvement of the near-field method, which speeds up the measurement up to ten times, is presented in this paper. Characterization of passive structure and active IC is shown to validate the proposed method. The electromagnetic emission from Field Programmable Gate Array (FPGA) working in different regimes is presented and analyzed, as well.

2. Theoretical Approach Electromagnetic field consists of six components –

three for electric and three for magnetic field. In near-field scan, it is necessary to measure each of these components separately. Since this paper focuses on characterization of magnetic field, only this task will be discussed.

Magnetic field is usually measured by a loop. Voltage induced in the loop is according to Faraday‘s law:

ldvBSdBdtdldE (1)

where the first term represents the electromotive force inducted by magnetic field variation and the second term is the voltage inducted by movement of the loop in magnetic field.

If the presence of the probe does not significantly disturb the field and the probe is not moving, the voltage Vout inducted in it can be calculated as:

HAfVout 2 (2)

where f is the frequency of measured signal, is the permeability of loop core (usually 0), H is the average magnetic field and A is the area of the loop. Equation (2) can be used only for frequencies below 1 GHz, because for higher frequencies parasitic inductance and capacitance of the loop must be taken into account.

To completely avoid the second term of equation (1), it is necessary to wait 100 – 1000 ms after each move of the probe [5]. This very slows down whole measurement. But if we assume, that the probe moves relatively slowly and the measured field is relatively low, it is possible to

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neglect this term without any effect on the accuracy of measurement.

To prove this premise, let us assume constant speed v of movement and strength B of magnetic field. Then we can calculate the second term of equation (1) as:

ldBvldvB . (3)

Now we can compare equations (2) and (3) and get result that both terms of equation (1) has comparable size for

fav (4)

where a is the length of the square loop side. Therefore if 1x1 mm loop is used for measurement at frequency of 1 MHz, it must move with speed of at least 1 km/s to get a significant inducted voltage.

Single loop is capable to measure magnetic field only in one direction. For total magnetic field distribution two orthogonal components Hx and Hy must be measured. The overall magnetic field Htot can be determined as

22yxtot HHH (5)

where Hx and Hy are two orthogonal components of magnetic field. ICs and PCBs have usually no conductors in the z plane so there is no necessity to measure Hz.

3. Experimental Setup Fig. 1 shows the configuration of the presented

system. It basically consists of a spectrum analyzer, a probe, a position system and a personal computer. The spectrum analyzer has enough low noise floor, so there is no need for using preamplifier. The system is controlled through program written in LabView and measured data are evaluated in Matlab.

Fig. 1. Presented measuring system setup.

Fig. 2. Magnetic field probe schematic.

In the presented setup, the Melles Griot Nanomotion II with spatial resolution of about 50 nm and maximal scan area 25x25 mm is used as positioning system. The maximum moving velocity is about 1 mm/s. The HP 4401b spectrum analyzer is used for signal detection and the probe is made by coax cable RG 174 with a small 0.2 mm2 loop located at its end (see Fig. 2).

Firstly, the commonly used way of near-field scan was implemented. In this application, the probe is placed at a specified position and after selected time interval the strength of the field is measured. During this interval, the average or maximum value of field strength is measured. This method was later used for comparison with the newly proposed one.

The newly proposed method use similar experimental setup as the previously presented one. The main difference is that the probe is moving continually between position xmin and xmax. During the movement, both the field strength and actual position of the probe are measured as fast as possible. The scanning lines have constant distance interval. The result of the new approach is therefore set of lines with known field strength instead of the set of points.

4. Results and Discussion The proposed method was experimentally validated

by measuring magnetic field distribution above passive structure created on PCB and commercially available IC. The first measurement should verify the proposed method while the second one tested IC behavior at different conditions.

4.1 Meander Pattern For testing of the spatial resolution and overall

function of presented method, a meander pattern was used. This pattern was fabricated at common FR4 substrate. The pattern was fed with 0 dBm signal from signal generator.

The scanning area for all measurements was 20x20 mm and the probe was placed 0.5 mm above the PCB surface. Measurement with the stationary probe was made with resolution 0.5 mm. In the moving probe mode, the scanned lines were also in 0.5 mm distance. In this measurement mode, the probe moved about two times faster and ten times more samples of near-field were acquired.

Fig. 3 a) presents total magnetic field distribution over the meander pattern for input frequency of 100 MHz using the stationary scanning mode, while Fig. 3 b) shows the same measurement for the moving probe. On both figures, 17.5x17.5 mm detail of scanned area is shown. On both figures the meander pattern is marked with black lines. It can be observed, that the second result is smoother and gives more accurate field distribution in areas around the corner of the pattern.

a)

b)

Fig. 3. Total magnetic field distribution above meander pattern a) station probe b) moving probe.

4.2 Characterization of IC’s Emission The second measurement was taken above the surface

of commercially available IC. FPGA circuit, which provides unique opportunity for chip EMC investigation, was chosen for this purpose [1]. Advantage of this type of device is that it can be reconfigured to completely different functions without changing the package or PCB parameters.

The test was performed on Xilinx Virtex2 XC2V1000 located on the Avnet development board with DDR1 16Mx16bit memory. The FPGA was configured as SoC containing the OpenRISC OR1200 32bit processor, DDR1 memory controller, UART and GPIO. To resolve the influence of different parts of the system on measured magnetic field, each functional block had its own clocking frequency as shown in Table 1.

System part Frequency [MHz]

Input clock 100

DDR interface 80

CPU 33.3

Tab. 1. Frequency list of the system.

The input frequency was fed to FPGA by only one pin and should not produce any electromagnetic field above other parts of IC. The core of the system was the CPU running at 33.3 MHz. The core occupied 50 % of FPGA resources and was not directly connected to any output pin. Finally, the DDR core was relatively small, but produced high frequency EMI above many I/O pins.

The measured magnetic field is presented in Fig. 6 and 7. In all figures, the FPGA package boundary (BGA with 256 pins) and silicon die size are highlighted. There are also presented all pins of the package. Selected group of pins are highlighted with different colors. These colors are summarized in Tab. 2.

Pin group Color Figure

Ground Black 4, 5

FPGA’s internal voltage Cyan 4

DDR address Red 5

DDR data Cyan 5

DDR clock White 5

Tab. 2. Colors used in Fig. 4 and 5.

a)

b) Fig. 4. Magnetic field above FPGA measured at 33.3 MHz:

a) running processor b) halted processor.

In Fig. 4 a), the magnetic field distribution above the chip at 33.3 MHz is presented. The field is mainly located above power pins supplying FPGA’s internal logic. There is also high filed strength near common pins, which can be explained by electromagnetic field coupling inside the package.

In Fig. 4 b), result of the measurement in identical configuration is presented, but in this case the CPU was in halt state. As clearly seen, only a weak field can be observed above silicon die.

Fig. 5 shows distributions of magnetic field measured at 80 MHz. In the first test (Fig. 5 a), the pattern 0x55AAAA55 was continually written to and read back from DDR memory. As expected, the highest magnetic field distribution is above data and clock pins. One can also see that the field is stronger above lower address pins (which are right) compared to higher address pins.

Fig. 5 b) shows magnetic field distribution for similar setup, but without any access of FPGA to DDR memory. The result is similar but significant difference can be observed above address pins. To explain this quite unexpected result, the internal structure of the DDR controller IP core was analyzed. The analysis showed that there was an error in core design. This error causes, that the core continues sending data on DDR data bus even if there is no transaction. This example shows that high-resolution near-field scan can be very useful for IP cores verification in light of EMI.

5. Conclusion Novel system for electromagnetic near-field scan

measurement was presented. The system consists of a common spectrum analyzer, positioning system and probe, but the probe is continuously moving above the tested device, instead of measuring each point separately. The method provides better resolution and is up to ten times faster compared to approaches published previously.

Magnetic field distribution above meander pattern and FPGA circuit was measured and analyzed. Results obtained on the meander pattern show on good spatial resolution and high speed of novel approach. Near-field data scanned above FPGA was used to analyze IC behavior under several conditions. It was shown that high-resolution near-field scan can be very useful for debugging IP core design in the light of EMI.

Acknowledgements This work was supported by the Grant Agency of the

Czech Technical University in Prague, grant No. SGS 10/280/OHK3/3T/13 and by the research program MSM 6840770014.

a)

b) Fig. 5. Magnetic field above FPGA measured at 80 MHz:

a) DDR read and write b) DDR not operating.

References [1] DONG, X., DENG, S., HUBING, T., BEETNER, D., Analysis of

chip-level EMI using near-field magnetic scanning, 2004 International Symposium on Electromagnetic Compatibility, EMC 2004, vol.1, no., pp. 174- 177 vol. 1, 9-13 Aug. 2004.

[2] HAIXIAO WENG, BEETNER, D.G., DUBROFF, R.E., Predicting TEM cell measurements from near field scan data, 2006 International Symposium on Electromagnetic Compatibility, EMC 2006, vol. 3, pp. 560-564, 14-18 Aug. 2006.

[3] XIAOPENG DONG, SHAOWEI DENG, BEETNER, D. G., HUBING, T.H., VAN DOREN, T.P., Determination of high frequency package currents from near-field scan data, 2005 International Symposium on Electromagnetic Compatibility, EMC 2005, vol. 2, pp. 679-683, Aug. 2005.

[4] IEC 61967-3: Integrated circuits - measurement of electromagnetic emissions, 150 kHz to 1 GHz - surface scan method.

[5] BAUDRY, D., ARCAMBAL, C., LOUIS, A., MAZARI, B., EUDELINE, P., Applications of the Near-Field Techniques in EMC Investigations, IEEE Transactions on Electromagnetic Compatibility, vol. 49, no. 3, pp. 485-493, Aug. 2007.