FPGA Based Analysis and Multiplication of Digital Signals

Zulfikar M. Yusuf #*1, Shuja A. Abbasi #2, A. R. M. Alamoud #3 #Department of Electrical Engineering

King Saud University, Riyadh - 11421, Saudi Arabia Email: {1zulfikarsafrina@yahoo.co.id, 2abbasi@ksu.edu.sa, 3alamoud@ksu.edu.sa}

* Department of Electrical Engineering Syiah Kuala University, Banda Aceh - 23111, Indonesia

Abstract—The importance of processing of digital signals has dramatically increased due to widespread use of digital systems. A new FPGA based technique for processing of two digital signals to generate a new signal as a product of two signals is presented. The technique is based upon the use of orthogonal functions to describe digital signals.

Keywords—FPGA, hardware realization, Walsh functions, simulation.

I. INTRODUCTION Digital signal processing is a well established area of

research. Digital signals find a wide spread use in many areas of application like information technology, electronic communication, computers, microprocessors, control and instrumentation etc. This is mainly because of inherent advantages of digital processing of signals. The need of techniques of analysis and processing of multiple digital signals is therefore well established.

The use of many orthogonal sets of functions and polynomials for representation of signals is well known to scientists and engineers since long. Such sets include trigonometric functions, Bessel functions, Hermite polynomials, Legendre polynomials, and a host of others. But, trigonometric functions which are inherently encountered in Fourier analysis have played a dominant role in applications to engineering and science problems [1], [2].

The selection and use of any orthogonal set of functions hinges primarily on the type of problem under study and the consequent amenability of the problem to the specified set. It has been observed that the use of Walsh functions to describe digital signals is very helpful in analyzing and processing of periodic digital signals [3]. Abbasi and Alamoud [4] have demonstrated the use of orthogonal functions for representation and realization of digital signals using orthogonal functions. A more detailed account of hardware realization using orthogonal functions is presented by Qasim and Abbasi [5].

Many different techniques for generating a signal have been used in past [6], [7], [8]. The use of orthogonal functions may be made to generate a spectrum for a given digital signal much the same way as is done for analogue signals using Fourier

analysis. Once a spectrum is available, analysis, processing and regeneration of periodic digital waves is possible [9], [10]. In the present work, this concept is practically implemented using state-of-the-art hardware realization techniques. The problem of FPGA based generation of a new signal as a product of two periodic digital signals is specially addressed.

II. ORTHOGONAL FUNCTIONS AND THEIR USE IN PROCESSING OF PERIODIC DIGITAL SIGNALS

Orthogonal functions are a set of discrete valued functions such that when any two of them are multiplied and integrated over a period, the result is zero. The selection and use of any orthogonal set of functions depends mainly upon the type of problem under study. For instance, some sets results in a simple and useful solution to a certain problem, where as others give complicated and less useful forms of solution.

The Walsh functions and the Rademacher functions are of particular interest for digital signal processing applications. The most important factor responsible for their increased use is that they have a digital nature. These functions and their transforms are important analytical tools for signal processing and have wide applications in many areas. These functions are easy to generate and control using relatively simple hardware and thus are ideal for real-time waveform generation and synthesis of different periodic waveforms [11], [12].

In original definition of Walsh functions, Walsh used a rather unattractive notation which is inconvenient for analytical considerations [1]. However, his definition is largely preferred by engineers and applied scientists for computational purposes in particular [2]. Various investigators of Walsh theory have formulated several other forms of defining or generating Walsh functions [9], [10], [13]. These investigations had two main objectives. The first is to obtain a simple and efficient method of generating Walsh functions, and employing them for computational purposes particularly in using digital computers. The second objective is to induce a definition which allows for simple and useful analytical or mathematical manipulations.

We preferred a definition based upon derivation of Walsh functions from Rademacher functions which is found to be

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2010 Second International Conference on Advances in Computing, Control, and Telecommunication Technologies

978-0-7695-4269-0/10 $26.00 © 2010 IEEEDOI 10.1109/ACT.2010.20

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more appropriate for hardware implementation. The Rademacher functions are defined as follows [1]:

),22(sin),1( xSgnxn n n = 0,1,2,…0 x 1 (1) Where, 1,0 x and the signum function Sgn(y) is

defined by:

0 , 10 , 1

Sgny

yy (2)

The definition of Rademacher functions may be extended over the whole non-negative real line by the periodicity property [1]:

xx ,01,0 (3)

Rademacher functions form an orthogonal, but incomplete set. Actually, they form a subset of the Walsh set of functions. Furthermore, the function xn, is right-continuous; i.e. [1].

xnxn ,lim0

, (4)

The Walsh functions are defined in terms of product of Rademacher functions as [1]:

1,0 , ,10 ininxi

N

in,x (5)

N

ii

i nn0

2 (6)

01

0

2

0,lim dx

N

nxnnAxf

N (7)

A function f(x) may be represented as a Walsh series given by [1]:

0,

nxnnAxf (8)

The expansion coefficients An are evaluated as [1]:

Tdx

Tx

nxfTnA

0,1 (9)

If a function h(x) is defined as a product of two functions given by:

xgxfxh (10) Where the function f(x) has the Walsh series expansion as

in (8) and g(x) has the following Walsh series expansion:

0

,n

n xnBxg (11)

The Walsh expansion of h(x) is then given by [1]:

0

,n

n xnCxh (12)

Where the expansion coefficients Cn are computed as [1]:

0mmmnn BAC (13)

III. ANALYSIS, SYNTHESIS AND MULTIPLICATION OF SIGNALS

Initially, the Walsh coefficients for both digital signals are calculated separately using (9). For multiplication of the two signals, the expansion coefficients for output signal are evaluated using (13). These coefficients are used to regenerate the output signal using (8). A direct theoretical analysis using (8), (9) and (13) performed to find the maximum number of bits required to represent expansion coefficients for the output signal, yields the following results.

Max_bits = 2{(n-1) + log2 (s)} +2 log2 (s) +1 (14)

Where n is number of bits in the input signal and s is the number of samples.

However, in order to obtain a more efficient VHDL coding for generation of signals, the maximum number of bits required according to (14) is more carefully analyzed using MATLAB. It was found that, in practice, the expansion coefficients of the output signal do not require the number suggested by (14). Instead, the number given by the following equation is enough.

Max_bits = 2{(n-1) + log2 (s)} +1 (15)

Further, according to arithmetic rules, the number of bits required for the output signal obtained from multiplication of two numbers with n bits each is given by:

output_bits = 2(n-1) + 1 (16)

IV. VHDL MODELLING AND HARDWARE IMPLEMENTATION Hardware implementation of Analysis, Synthesis and

multiplication of signals has been done using VHDL. A comprehensive code is developed for efficient realization based upon the flow chart given in Figure 1.

Figure 1. Process of VHDL Coding for Hardware Implementation

Generation of Rademacher Functions

Generation of Walsh Functions

Generation of Spectrum for Individual Signals

Processing of Expansion Coefficients for Generation of Spectrum for Output Signal

(Multiplication)

Generation of Output Signal

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Any number of bits may be used for representation of digital signals. For demonstration purposes, all input signals are taken as 8-bit signed numbers with 8 samples per period. FPGAs from Xilinx are chosen and the design is done using Xilinx ISE 9.2i system of softwares. The spectrum of the digital signals is plotted as expansion coefficients Vs the order of the Walsh functions.

V. RESULTS AND DISCUSSION FPGA based design and implementation has been done.

The design is targeted to Spartan XC3s2000 chip. The device utilization summary is given below:

Selected Device : 3s2000fg456-5

Number of Slices: 3429 out of 20480 16%

Number of Slice Flip Flops: 892 out of 40960 2%

Number of 4 input LUTs: 6249 out of 40960 15%

Number of IOs: 35

Number of bonded IOBs: 35 out of 333 10%

Number of MULT18X18s: 40 out of 40 100%

Number of GCLKs: 3 out of 8 37%

Xilinx ISE simulator is used to demonstrate the results of various processing steps. A simple mechanism of feeding input signals is used. The two input signals s1 and s2 are shown in Figure 2. The simulation shows the results at the signal entry stage.

Figure 2. Entry of two Digital Signals

The next step after signal entry is to determine the digital spectrum. Figures 3 and 4 show the spectrum for the first and second signals s1 and s2 generated through FPGA implementation.

Figure 3. Spectrum of first signal

Figure 4. Spectrum of second signal

The expansion coefficients for the output signal (s1 * s2) are evaluated within the VHDL code using (13). If A, B and C are the Walsh coefficients of s1, s2 and output signal respectively, then for s=8, equation (13) can be re-written as follows:

C0=A0*B0+A1*B1+A2*B2+A3*B3+A4*B4+A5*B5+A6*B6+A7*B7

C1=A1*B0+A0*B1+A3*B2+A2*B3+A5*B4+A4*B5+A7*B6+A6*B7

C2=A2*B0+A3*B1+A0*B2+A1*B3+A6*B4+A7*B5+A4*B6+A5*B7

C3=A3*B0+A2*B1+A1*B2+A0*B3+A7*B4+A6*B5+A5*B6+A4*B+

C4=A4*B0+A5*B1+A6*B2+A7*B3+A0*B4+A1*B5+A2*B6+A3*B7

C5=A5*B0+A4*B1+A7*B2+A6*B3+A1*B4+A0*B5+A3*B6+A2*B7

C6=A6*B0+A7*B1+A4*B2+A5*B3+A2*B4+A3*B5+A0*B6+A1*B7

C7=A7*B0+A6*B1+A5*B2+A4*B3+A3*B4+A2*B5+A1*B6+A0*B7

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The spectrum for the output signal is shown in Figure 5.

Figure 5. Spectrum of output signal

The values of expansion coefficients forming the spectrums are shown in tabular form in Table 1.

TABLE I. VALUES OF EXPANSION COEFFICIENTS

Coefficients s1 s2 s1 * s2

A0=21.75 B0= -0.125 C0=945.1 A1=17.25 B1= 22.375 C1=1173.1 A2=10.75 B2= -0.125 C2=1137.1 A3=8.75 B3= 54.375 C3=1429.1 A4=5.75 B4= 0.125 C4=539.9 A5=4.75 B5= 22.625 C5=671.9 A6=2.75 B6= 0.125 C6=347.9 A7=2.25 B7= -9.375 C7=415.9

The FPGA implementation is used for further study of

processing of these signals. It is obvious that accuracy of signals increases with increase in the number of samples used in quantizing the signals at the expense of more hardware. This increase in hardware also results in more delays which reduces the maximum usable frequency. A quantitative study is performed by hardware implementation with 4, 8 and 16 samples per period using 4-bit, 6-bit and 8-bit representation of signals. Timing analysis tool available in Xilinx ISE 9,2i software is used to determine all the delays and then obtaining the critical path and critical path delay. The results are presented in Table II. It is clearly seen that increasing the number of samples used and increasing the number of bits decrease the maximum usable frequency.

TABLE II. VARIATION OF MAXIMUM USABLE FREQUENCY

Number of Samples

Maximum Frequency (MHz) 4 bits input 6 bits input 8 bits input

4 131.264 127.547 119.987 8 61.031 60.777 59.968 16 29.974 29.232 29.044

The behavioral simulation results of multiplication are

given in Figure 6. It has been observed that 100% accuracy is achieved in all the cases. This is the advantage of direct digital processing.

Figure 6. Behavioral Simulation of Multiplication of Signals

Timing simulation in all cases is perfomed and it is found that the results are satisfactory with the added loads of parasitics. The results are shown in Figure 7.

Figure 7. Timing Simulation of Multiplication of Signals, (s1 * s2)

A more closer examination of timing simulation results is presented. Figure 8 shows the results after zooming at appropriate point to determine the delay. It has been found that the delay is about 6.7 ns at most of the places.

A timing analyzer tool available in Xilinx ISE 9.2i is used to calculate all the delays and the critical path delay. The results are shown in Table III. The critical path delay is found to be 6.761 ns.

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Figure 8. Close Examination of Timing Simulation Results

TABLE III. TIMING ANALYSYS RESULTS

Destination Clk (edge) to Pad (ns)

Internal Clocks

Clock Phase

output<1> 6.506 clk_BUFGP 0.000 output<2> 6.506 clk_BUFGP 0.000 output<3> 6.592 clk_BUFGP 0.000 output<4> 6.592 clk_BUFGP 0.000 output<5> 6.549 clk_BUFGP 0.000 output<6> 6.549 clk_BUFGP 0.000 output<7> 6.761 clk_BUFGP 0.000 output<8> 6.761 clk_BUFGP 0.000 output<9> 6.724 clk_BUFGP 0.000

output<10> 6.724 clk_BUFGP 0.000 output<11> 6.747 clk_BUFGP 0.000 output<12> 6.747 clk_BUFGP 0.000 output<13> 6.713 clk_BUFGP 0.000 output<14> 6.713 clk_BUFGP 0.000 output<15> 6.725 clk_BUFGP 0.000

VI. CONCLUSIONS The work describes a new technique for multiplication of

two periodic digital signals. The use of orthogonal functions is made for the representation of signals. Each signal is converted

into a series of Walsh functions. A spectrum in terms of expansion coefficients is generated. This spectrum is used for the analysis and subsequent direct processing of signals. Hardware implementation targeted to Xilinx FPGAs has been done. Results with 8-bits and 8 samples per period are presented and found to give 100% accuracy. A quantitative assessment of maximum usable frequency with number of bits and number of samples is presented. It is concluded that the technique can be efficiently used for direct multiplication of two digital signals using hardware implementation techniques.

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