Dual-Band CMOS Transceiver with Highly Integrated Front-End for 450Mb/s 802.11n systems

Shai Gross, Tzvi Maimon, Fabian Cossoy, Mark Ruberto, Georgi Normatov, Alexander Rivkind, Nikolay Telzhensky, Rotem Banin, Ori Ashckenazi, Assaf Ben-Bassat, Sharon Zaguri, Gabriel Hara,

Mario Zajac, Nir Shahar, Shay Shahaf, Hani Yousef, Eyal Mor, Yishai Eilat, Anna Nazimov, Zeev Beer, Amir Fridman and Ofir Degani

Intel Corporation, Mobile Wireless Group, Haifa, Israel

Abstract — A 3-stream, 802.11n WLAN MIMO

transceiver, with fully integrated PAs and LNAs in both 2.4GHz and 5GHz bands, and a T/R switch in the 2.4GHz band, was implemented in a standard 90nm CMOS technology. The transmitter achieves an EVM of -28dB at output power of 19dBm and 17dBm in the 2.4GHz and 5GHz bands, respectively. The transmitter power consumption per Mb of data, in 3-stream mode, is 3.7mW/Mb and 4.5mW/Mb in the 2.4GHz and 5GHz, respectively. This is four times lower comparing to the single stream (SISO) mode. The receiver NF is 4dB in both bands, and power consumption is 1.6mW/Mb and 1.7mW/Mb, in the 2.4GHz and 5GHz bands, respectively.

Index Terms — IEEE 802.11n, WLAN, MIMO, CMOS, RF transceiver, 3x3, integrated FEM, integrated LNA, integrated PA, Integrated T/R switch, RC filter, frequency synthesizer.

I. INTRODUCTION

The widespread acceptance of 802.11n products has been driven by users seeking to exchange information in a timely manner, stream High Definition (HD) video, and handle voice, video, and data traffic concurrently. From power consumption point of view, the power per Mb of data is significantly lower compare to SISO systems. This has led to the adoption of 802.11n as a key technology component in both consumer and enterprise notebook PCs. While the 802.11n standard supports up to 4 data (spatial) streams, capable of delivering up to 600Mb/s, the most common high throughput products in the market today supports only two data streams, delivering 300Mb/s. Naturally, supporting more data streams, directly impact the silicon and package size, board complexity, and BOM, which eventually translates to higher cost. In recent years, a major effort has been done [1]-[3] in order to reduce the cost of the WiFi radio, by integrating portions of the FEM. Described in this paper, is a highly integrated 3x3, dual band transceiver, capable of delivering a throughput of 450Mb/s, with an integrated PAs and LNAs in both the 2.4GHz (aka LB) and 5GHz (aka HB) bands, and a T/R switch in the LB.

Supporting high MIMO data rates imposes stringent requirements from such a transceiver. Having 3 power amplifiers (PAs) working simultaneously on the same die, introduces a new level of design complexity. The design would need to overcome all reliability issues, keeping the total power consumption low and still be linear enough in order to meet the required EVM and mask requirements. Furthermore, having multiple PAs in close proximity exposes the adjacent chains to a risk of cross talk, which can significantly degrade the MIMO performance. These challenges among others, coupled with the need of keeping the die size and pin count as low as possible, are been addressed in the transceiver presented in this paper.

Section II of this paper describes the high level architecture of this transceiver. Section III discusses the different blocks implementation and challenges, followed by measurements results presented in section IV.

II. ARCHITECTURE

Fig.1 shows high level description of the transceiver block diagram. For brevity, all peripheral content such as LDOs, various calibration features, and biasing systems, were omitted.

The radio consist of three identical, direct conversion transceivers, where each transceiver has two RF chains (one for each band), a LO generation, and a shared BB filter for both TX and RX paths.

The HB and LB chains consist of integrated PAs, and LNA. The LB chain also includes an integrated T/R switch, leaving only a passive balun filter as non-integrated. In the receive path, the signal from the antenna is amplified by a programmable gain, single-stage LNA, passing through a TX/RX selector and down converted using a passive quadrature mixer. The down converted signal is then mux’ed to the 5-pole filter, and a programmable gain amplifier before going to the ADC.

In the transmit path the input signal is mux’ed to the same filter as the receiver and from there, to the TX programmable gain amplifier. It is then up-converted with a passive quadrature mixer and routed through a TX/RX

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selector to the RF TX chain. The first stage of each chain is a programmable gain, RF amplifier, followed by a fixed gain driver amplifier and finally a power amplifier.

The LO generation is based on a fractional-N synthesizer using a 40MHz reference clock. The VCO output frequency range is between 3.2GHz and 4GHz, which is routed to all three chains and multiplied locally by 3/4 or 3/2 for the LB and HB chains, respectively.

Fig. 1. Transceiver block diagram.

III. CIRCUITS IMPLEMENTATION

A. Transmitter

Having three, simultaneously working PAs, integrated on the same die, impose a variety of challenges. The main challenge is to design a PA, which on one hand, meets the low-data rate spectral masks in SISO mode with high output power, while on the other hand, can reach -28dB EVM for 3x3 MIMO with good enough efficiency to keep the overall power consumption within the limits. This was mitigated by having two operational modes of the PA. In the first mode, the PA operates at a class-A bias point to meet the CCK spectral mask and band-edge requirements with good linearity for SISO. The second mode is a low linearity mode, where the PA operates at a class-AB bias point for higher efficiency, which enables all three PAs to work simultaneously with lower power consumption. In order to improve the PA nonlinearities inherent in a class-AB mode of operation, a digital pre distortion (DPD)

algorithm is used. Fig. 2 shows the TX chain EVM performance as a function of output power. Implementing the DPD algorithm on the class-AB PA, achieved an EVM of -28dB at output power of 19dBm (PA efficiency of 18%) and 17dBm (PA efficiency of 17.5%) in the LB and HB, respectively. The Psat of the PAs was designed to be 26dBm, in order to meet the requirement for output power without over designing the Psat and ultimately degrading PAE.

Fig. 2. EVM vs. Output power, with and without DPD for various channels in both frequency bands.

In order to achieve flat gain and Psat response in the HB, all the matching networks were designed using transformers, allowing very wide-band impedance transformation. Shown in Fig. 3, the simulated gain and P4dB variance across the 700MHz bandwidth is ±0.75dB. The PA employs a standard threshold, thin-gate oxide common-source (CS) device and a thick-gate oxide common-gate device, in a quasi-differential cascade topology for improved reliability and performance. The driver and power amplifiers are working from a 3.3V supply.

Fig. 3. HB TX gain and output power across the full band frequency.

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2.412G EVM no DPD2.412G EVM w DPD5.17G EVM no DPD5.17G EVM w DPD5.825G EVM no DPD5.825G EVM w DPD

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B. Receiver

LNAs of both bands have a triple cascade topology [1] resulting a highly unilateral amplifier. It has 4 coarse gain steps of 6dB, using current steering mechanism. By using the triple cascade topology there is a better isolation between the current steering branches and the input of the amplifier, thus reducing the impact of the different gain steps on the input matching. The down conversion is done via passive direct conversion quadrature mixer. The LB receiver has an integrated low loss T/R switch, based on the topology described in [4], were the RX side of the switch is part of the LNA matching network. The receiver dynamic range (in both bands) is 60dB, with gain step resolution of 1.5dB. The receiver NF is 4dB in both bands. Sensitivity is better than -90dBm for the low data rates, and better than -64dBm for high data rate MIMO. Out-of-channel IP1dB of -14dBm provides sufficient immunity to interferes.

C. Analog/BB Circuits

The Rx/Tx shared filter has five poles, implemented by a first pole in a trans-impedance stage, and two bi-quads stages, each having two complex poles. The filter is optimized to improve interferers rejection, and meet the requiring group delay, and in-band flatness.

The filter has two modes of Band Widths (BW) operation, 10MHz and 20MHz, which are configurable with two banks of capacitors with build-in process variations compensations. A DC canceling DAC is connected to the filter input. As shown in Fig. 1, a multiplexer is used before the RXPGA input. The purpose of this MUX is to connect a variety of radio testing signals to the ADC, and enable BB loop back path.

D. LO Generation

A single 3.2GHz - 4GHz LC VCO is used to generate the required frequency source for both the LB and HB. The VCO employ a 5-bit digital switched capacitors bank for coarse tuning, and a varactor for fine tuning. The VCO coarse tuning is done by an automatic tuning algorithm that is PVT (Process, Voltage, Temperature) variation resistant and ultra fast, converging within <10µSec.

The VCO is locked by a fractional-N PLL. The PLL reference is a 40MHz crystal oscillator with integrated programmable load capacitors for frequency calibration. The PFD-CP incorporates a digital lock detect circuit and dynamic charge pump current control to improve transient performance. The PLL feedback uses a custom digital CMOS Prescaler and a digital fractional divider.

The VCO frequency is distributed to each transceiver chain and multiplied locally by 3/2 or 3/4 for the HB or

LB, respectively. The VCO signal passes through V to I converter, and the current is distributed by means of differential traces to the three chains. Since the receiver uses a direct conversion architecture, it is extremely important to reduce electromagnetic coupling between the LO and the receiver’s signals, in order to minimize DC offset. For this reason, special attention is given to the floor planning of the LO Generation (LOG) inductively loaded mixer and buffer, along with careful design for low currents to minimize the electromagnetic coupling.

IV. MEASUREMENT RESULTS

The transmitter EVM (with DPD) is -28dB@19dBm and -25dB@19.7dBm for LB, and -28dB@17dBm and -25dB@18.5dBm for HB. For an EVM of -28dB, the DPD algorithm improves the output power of the integrated PAs by 3-4dB. Output power of LB PA pass CCK spectral mask requirements at 18dBm and OFDM (HT-20/40) spectral mask at 20.4dBm/18.6dBm. HB PA pass OFDM (HT-20/40) spectral mask at 18.6/17.3dBm.

The PAs reliability was confirmed through accelerated aging testing procedure. All 3 PAs were toggled together, in a multiple units, between ON and OFF repeatedly for 170 hours, under extreme supply voltage and ambient temperature conditions, while monitoring their bias point and 23dBm output power. The measured data showed no noticeable degradation in the output power, and only 2% drop in the current consumption from start to end. This assures proper operation over the life time of the product.

One way to look at the benefit of using multi stream system is the significant reduction in power consumption per (Mega-bit) Mb of data. In the 802.11g mode (SISO) the transmitter discussed in this paper, consumes 15.8mW/Mb and 17.3mW/Mb in the LB and HB, respectively, compare to 3.7mW/Mb and 4.5mW/Mb, in the MIMO 3x3 mode. The receiver consumes, in the 3x3 mode, 1.6mW/Mb and 1.7mW/Mb for the LB and HB, respectively. In both, transmit and receive, the power consumption during 3x3 mode is higher at any given time, however, for a given amount of data, it actually consumes 4 times less power, compare to SISO mode.

Synthesizer lock time, including VCO automated band selection mechanism, takes less than 20uS, and integrated phase noise is better than -46dBc in the LB, and -38.5dBc in the HB, across the whole bands.

The effective throughput in the 5.24GHz channel (3-stream, HT-40, GI=800nS), shown in Fig. 4, reaches more than 260Mbp/s.

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TABLE I PERFORMANCE SUMMARY

Parameter LB H

RX sensitivity

6Mbps -92 -54Mbps -74 -450Mbps -66 -

RX NF 4 RX power consumption

54Mbps 6.4 7450Mbps 1.6

TX Psat 26.8 2

TX output power

-19dB EVM 21.6 2

-25dB EVM 19.7 1

-28dB EVM 19

CCK 18 NOFDM (HT-40) 18.6 1

TX power consumption

54Mbps 15.8 1450Mbps 3.7 4

Integrated phase noise < -46 < Supply 1.8V, 3.3V Technology 90nm CMOS Die size 25mm² Package QFN dual-row Standard 802.11a/g/n, MIMO, 3x3,

Fig. 4. Effective throughput (3x3, HT-40, G

V. CONCLUSION

A highly integrated, dual band, 3x3 (3transceiver with integrated PAs, LNAs animplemented in a standard 90nm CMOS tTX chain can deliver an output power17dBm in the LB and HB, respectively,28dB.

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Fig. 5. Microphotograph of the silico

ACKNOWLEDGEM

The authors would like to thanksilicon validation team, which are design process. The authors wouldback-end, validation, integration, teams for their support.

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[2] A. Afsahi, A. Behzad, V. MagooIntegrated Dual-Band Power ABaluns in 65nm CMOS for an SoC” IEEE RFIC Symp. Dig, pp.36

[3] M. Terrovitis, M. Mack, J. HwangB. Wang, S. Mehta, D. Su, “A lxl Fully Integrated RF Front-end UtiProceedings of ESSCIRC, 2009.

[4] A.A. Kidwai, C.T. Fu, R. SadhJensen, S. Taylor, “An Ultra-LSwitch fully integrated with 80290nm CMOS” IEEE RFIC Symp

80 85 90 95 100

TransmitterReceiver

QAM, 3 stream signals, , and HB, respectively. es less than 1.7mW/Mb r consume 3.7mW/Mb B, respectively. Fig. 5 e chip. Manufactured in ze of 5mm X 5mm, and

on die.

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k the layout team and an integral part of the also like to thank the, Q&R, and production

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nuel Cohen, Yishai Eilat, Nikolay Telzhensky, Tzvi em Banin, Ori Ashkenazi, uri, Gabriel Hara, Mario mir Fridman, Richard Lin, Band CMOS Transceiver

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