Power Saving Control Strategies and Their Implementation in DC/DC Converter for Data and

Telecommunication Power Supply

Rais Miftakhutdinov Power Supply Control Group

Texas Instruments Inc. Cary, NC 27518, USA

r-miftakhutdinov1@ti.com, rais@ieee.org

Abstract— The paper focuses on promising topologies and control strategies to meet strict power saving and efficiency requirements over wide output power range demanded by new regulations and trends in data and telecommunication industry. The optimal control algorithm for phase shifted ZVS DC/DC converter is described implemented in new IC controller. Some practical design recommendations are provided allowing zero voltage switching at all operating conditions. The advantages of suggested control strategy are verified by test results based on 95.3% efficient, 12-V, 660-W output DC/DC converter for server power supply.

I. INTRODUCTION Today’s approach to data and telecommunication power

supply design focuses on power saving and efficiency increase over wide output power range demanded by new regulations and industry trends [1], [2]. Section II of the paper provides brief review of new power saving regulations for server and telecom power supplies and sets the efficiency design goals for post-PFC isolated DC/DC converter. To meet these challenging efficiency and power saving requirements, few promising power stage topologies are available including asymmetrical half-bridge, LLC resonant and phase-shifted full-bridge [3]-[5]. Pros and cons of these topologies along with the review of possible control strategies are discussed in Section III. Section IV describes the new optimal control algorithm for the phase shifted ZVS converter providing power saving and high efficiency over entire output power range and the related IC controller, where this algorithm is implemented. Section V focuses on aspects of providing zero-voltage-switching (ZVS) over wide operating conditions for the phase shifted converter using new CoolMOS® or similar technology for primary-side high-voltage power FETs. Advantages of suggested control algorithm and validity of ZVS design recommendations are verified in Section VI by the test results of 95.3% efficient, 12-V, 660-W output DC/DC converter prototype designed for the server power supply.

II. STRIVE FOR EFFICIENCY AND POWER SAVING High efficiency was always important for data and

telecommunication power supply to achieve high power density and improve thermal performance. So far, only high efficiency at maximum power was required because it determines reliability, size and cost of equipment and cooling. Recently the focus is shifted on energy saving and high efficiency over the entire output power range. This approach reduces the overall power consumption, because data and telecommunication systems operate significant amount of time at mid and light loads. Worldwide movement for “Green power” and energy saving has resulted in new standards for increased efficiency over wide output power range. One example is ENERGY STAR®, which is a joint program of the U.S. Environmental Protection Agency and the U.S. Department of Energy. The version 1 of ENERGY STAR® Program Requirements for Computer Servers, which is effective since May 15, 2009, sets the efficiency and power consumption requirements for server power supplies [1]. Table I shows efficiency requirements at 10%, 20%, 50% and 100% output power of single-output AC/DC and DC/DC converters set force in this Program. The typical front-end server power supply includes PFC followed by an isolated DC/DC converter. Many server power supplies also include 5-V standby power supply. Thus, the PFC and standby power supply efficiency and losses have to be taken into account while setting the design goal for the post-PFC converter.

TABLE I. EFFICIENCY REQIREMENTS FOR SINGLE OUTPUT AC/DC OR DC/DC SERVER POWER SUPPLIES

Rated Output Power

10% Load

20% Load

50% Load

100% Load

≤ 500 W 70% 82% 89% 85%

501 – 1000 W 75% 85% 89% 85%

> 1000 W 80% 88% 92% 88%

978-1-4244-4783-1/10/$25.00 ©2010 IEEE 1897

TABLE II. EFFICIENCY DESIGN GOALS FOR PFC, STANDBY POWER SUPPLY AND 660-W DC/DC CONVERTER IN SERVER POWER SUPPLY

Rated Output Power

10% Load

20% Load

50% Load

100% Load

Efficiency from Table 1 75% 85% 89% 85%

AC/DC Efficiency 80.8% 88.8% 90.5% 85.1%

Overall Power Consumption 89 W 157 W 376 W 788 W

PFC Efficiency 95.3% 96.4% 97.6% 97.7%

PFC Output Power 85 W 151 W 367 W 770 W

Standby Power 6 W 7 W 10 W 10 W

Standby Power Efficiency 80% 82% 85% 85%

Standby Power Consumption 7.5 W 8.5 W 12 W 12 W

DC/DC Input Power 77.5 W 142.4 W 355 W 758 W

DC/DC Output Power 66 W 132 W 330 W 660 W

DC/DC Efficiency Goal 85.2% 92.7% 93% 87.1%

Table II shows power distribution and efficiency goals for PFC, 660-W isolated DC/DC converter and 5-V, 2-A standby power supply as parts of the 670-W server power supply. The Table II is helpful to compare and optimize efficiency design goals of each part of the power supply and ensure the design meets overall power supply requirements. From Table II, the efficiency design goals for the post-PFC major DC/DC converter are 87.1% at 100% load, 93% at 50% load, 92.7% at 20% load and 85.2% at 10% load. Next step for the DC/DC converter design is the selection of proper power stage topology and control algorithm to meet the efficiency goals over the entire output power range.

III. DC/DC CONVERTER TOPOLOGIES AND CONTROL STRATEGIES

Topology selection of the post-PFC isolated DC/DC converter is critical for the overall power supply efficiency. The selection criteria must take into account the trade offs and challengers of maintaining required efficiency at mid and low output power range. It is desirable that the selected topology allows different control modes, optimal for the highest efficiency at specific output power conditions. Usually, the ZVS allowing topologies are preferable in such applications because of the relatively high input voltage range, from 350 V to 420 V. Potential candidates include phase shifted full-bridge, asymmetrical half-bridge, LLC resonant converter and variations of these topologies [3]-[5]. The optimal topology selection depends on the control strategy. Because of that consider first possible control algorithms allowing power saving and high efficiency over wide output power range. These control algorithms and approaches are listed below.

• Interleaving of few phases for better current and temperature distribution at maximum output power with gradual phase shedding when the load decreases;

• Synchronous rectification using MOSFETs with the diode emulation technique at light load to avoid current circulation. It could be beneficiary to shut off the drive circuit of rectifier MOSFETs at very light load where the drive losses exceed the conduction losses. Performance of synchronous rectifier significantly depends on accurate timing between the primary and secondary side switches;

• Proper use of ZVS and zero current switching (ZCS) technique to reduce switching losses in power MOSFETs. This requires optimal adaptive or predictable set of delays between switching events that depend on operating conditions;

• Optimal adjustment of intermediate bus voltage, drive voltage and other system parameters to maintain highest efficiency at different operating conditions;

• Smooth transition from one mode to another depending on operating conditions, for example from continuous mode to discontinuous, from fixed frequency to frequency foldback etc.;

• Proper use of pulse skipping or burst mode at light load and at no load to reduce the entire power consumption.

For the interleaved approach, the asymmetrical half-bridge topology is suitable best because of its relative simplicity per each phase [4]. One possible example of interleaving using 4 phases is shown in Fig. 1. The potential drawback of the asymmetrical half-bridge converter is its limited optimal input voltage range. This can be improved by selecting the unequal turn ratios of the power transformers [4].

In case of interleaving, the general challengers include current sharing between the phases and smooth phase shedding or adding depending on load change, especially at fast load current transients. Also, when the number of phases changes, it is desirable to adjust the phase shift angle between the control signals to maintain highest ripple cancellation effect. Based on these considerations, digital control with its programmability and flexibility is most suitable for such relatively complicated control algorithm. Although, the multi-phase interleaved approach has significant merits in achieving the best efficiency over wide output power range, the simpler attractive topologies for the 660-W converter are considered next.

Figure 1. Four phases interleaved asymmetrical half-bridge

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Figure 2. LLC resonant converter

Another strong candidate is the LLC resonant topology recently gaining popularity as post-PFC isolated DC/DC converter (Fig. 2). The main advantage of LLC resonant converter is ZVS for the primary side switches and ZCS for the secondary side synchronous rectifier MOSFETs [5]. This topology has the efficiency peak at the maximum input voltage, which is important advantage for the post-PFC converter, normally operating at the upper end of its input voltage range. Another advantage is the low-voltage rated secondary side synchronous rectifier FETs having lower Rdson versus the higher voltage rated counterparts. However, the variable switching frequency control, special attention to the light load operation and current sharing difficulties in case of interleaving are significant challenges to deal with this topology. Another drawback is the shorted output operation for some specified amount of time that sometimes required in the power system. Such operation requires significant operating frequency increase to limit the input current because there is no output inductor in such topology. Considering these trade offs and challengers, the use of such topology as part of the server power supply could have some limitations even if the high efficiency can be achieved.

The standard phase-shifted full-bridge topology, shown in Fig.3, has the long history of usage as the post-PFC converter [3]. The major advantages of this topology are ZVS of the primary power MOSFETs, fixed frequency PWM operation, reliable handling of the shorted output condition with the cycle-by-cycle current limiting and relatively wide input voltage operating range. The major drawback is the circulating current through the primary switches during PWM off time interval and need for the snubber or clamping circuit to prevent the ringing at the secondary side rectifiers.

Figure 3. Phase-shifted full-bridge DC/DC converter

Nevertheless, to maintain high efficiency and reduce power consumption of the phase shifted converter over the wide output power range, an additional optimization and improvement of the control algorithm are needed. The following section discusses such optimization.

IV. PHASE SHIFTED DC/DC CONVERTER WITH ADVANCED CONTROL ALGORITHM AND RELATED IC CONTROLLER The efficiency improvement of phase-shifted full-bridge

DC/DC converter is achieved by using the synchronous rectification technique, control algorithm providing ZVS condition over the entire load current range, accurate adaptive timing of the control signals between primary and secondary FETs and special operating modes at light load for the highest efficiency and power saving [6]. The simplified electrical diagram of this converter is shown in Fig. 4. The controller IC is located on the secondary side of converter. Such location becomes popular trend allowing easier system level communication and better handling of some transient conditions that require fast direct control of the synchronous rectifier MOSFETs. The power stage includes primary side MOSFETs, QA, QB, QC, QD and secondary side synchronous rectifier MOSFETs, QE and QF. For the 12-V output converters in server power supplies use of the center-tapped rectifier scheme with L-C output filter is a popular choice.

To maintain high efficiency at different output power conditions, the converter operates in nominal synchronous rectification mode at mid and high output power levels, with transitioning to the diode rectifier mode at light load and further followed by the burst mode, as the output power becomes even lower. All these transitions are based on the current sensing on the primary side using the current sense transformer in this specific case.

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COMP

SS/EN

SYNC

VREF

TMIN

VDD

OUTA

OUTC

OUTD

OUTB

GND

EA+

DELCD

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EA-

CS

ADEL

ADELEF

OUTF

DELAB

DCM

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Figure 4. Phase shifted full-bridge converter with advanced controller

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Figure 5. Major waveforms of phase-shifted converter at nominal mode

Major waveforms of the phase-shifted converter during nominal operation mode are shown in Fig. 5. Upper six waveforms in the Fig. 5 show the output drive signals of the controller. At nominal mode, the outputs OUTE and OUTF overlap during the part of the switching cycle when the both rectifier MOSFETs are conducting and the windings of power transformer are shorted. Current, Ipr, is the current flowing through the primary winding of power transformer. The bottom four waveforms show the drain-source voltages of rectifier MOSFETs, VdsQE and VdsQF, the voltage at the output inductor, V Lout, and the current through the output inductor, I Lout. Proper timing between the primary switches and synchronous rectifier MOSFETs is critical to achieve highest efficiency and reliable operation in this mode. The controller IC adjusts the turn OFF timing of rectifier MOSFETs as function of load current to ensure the minimum conduction time and reverse recovery losses of their internal body diodes.

ZVS is an important feature of relatively high input voltage post-PFC DC/DC converters to reduce switching losses associated with the internal parasitic capacitances of power switches and transformers. The controller ensures ZVS conditions over the entire load current range by adjusting the delay time between the primary MOSFETs switching in the same leg in accordance to the load variation. Controller also limits the minimum ON-time pulse applied to the power

transformer at light load, allowing the storage of sufficient energy in the inductive components of power stage for the ZVS transition.

As soon as the load current keeps reducing from the mid load current down to no-load condition, the controller selects the most efficient power saving mode by moving the converter from the nominal operation mode to the transition mode, then to the discontinuous-current diode-rectification mode and, eventually, at very light load and at no-load condition, to the burst mode. These modes and related output signals, OUTE, OUTF, driving the rectifier MOSFETs, are shown in Fig. 6.

It is necessary to prevent the reverse current flow through the synchronous rectifier MOSFETs and output inductor at the light load, during parallel operation and at some transient conditions. Such reverse current results in circulating of some extra energy between the input voltage source and the load and, therefore, causes increased losses and reduces efficiency. Another negative effect of such reverse current is the loss of ZVS condition. The suggested control algorithm prevents reverse current flow, still maintaining most of the benefits of synchronous rectification by modulating the drive signals of rectifier MOSFETs in a predetermined way. At some pre-determined load current threshold, the controller reduces the synchronous rectifier drive signals from the overlapping to 50%, and then gradually reduces their duration, until disabling at the second predetermined threshold. This operation is called transition mode.

Figure 6. Timing diagrams and transitions between power saving modes

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Synchronous rectification using MOSFETs requires some electrical energy to drive the MOSFETs. There is a condition below some light load threshold when the MOSFET drive related losses exceed the saving provided by the synchronous rectification. At such light load, it is beneficiary to disable the drive circuit and use the internal body diodes of rectifier MOSFETs, or external diodes in parallel with the MOSFETs, for more efficient rectification. This mode of operation is called discontinuous-current diode-rectification mode.

At the very light load and no load conditions, the duty cycle, demanded by the closed-feedback-loop control circuit for output voltage regulation, can be very low. This could lead to the loss of ZVS condition and increased switching losses. To avoid the loss of ZVS, the control circuit limits the minimum ON-time pulse applied to the power transformer. Therefore, the only way to maintain regulation at very light load and at no-load condition is to skip some pulses. The controller skips pulses in a controllable manner to avoid saturation of the power transformer. Such operation is called burst mode.

One example of the controller IC closely following the described control algorithm is the UCC28950 from Texas Instruments. The block diagram of this controller IC is shown if Fig. 7. This controller provides adaptive timing between primary and secondary MOSFETs switching and provides up to 10:1 delay time adaptive ratio for the primary switches in the same leg as function of the CS-pin signal. The light load efficiency management block provides optimal transition between different operating modes shown in Fig. 6 as the function of the CS-pin signal. The controller provides all major functions and features usually found in such ICs, like the accurate resistive switching frequency setting, user selectable voltage or current mode operation, closed loop soft start with enable, cycle-by-cycle current limit, PWM ramp slope compensation, under voltage shutdown, accurate reference regulator, synchronization pin for the interleaved operation of converters and others.

Figure 7. Block diagram of the advanced phase-shifted contoller IC UCC28950

V. ZVS PRACTICAL RECOMMENDATIONS One of the most important aspects of post-PFC converter

design is maintaining ZVS condition over entire load current range. For the accurate ZVS prediction, the switching energy of power FETs as function of the applied drain-source voltage Vds, needs to be known. The new super junction technology for high voltage MOSFETs significantly reduces Rdson, Cds and Cgs capacitances [7] providing lower conduction and switching losses. Because of significant non-linear behavior of drain-source capacitance, the super junction MOSFETs, like CoolMOSTM, require new analytical model to estimate switching losses, junction capacitance energy and set proper ZVS conditions. New equation is suggested for the super junction FETs that is simple and provides accurate results:

( )2

)5ln()(2

2 VdsCinitV

VVdsVdsossKc

CossEcds ⋅++⋅⋅= (1)

Here, Ecds is the energy stored, Coss is output capacitance from datasheet at Vdsoss = 25V, Vds is the voltage, where the switching energy has to be found. Parameters Kc and Cinit are constants for each specific MOSFET. For SPA11N60FCD type FET from Infineon, Kc = 2.2 and Cinit = 40 pF.

The plots in Fig. 8 compare calculated energy using (1) with the experimental plot provided in the datasheet.

0 100 200 300 400 500 6000

1

2

3

4

5

6

7

8

Vds (V)

Eoss

(mic

roJ)

a) Analytically derived plot

b) Experimental plot from datasheet

Figure 8. Comparison of analytical energy model Ecds over Vds for SPA11N60FCD type MOSFET

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One can see that both plots correlate very accurately. The analytical equation is very helpful for accurate ZVS prediction.

The next step for the ZVS based design is to determine the leakage and magnetizing inductances of power transformer that guarantee ZVS switching over the entire load current range. The energy stored in the leakage and magnetizing inductances is compared with the energy required to discharge MOSFET capacitances in accordance to (1). At the mid and high load current conditions the ZVS is maintained by the energy stored in the leakage inductance. In some cases, it is beneficiary to use the special inductor in series with the primary winding of power transformer along with the clamped diodes as described in [8] to ensure ZVS. At light load the energy is provided by the magnetizing inductance of power transformer. Because the transition resonance frequency associated with the leakage inductance is significantly different from the resonance frequency associated with the magnetizing inductance, the delay time between primary FETs must be adjusted as function of the load current. Such adaptive delay time is provided by the controller in Fig. 7.

VI. EXPERIMENTAL RESULTS The 660-W output power prototype of phase shifted full-

bridge DC/DC converter has been designed and tested to verify the suggested control algorithm, meeting of the efficiency goals and the accuracy of theoretical efficiency and power losses prediction over the entire load current range. The input voltage is 350 V to 420 V and the output is 12 V, 55 A. The primary MOSFETs are SPA11N60CFD and the synchronous rectifier MOSFETs are FDP047AN08A0, two in parallel. The measured efficiency of the prototype (solid curve) and analytical prediction (dashed curve) along with the design goals (circles) over the load current are shown in Fig. 9. There is good correlation between the analytically predicted and measured efficiency in the load current range below 12% and above 50% of maximum current. The efficiency difference from 12% to 50% load is attributed to the partial ZVS loss in this range that adds additional switching losses.

0 4 8 12 16 20 24 28 32 36 40 44 48 52 5660646872768084889296

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Efficiency GoalMeasured 660 W prototypeAnalytically predicted efficiency

Load current (A)

Effic

ienc

y (%

)

Figure 9. Measured (solid curve), analytically predicted (dashed curve) and efficiency design goals (circles) of the 660 W prototype

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 20123456789

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Vin = 400 V, Vout = 12 VLoad current (A)

Ligh

t loa

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wer

loss

es (W

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CCM mode with synchronous FETs

DCM mode with diode rectificationBurst

mode

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Ligh

t loa

d po

wer

loss

es (W

)

CCM mode with synchronous FETs

DCM mode with diode rectificationBurst

mode

Figure 10. Power losses of 660 W DC/DC converter prototype at light load

One can see that there is good margin for the achieved efficiency at 10%, 50% and 100% load versus the design goals. However, the design goal at 20% load is not achieved and additional, at least 1% efficiency increase, is needed. There are few options to meet the design goal at 20% load. One option is to choose the higher Rdson FETs with the smaller die size and lower parasitic capacitances. The efficiency margin at 50% and 100% load allows sacrifice of some conduction losses for the sake of the reduced switching losses. However, this approach may not be the best one, because in some cases the industry standards exceed the regulations set by the government shown in Table 1. The better way is to reduce the magnetizing inductance and slightly increase the leakage inductance of the power transformer to achieve ZVS in the shown area. This example demonstrates that to meet such challenging requirements, additional tuning and design iteration might be needed.

Because of the power saving trend even at very light and no-load conditions, careful optimization of operation at light load condition of the prototype has been fulfilled to set the proper boundaries between different operation modes. The result of this optimization is shown in Fig. 10. This plot demonstrates the power savings while moving from the synchronous rectification mode above 1-A load current, into the discontinues current mode (DCM) with the diode rectification between 0.3-A and 1-A load current, and eventually into the burst mode operation at load current below 0.3 A.

VII. CONCLUSION The new industry requirements and regulations for

increased efficiency and power saving over wide output power range for the data and telecommunication power supply are outlined. Efficiency design goals for the post-PFC isolated DC/DC converter are derived as part of the 670-W server power supply that includes the PFC, the standby power supply with 5-V, 10-A output and the main DC/DC converter with 12-V, 55-A output. Few topologies including interleaved asymmetrical half-bridge, LLC resonant and phase-shifted full-bridge have been compared as candidates to meet the efficiency goals. The control strategies providing power saving and maintaining high efficiency control over the entire output power range are listed and discussed. Based on this, the

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phase-shifted full-bridge converter has been selected for further consideration and its advanced control algorithm presented along with the related IC controller. Some practical design rules to achieve the full ZVS and the new accurate analytical equations for the switching energy of the CoolMOS® technology based FETs are provided. Advantages of suggested control algorithm and the accuracy of analytical prediction to meet the efficiency goals are verified by the 660-W DC/DC converter prototype for the server power supply with the efficiency up to 95.3% achieved.

REFERENCES [1] “ENERGY STAR® program requirements for computer servers,

version 1.0,” Available: http://www.energystar.gov/index.cfm?c=archives.enterprise_servers

[2] R. Mammano, “Improving power supply efficiency - The global perspective,” Texas Instruments Power Supply Design Seminar, Topic 1, SEM-1700, 2006.

[3] J. Zhang, X. Xie, X. Wu and Z. Qian, “Comparison study of phase-shifted full bridge ZVS converters,” in PESC 2004 Conference Proceedings, 2004, pp. 533-539.

[4] R. Miftakhutdinov, A. Nemchinov, V. Meleshin and S. Fraidlin, “Modified asymmetrical ZVS half-bridge DC-DC converter,” in APEC 1999 Conference Proceedings,1999, pp. 567-574.

[5] D. Fu, B. Lu and F. Lee, “1MHz high efficiency LLC resonant converters with synchronous rectifier,” in PESC 2007 Conference Proceedings, 2007, pp. 2404-2410.

[6] R. Miftakhutdinov, “Power Saving Solutions in DC/DC Converter for Data and Telecommunication Power System,” in PEDS 2009 Conference Proceedings, available on CD.

[7] F. Bjoerk, J. Hancock and G. Devoy, “CoolMOSTM CP- How to make most beneficial use of the latest generation of super junction technology devices,” Infineon Appl. Note, AN-CoolMOS-CP-01, February 2007.

[8] R. Redl, N.O. Socal and L. Balogh, “A Novel Soft-Switching Full-Bridge DC/DC Converter: Analysis, Design Considerations, and Experimental Results at 1.5 kW, 100 kHz,” in IEEE Trans. on PE., vol. 6, No.3, pp. 408-418, July 1991

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