Low-Power Low-Voltage Analog Circuit Design using Hierarchical Particle Swarm Optimization

R. A. Thakker, M. Shojaei Baghini, M. B. Patil

Department of Electrical Engineering, Indian Institute of Technology, Bombay. E-mail: rajesht@ee.iitb.ac.in, mshojaei@ee.iitb.ac.in, mbpatil@ee.iitb.ac.in

Abstract

This paper presents application and effectiveness of Hierarchical particle swarm optimization (HPSO) algorithm for automatic sizing of low-power analog circuits. For the purpose of comparison, circuits are also designed using PSO and Genetic Algorithm (GA). CMOS technologies from 0.35 μm down to 0.13 μm are used. PVT (process, voltage, temperature) variations are considered during the design of circuits. We show that HPSO algorithm converges to a better solution, compared to PSO and GA. For CMOS Miller OTA, even performance of the circuit designed by HPSO algorithm is better than the performance of recently reported manually designed circuit. For the first time, design of this OTA, in 0.4 V supply voltage, is also presented. For this new design, HPSO algorithm has taken 23.5 minutes of CPU time on a Sun system with 1.2 GHz processor and 8 GB RAM. 1. Introduction

The problem of analog circuit design and, in particular, MOS transistor circuit design has become very complex with the down-scaling of technology and with the increasing complexity of physical models. Various optimization techniques have been reported in the past and the recent times for automatic design of analog circuits. The gradient-based optimization methods [1] need to calculate derivatives and also require good initial guess for the design variables. In the absence of initial guess close to the globally optimum solution, these algorithms would generally stick at a locally optimum solution. Convex optimization techniques [2], which guarantee globally optimum solution, require a very good knowledge of circuit design and also of physical models to prepare constraints, which would be very difficult looking at the current state-of-the-art MOSFET models.

The evolutionary algorithms, which can be used to solve multimodal optimization problems to explore the solution space more efficiently, do not suffer from

difficulties associated with the gradient-based and convex optimization methods. The Genetic Algorithm (GA), developed by Holland [3] with an inspiration from biological evolution, has been reported several times for automatic analog circuit design. Few recent citations are also found in [4]. Particle swarm optimization (PSO), proposed by Kennedy and Eberhart [5], has been observed to give better accuracy compared to GA in most of the applications. PSO algorithm was used for circuit design applications in [6]. This paper shows the effectiveness of hierarchical PSO (HPSO) [7], an extended version of PSO algorithm, for analog circuit design problem. 2. Analog Circuit Sizing Problem

In analog circuit design, after choosing a proper circuit configuration, values of circuit elements, called design variables, need to be determined to achieve the desired specifications. In case of MOS transistor circuits, generally these variables include the width (W) and length (L) of transistors, values of resistors, capacitors and inductors. Integrated analog circuit designers prefer to use technologies with longer minimum channel lengths as compared to digital circuits. However, technology scaling, high performance demands, and system-on-chip applications force analog modules to be implemented in the same or at most few technology nodes behind as that of digital circuits. The increased complexity of physical models and process variations with down-scaling of technology has made the manual design of analog circuits to be a challenging and time-consuming task. Therefore, efficient automatic design techniques are required.

The block diagram of the automatic analog circuit design, implemented in this work, is shown in Fig. 1. The optimizer module minimizes the error between desired specifications and simulator-returned performance measures using a suitable optimization algorithm (in this study, algorithm is: GA, PSO, or HPSO). The error function is defined as,

2009 22nd International Conference on VLSI Design

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DOI 10.1109/VLSI.Design.2009.14

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∑ ⎟⎟⎠

⎞⎜⎜⎝

⎛ −=

2

Desired

SimDesiredSpec

SpecSpecFε , (1)

where DesiredSpec represents desired specifications, and

SimSpec denotes the specifications returned by a circuit simulator for a particular solution provided by the optimizer. In each circuit design evolution, the specifications which satisfy the required criteria, will not contribute to the error function in Eq. (1).

Fig. 1 The block diagram representation of automatic circuit optimizer.

3. Particle Swarm Optimization

In PSO algorithm [5], for a problem with n variables, nxxx ,,2,1 … , a population of N particles is initially generated by randomly assigning positions and velocities to each particle for each variable. In the case of analog circuit sizing, variables are the circuit design variables, e.g., sizes of transistors. If the position and velocity of the ith particle are denoted by vectors ix and iv respectively, then

( ) ,,...,, 21 niiii xxx≡x and ( )n

iiii vvv ,...,, 21≡v (2) Particles are moved towards the fittest particle and

in this process; algorithm finds a better solution and is expected to reach the desired solution over time. Each particle keeps in memory the best position (denoted by ix ) it has attained during its trajectory. The velocity of a particle is updated on the basis of weighted addition of three vectors (Eq. 3), shown in Fig. 2(a): (i) particle’s own velocity (A), (ii) the displacement of the particle from its past best position (B), (iii) the displacement of the particle from the globally best particle (C). The velocity update is given by,

,)()()()()( 2211 igiiii rprpttwtt xxxxvv −+−+=Δ+ (3)

( ) ( ) ( ) ,tttttt iii ΔΔ++=Δ+ vxx (4) ( )

ffi wt

ttwwtw +

−−=

max

max)()( , (5)

where i is the particle index, t is the current iteration number, tΔ is equal to 1. r1 and r2 are random

numbers uniformly distributed in the range [0, 1]. The parameter w is “inertia”, and p1 and p2 are the acceleration coefficients. The gx represents the best position attained by globally best particle. The velocities computed with Eq. (3) are used to move the particles as specified by Eq. (4). The commonly reported linear approach to update w parameter is used in this work and given in Eq. (5). wi and wf represent the initial and final values of w, respectively, and tmax is the maximum number of iterations.

Fig. 2 (a) Two-dimensional representation of the components involved in velocity update of particles. (b) Arrangement of particles in HPSO algorithm.

In HPSO [7], population of N particles is first

arranged in ascending order according to their fitness, with the globally best particle (the “global leader”) at position N, as shown in Fig. 2(b). The next M best particles are designated as the “local leaders.” The remaining (N-M-1) particles (the “generic particles”) are divided into M groups. The M local leaders are assigned to the M groups. The generic particles follow their local leader and the local leaders follow the global leader. This feature enables enhanced exploration of the search space and shows better consistency in finding the optimum solution. Algorithm parameters used in this work- For PSO and GA, N = 20. The crossover and mutation probabilities in GA are taken 0.8 and 0.2, respectively. For PSO, wi = 0.9 and wf = 0.4. For HPSO, wi = 0.73 and wf = 0.4 [7], and N = 21, M = 5. For both, PSO and HPSO, p1 = p2 = 1.49 [7]. 4. Analog Circuit Examples and Results

In this section, we demonstrate the application of HPSO algorithm for automatic design of four analog circuits. The Cadence Spectre circuit simulator with BSIM3v3 MOSFET models is used to simulate circuits. To improve efficiency of the automatic design process, the simulator is asked to evaluate the fitness of a particular particle (chromosome), only if it has changed on at least one of the design variables by more than 1%. This restriction prevents unnecessary circuit

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simulations. GA, PSO, and HPSO algorithms are compared with respect to two criteria. • Quality of the solutions (measured by the error

function Fε given in Eq. (1)). • Consistency of the algorithm in finding the best

solution is measured by εF (average value of Fε) over independent trials for each design problem. In addition to the calculation of Fε, the CPU time

taken by each algorithm is recorded, and averaged (denoted by CPUT ) over multiple design trials. The specifications during circuit evolutions are also recorded and normalized with the desired specification values for illustration purpose. All simulations are performed on a Sun system with 1.2 GHz dual core processor with 8 GB RAM.

Fig. 3 CMOS buffer chain and plots of rise (τpd, r) and fall (τpd, f) propagation delay, and power dissipation versus circuit evolutions. One design solution obtained with HPSO is: W1 = 0.13 μm, W2 = 0.5 μm, W3 = 1.7 μm, W4 = 6.5 μm, and K = 2.0.

4.1 CMOS Buffer Chain

CMOS buffer chain (Fig. 3), commonly used for driving large capacitive loads, is designed using standard 0.13 μm CMOS process at VDD = 1.2 V and for L = 0.13 μm. Input stage M1 is chosen with minimum size. The width of remaining three NMOS transistors, and the ratio between the width of NMOS and PMOS transistors are considered as design variables. The buffer chain is designed using GA, PSO, and HPSO algorithms to minimize the rise (τpd, r) and fall (τpd, f) propagation delays, and power dissipation of the circuit. To examine the consistency of algorithms, five independent designs are carried out using each algorithm. Performance measures, evolved during the design cycles and averaged over five design trails, are plotted in Fig. 3. HPSO and GA algorithms are close in performance with HPSO algorithm slightly better than

GA. PSO algorithm is not able to minimize the power dissipation as compared to HPSO and GA.

To evaluate the buffer chain designed by HPSO algorithm, the circuit is also sized manually using the logical effort theory (LET) with equal stage efforts assigned to each stage. It was observed that the results of HPSO algorithm not only match those of LET design, but also slightly better.

4.2 Two-stage CMOS Operational Amplifier

The two-stage CMOS op-amp, shown in Fig. 4 (a), is designed using 0.13 μm CMOS process at VDD = 1.2 V, T = 27 ˚C, and for specifications given in Table 1. Op-amp specifications are of different orders in terms of values, which require different weights to be assigned to each of them during automatic design process. We have used constant weight approach and to ensure stability of the designed circuit, chromosomes in GA (or particles in PSO) are considered to be elite (or leaders in PSO), only if they have phase margin greater than 55˚.

Fig. 4 (a) Two-stage CMOS operational amplifier and (b) Plot of average error ( )εF .

The design variables in this circuit are: W and L of

transistors, the compensation capacitor, and the biasing current I0. The range for each design variable is shown in Table 1. Systematic offset is taken into consideration during design cycle. Ten independent design trials are carried out. Five process corners taken into account during the design are: TT, FF, SS, FS, and SF, where ‘T’ stands for typical, ‘S’ for slow, and ‘F’ for fast. The plot of εF versus number of circuit evolutions is shown in Fig. 4(b). PSO and HPSO algorithms are close in performance; whereas the performance of GA is poor. Two (out of ten) design solutions obtained

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with HPSO are given in Table 1. All of them are showing similar performance though sizes of transistors are different in some cases.

Table 1. Design solutions and specifications at TT process corner for two-stage op-amp designed by

HPSO.

Design variables

Variable range

Solution 1

Solution 2

W1/L1

W: 0.5 to 10 (μm)

L: 0.13 to 1 (μm)

Transistor

dimensions are in μm.

2.5/0.75 3.0/0.75 W2/L2 1.5/0.5 1.5/0.5 W3/L2 3.8/0.5 3.8/0.5 W4/L3 7.0/0.75 7.0/0.75 W5/L4 1.5/0.25 3.5/0.25 W6/L3 3.0/0.75 2.0/0.75 W7/L5 4.0/0.75 3.5/0.75 W8/L5 4.0/0.75 5.0/0.75 W9/L3 5.5/0.75 5.5/0.75 I0 (μA) 0.01 to 10 (μA) 4.5 4.8 CF (pF) 0.1 fF to 10 pF 0.09 0.1

Desired specifications Specifications obtained Gain ≥ 86 dB 86.16 86.13

Phase margin ≥ 65˚ 61.79 60.9 UGF ≥ 100 MHz 101 97

Power dissi. ≤ 20 μW 21 21.2 Rise slew rate ≥ 40 V/μs 50.33 48 Fall slew rate ≥ 40 V/μs 37.79 38

4.3 Ultra-low-voltage CMOS Miller OTA

The third example is an ultra-low-voltage, bulk-driven, rail-to-rail CMOS Miller OTA; recently reported in [8] and shown in Fig. 5(a). We show automatic design of this circuit in 0.35 μm TSMC mixed-mode process and at VDD = 0.6 V, which are the same process and VDD level used in [8]. The circuit is designed for specifications given in Table 2, which are equivalent or better than that reported in [8].

To carry out the comparison with the results reported in [8], the process, supply, and temperature (PVT) variations are not taken into account during the design. The ranges of design variables are given in Table 2. The circuit is designed for ten independent design trials. The plot of εF is shown in Fig. 5(b). It can be seen that the HPSO algorithm is better in performance in comparison to PSO and GA.

The specifications and sizing of transistors reported in [8], and that obtained using HPSO algorithm (one out of ten solutions), are given in Table 2. The following observations can be made from the table for the circuit designed using HPSO algorithm in comparison to that reported in [8].

(a) The open loop gain is greater by 9 dB, which means it is superior by 2.8 times.

(b) The unity gain frequency is close to four times better.

(c) It has given better phase margin and slew rate. (d) The performance in terms power dissipation and

third component of THD is equivalent. (e) The total transistor area is less by 80 %.

Fig. 5 (a) Ultra-low-voltage, ultra-low-power CMOS Miller OTA. (b) Plot of error ( )εF .

Fig. 6 Plot of specifications versus circuit evolutions for CMOS Miller OTA (Fig. 5(a)) designed by HPSO algorithm in 0.18 μm and VDD = 0.4 V.

For future ultra-low-voltage applications, this

circuit is also designed for standard 0.18 μm mixed-mode process at VDD = 0.4 V using HPSO algorithm. The NMOS and PMOS threshold voltages are 403 and 440 mV, respectively. The desired specifications are set to the same values as used for 0.35 μm technology, and the circuit is designed for five independent design trials. The progress of performance measures (normalized) versus circuit evolutions averaged over

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five independent design trails is shown in Fig. 6. Two design solutions with obtained specifications are shown in Table 3. The following major observations can be made about the circuit reuse in VDD = 0.4 V (Table 3) compared to the circuit in VDD = 0.6 V (Table 2):

(a) The open loop gain is reduced. (b) The unity gain frequency is increased. (c) The total transistor area is larger.

Table 2. Design solution and specifications reported in [8], and those obtained by HPSO algorithm for

CMOS Miller OTA in 0.35 μm technology.

Design variables

Ref [8] HPSO Algorithm Variable Range Solution

(W/L) MP 200/9 W: 1 to 200 (μm) L for transistors is equal to the values reported in [8]. Transistor dimensions are in μm.

34.5/9 (W/L) M5 200/9 87/9 (W/L) M1, 250/1 130/1 (W/L) M8, 100/9 18/9 (W/L) M3b, 400/1 86.5/1 (W/L) M3a, 100/1 19.5/1 (W/L) M7 800/9 104/9 (W/L) M6 400/1 33/1 Rc (kΩ) 73.1 1 to 100 kΩ 81 Cc (pF) 5 1 to 10 pF 1.9 Iref (nA) 130 100 nA to 10 μA 109

Desired specifications Specifications obtained Ref [8] HPSO

Open loop gain ≥ 75 dB 73.5 82.67 Phase margin ≥ 65˚ 54.1˚ 58.01˚

UGF ≥ 50 kHz 13.02 48.61 Power dissipation ≤ 500 nW 550 545.49 THD3 ≤ 1% at 520 mVp-p, 1

KHz 0.13 % 0.15 %

Rise slew rate ≥ 15 V/ms 14.7 21.77 Fall slew rate ≥ 15 V/ms 14.7 23.11 Total Trans. Area (μm2) 14500 2858.5

Total Area (μm2) 20772 5586.92

4.4 High-gain low-power three-stage Op-Amp The circuit schematic of high-gain low-power

three-stage CMOS op-amp, commonly used in transimpedance amplifiers and recently reported in a highly precise 1-V CMOS current reference generator [9], is shown in Fig. 7(a). A small modification was applied to the circuit to provide a proper topology for low-voltage design. For Vbias, we used VDD/2. We also used drain of M22 to bias gate of M25 and M26. This circuit is designed for 0.18 μm UMC technology. The process variations (TT, FF, SS, FS, SF), supply variations (± 10 % at 1.0 V), and temperature range 27-70 ˚C are taken into account. The desired specifications and the range of design variables are given in Table 4. To reduce the design time, the following steps are used in designing the circuit.

(a) Initially, the circuit is designed for TT process corner with supply variations considered and at T = 70 ˚C.

(b) The solution obtained in step (a) is refined to consider process and supply variations.

(c) The design solution obtained in step (b) is refined to consider PVT variations.

Table 3. Design solution and performance measures

for CMOS Miller OTA in 0.18 μm technology.

Design variables Solution 1 Solution 2 (W/L) MP

Transistor dimensions are in μm.

110.5/9 105/9 (W/L) M5 122.5/9 100/9 (W/L) M1, M2 17/1 11.5/1 (W/L) M8, M9 15/9 11.5/9 (W/L) M3b, M4b 138/1 90/1 (W/L) M3a, M4a 38.5/1 65/1 (W/L) M7 194/9 143.5/9 (W/L) M6 98/1 151/1 Rc (kΩ) 99 98 Cc (pF) 2.7 1.9 Iref (nA) 350 420

Desired specifications Specifications obtained Open loop gain ≥ 75 dB 75 76.84

Phase margin ≥ 65˚ 59.7˚ 56.5˚ UGF ≥ 50 kHz 58 58.83

Power dissipation ≤ 500 nW 571 581 THD ≤ 1% at 400 mVp-p, 1 KHz 1 % 1 %

Rise slew rate ≥ 15 V/ms 30.87 30.58 Fall slew rate ≥ 15 V/ms 16.4 21

Total Transistor Area (μm2) 4598 3827.5 Total Area (μm2) 7520.24 6046.19

For better clarity, the comparison between

algorithms is carried out after completion of step (a) and is shown in Fig. 7(b). It can be seen that GA is quicker in reducing the error Fε. But, HPSO is able to catch GA in terms of performance and is observed to keep on reducing Fε. The plots of specifications averaged over five independent designs for HPSO algorithm after step (a) are shown in Fig. 8 and can be seen that they attained the specified values. One of the design solutions obtained with HPSO algorithm at the end of step (c), is shown in Table 4 along with the performance measures for the extreme supply voltages and temperatures at TT process corner.

The average CPU time )T( CPU taken by algorithms for the design of circuit examples considered in this work is given in Table 5. GA has taken slightly more CPU time, compared to PSO and HPSO.

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Fig. 7 (a) High-gain low-power three-stage op-amp (Vbias = VDD/2). (b) Plot of error ( )εF .

Table 4. Design solution and performance measures

at TT process corner for three-stage CMOS op-amp.

. Design variables Variable range Solution

(W/L) M17, M18

W: 1 to 50 (μm) L: 1 to 10 (μm)

Transistor

dimensions are in μm.

3.0/8.25 (W/L) M19, M20 12.0/7.5 (W/L) M21, M22 3.0/2.75 (W/L) M23, M24 3.0/2.25 (W/L) M25, M26 9.5/2.0 (W/L) M27, M28 15.5/5.5 (W/L) M29 50.5/1.0 C1 (pF) 0.001 to 10 pF 4.3 R4 (kΩ) 1 to 75 kΩ 59 Desired specifications Specifications obtained

Temp 27˚ C 70˚ C VDD 1.1 V 0.9 V 1.1 V 0.9 V

Gain ≥ 100 dB 119 114 118 114 Phase margin ≥ 65˚ 64 71 65 72

UGF ≥ 300 kHz 687 509 658 507 Power dissi. ≤ 10 μW 14 7 14 7.3

Systematic input offset voltage ≤ 50 μV

19 4.3 28.7 11.22

Table 5. The average CPU time )T( CPU taken for

the design of circuits by algorithms.

Design Example GA PSO HPSO h: hours, m: minutes, s: seconds

B u f f e r C h a i n 4 m 21 s 3 m 54 s 3 m 48 sTwo-stage opamp 1 h 43 m 1 h 38 m 1 h 37 mCMOS Miller OTA 26 m 28 s 22 m 27 s 23 m 4 sThree-stage opamp 2 h 56 m 2 h 41 m 2 h 48 m

Fig. 8 Plots of specifications of three-stage op-amp designed by HPSO at TT process corner, T = 70 ˚C. 5. Conclusions

In conclusion, application of HPSO algorithm is

demonstrated for automatic design of low-power low-voltage analog circuits. It is observed that in general, HPSO algorithm finds solutions with better repeatability, compared to GA and PSO. For ultra-low-voltage CMOS Miller OTA designed in 0.35 μm standard technology, the specifications of HPSO-designed circuit are significantly better than that of recently reported manual design. The OTA is also designed for the first time in 0.18 μm technology at VDD = 0.4 V. For this new design, HPSO algorithm takes 23.5 minutes of CPU time. 6. References [1] A. Savio, et al., “Automatic scaling procedures for analog design reuse,” IEEE Cir .and Sys.-I, 2539-2547, Dec. 2006. [2] M. Hershenson, et al., “Optimal design of a CMOS op-amp via geometric programming,” IEEE Trans. Comp. Aided Des. of Int. Cir. and Sys., vol. 20, pp. 1-21, Jan. 2001. [3] D. Goldberg, “Genetic Algorithm in Search, Optimization, and Machine Learning,” 1989. [4] A. Somani, et al.., “An evolutionary algorithm-based approach to automated design of analog and RF circuits using adaptive normalized cost functions,” IEEE Trans. Evol. Comp., Vol. 11, 336-353, June 2007. [5] J. Kennedy, et al., “Particle swarm optimization,” Proc. IEEE Int. Conf. on Neural Networks, pp. 1942-1948, 1995. [6] J. Park, et al.., “Parasitic-aware RF circuit design and optimization,” IEEE Cir. and Sys.-I, 1953-1966, Octo. 2004. [7] S. Janson and M. Middendorf, “A hierarchical particle swarm optimizer and its adaptive variant,” IEEE Trans. Sys., Man, and Cyber. – Part B: vol. 35, 1272–1282, Dec. 2005. [8] L. Ferreira, et al.., “An ultra-low-voltage ultra-low-power CMOS Miller OTA with rail-to-rail input/output swing,” IEEE Cir. and Sys.-II: Exp. Briefs., 843-847, Octo. 2007. [9] A. Bendali, et al., “1-V CMOS current reference with temperature and process compensation,” IEEE. Cir. and Sys.-I., 1424-1429, July 2007.

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