The 7th International Conference on Power ElectronicsOctober 22-26, 2007 I Exeo, Daegu, Korea

PA25

Novel Single-state PWM technique in Multilevel Inverter for unbalanced dc sources

Nguyen Van Nho l,

HochiminhCity University OfTechnologyDepartment ofElectrical Engineering

268 LyThuongKiet, District 10, Hochiminh CityEmail: nvnho@hcmut.edu.vn

Hong Hee Lee2, Nguyen Dinh Tuyen3

University OfUlsanDepartment ofElectrical Engineering

680-749 San 29, Muger 2-dong, Ulsan, KoreaEmail: hhlee@mail.ulsan.ac.kr

Abstract- Single-state PWM technique (SS PWMO presents anoptimised switching losses PWM scheme to be applied formultilevel inverter for possible reducing number of switchingsin a sampling period. Nonlinear control characteristics andharmonic distortion factor can be significantly improved if thenumber of levels is high. To implement a single- state PWMcontrol with minimised voltage error on condition of unbalancede sources, a compensating technique is required. The paperwill propose a possible solution for implementing the SS PWMwith minimised voltage error, using carrier based approach.This again demonstrates the utilisation of carrier based andspace vector PWM relationship in solving various optimisedPWM problems in multilevel inverters.

components [7]. In this case, the SS PWM method can be aprospective solution for hybrid topologies. In some case,diode clamped inverter can be used in thie hybrid invertersand compensating the influence ofunbalanced dc sources bya proper SS PWM will improve the voltage output.In the paper, the principle ofproposed single state PWM can

be deduced from the generalised PWM theory for multilegmultilevel inverter on unbalanced dc sources [8]-[9]. Thecontrol characteristics and harmonic distortion will becalculated for several multilevel inverters. The method isexplained for diode-clamped multilevel inverters (Fig. I) butits principle can be properly applied to other invertertopologies.

II. CIRCUIT ANALYSIS

The circuit model and equations of a generalized I-legn-Ievel inverter can be applied for three-phase n-Ievelinverter, in which each voltage vector can be described in3-coordinates as follows:

(2)

j = [1,1,I]T

(3)

(I)

-- -- --V re! = f}2 + VOrefI ;

-- Twhere V re! = [Vre!(l)' V re!(2) , Vre!(3) ]

-- Tand Vi2 =[f}2(l)' Vi2(2)' Vi2(3) ] .

Define two active high VH(x) and low VL(x) voltage levels,

which are closest to the reference Vre!(x) and

corresponding to levels of L(x) and H(X) on dc side (Fig. 1b)

as:

Reference voltage in single-leg inverter: Vre!(x)

x =1,2,3 between inverter outputs and dc-neutral point

"0", analysed as a sum of active voltage and the relevantoffset as follows [8-9]:

I. INTRODUCTION

Recently, multilevel inverters have been developing veryintensively and they have become a significant part in powerapplications. There are several basic topologies as diodeclamped multilevel inverters, cascaded multilevel inverterand capacitor clamped multilevel inverters. Normally, forattaining required voltages, these power converters can becontrolled using conventional carrier based PWM or spacePWM methods [1]-[4]. It appears a question, ifit is possibleto effectively implement a PWM method with reducednumber of switchings in sampling period. In practice, thereexist several PWM methods, which can produceapproximately the reference. The simplest case assingle-state PWM, which normally requires only onecommutation for three-phase in half carrier period, canobtain the output with acceptable error if the number oflevels is high [5]. In another case, the switching voltagevector will be selected for purpose of satisfying severaloptimal conditions. The Direct Torque Control and hysteresiscurrent controller in control ofAC motor drives can be seenas different applications of single-state PWM techniques.This paper presents a carrier based approach to implement

single-state PWM method with minimised error. Comparingwith recent solution [5], several new characteristics will beconsidered: a) solution is of carrier based PWM approachwith possible common mode control, b) variation of dcsources and c) solution in whole modulation range.For a given PWM scheme, dc voltage unbalancing oroscilating can reduce the output quality [6]. It is needed to beeliminated or compensated, particulaly for diode-clampedinverters, capacitor clamped inverters and related hybridinverters. Recent developing of hybrid inverters enables tobuild very high level inverters of reduced hardware

978-1-4244-1872-5/08/$25.00 © 2008 IEEE 174

The 7th International Conference on Power ElectronicsOctober 22-26, 2007 / EXCO, Daegu, Korea

The reference modulating vector

---+ [ ]1' can be determined asvref = Vr~f(1)' Vr~f(2 p Vr~f(3)

follows [3]:

Vr~f =K}V} + K 2V2 + K 3V3 + K 4V4

K}+K 2 +K3 +K4 =1(9)

where

(15)

(11)

(12)

(10)

if j: j:~ref(x) > ~j

else.S/(x) = {~

Vi = VL + [VAd ]Si; j = 1,2,3,4.. .

The nominal switching state 5j ; j =1,2,3,4 can be

determined as :

where 5i is nominal switching state and can be determined

as below [9].

Nominal switching states 5j : can be deduced as below.

First, let's re-arrange nominal modulating signals

;r~f(x) ,X = 1,2,3 from (6) in decreasing order as:

1~;} ~;2 ~ ;3 ~ 0 = ;4 (13)

where ~1 =Ma.x{~ref(1)' ~ref(2)' ~ref(3)}

, ~3 = Min{~ref(1)' ~ref(2)' ~r"f(3)} j = 1,2,3 . (14)

(8)

a)

o 0

VAd(2) 0

o VAd(3)

VAd(1)

[VAd ] = 0

o

---+ l'where ;r~f = [;r~fO)' ;r~f(2)' ;ref(3)] is determined as

---+ -1 ---+ ---+

;r~f = [VAd ] (V,~f - ~_) (6)

(7)and VAd(x) - active dc voltage source:

VAd(x) =VH(x) - VL(x) ; X =1,2,3

Switching states Sj corresponding switching voltage

vectors V.i can be described as:

Corresponding matrix ofactive dc voltage sources VAd(x) is ---+ ---+

Sj = L +Sj; j = 1,2,3,4of 3x3-dimension and described as:

III. PROPOSED SINGLE STATE PWM METHOD

---+ ---+

Depending on the vector diference (Vr~f - VI_) and

active voltage [Vad ] ,the states 52 can be any from

vectors [0,0,1]1, [0,1,0]1, and [1,0,0]1 and 53 can be any

from vectors [O,l,lf, [1,O,lf and [l,l,of. It can bededuced that:

- voltage vectors to appear in (9) are depending onthe reference common mode voltage

- adding an additional common mode voltage VOadd

to reference in modified PWM techniques can change theorder of commutations between phases. As result,

combination (52' S3) can be some from 6 available variants

described above.

V e 11)

VOadd

VOaddl Vrefh)

V12(1)1

~}r~(1)VOreflc)

Eref(l)

Vreff1~--""'--­

VL(1)+------:'''''*'--

b)

i+-level"O"

Figure I: a) 5-level NPC inverter~ b) c) and d) Analysis of inverterleg voltages

Reference vector can be implemented by 4 subsequentswitching voltage vectors as follows: To determine the vector in SS PWM method with

absolutely minimum active error from the reference, itwould require to consider all vectors to be involved whenthe offset voltage goes through entire operating range (i.e.

175

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The 7th International Conference on Power ElectronicsOctober 22-26, 2007 I EXCO, Daegu, Korea

VOMin ~ Vo ~ VOMax ). However, if the the offset voltage is

modified very large, some extra switchings may be requiredand they can cause more switching losses.

An appropriate modified PWM can be proposed sothat the modified leg voltages will be limited incorresponding active voltage levels, Le.

VL(x) :::; V~rej :::; VH(x)· There can be several approaches

as:a.The selected vector will be considered as one from 4

related vectors in (9). This approach does not needmuch calculating.

b. A more generalised criterium than case a) is that theimplemented vector will be proposed as one from 8vectors deduced from equation as

Vk = VL + [VAd ]sk; k = 0,1,2,...,7. (16)

where

S E {[O,O,O]T , [O,O,l]T , [O,l,O]T ,[O,l,l]T}k T T T[1,0,1] ,[1,1,0] , [1,1,1]This approach enables to locally select vector with

minimum active error while reducing the number ofextraswitchings to minimum.

Discussion: For balanced dc sources, the vector withminimum error in single-state PWM method can be

determined from 4 vectors Vj involved in (9) and changing

common mode voltage has no effect on the location ofselected vector and the resulted error. This will be differentfor unbalanced dc sources, the vector with minimum erroris needed to be determined from all 8 variants describedabove and the selected vector and voltage error will dependon the reference common mode voltage.

Algorithm of proposed single-state PWM method:

1. For given reference active voltage Vi2 and

measuried dc sources, to select reference common

mode voltage VOref within (VOMin,VOMa,) range

2. To determine active low voltage level VL , active

dc sources VAd(l)' V Ad(2)' V Ad(3) and vector

errors of reference V rej from switching vector V j

as:

Ej =Vrej - Vj =Vt2 + vorejl- VL -[VAd ]s~where j=O,I,2,3..,7. (17)

3. To calculate error Ej . The selected vector is one,whose error attains minimum value:

Ej =IEjl= k[(E;(l) -0.5E;(2) -0.5E;(3)2 +0.7 :(E;(2) - E;(3))2]j=O,I,2,3, ... ,7 (16)

§ ref = Sj = i + s for

E j = Min(Eo,E2 ,···,E7 ) ;k=const. (19)

IV. OVERMODULATION

Let's suppose that:- the value ofreference modulation index is defined the sameas for case of standard balanced dc sources.- the voltage values are described without dimension as ratio

(V / VdcN ), where the normal dc voltage VdcN can selected

as voltage value on each dc source in case of dc voltagebalancing.Because of producing output voltage with nonzero error, thesingle-state modulation has a non-linear control characteristicand generates low-order harmonic voltages for the wholemodulation range. Compared to conventional PWM methods,overmodulation in single-state PWM method losses itsoriginal meaning. However, overmodulation can be supposedas an approach to extend the reference fundamental voltage

V(l)mrej to a maximum value of six-step mode, ie, attaining

a value of 2 VSMin • where VsMin is a selected value not toH

exceed the minimum total instant dc voltage. That is,overmodulation happens if reference fundamental voltage

V(l)mrej exceeds the value of VsMin /.J3 . The active

voltages in single-state overmodulation can be deduced fromprinciple control between two-limit trajectories. As a result,three following active voltages, corresponding to 3 limitmodulation indexes ofmreFI,I.05 and 1.1 can be deducedfor two-mode overmodulation.For mreFI, the active voltages are defined as

VSMin B 211kx 2H) k 2 3Vx12 = r:; cos( - --+ - ; x = 1" (20)....;3 3 3

For mreF1.05, the leg voltage can be described in the form as:

{

VSMin for fx > VSMin

V xo = fx for 0:::; fx < VSMin

° for fx <°2m 2H

where f x = 0.5VSMin + VSMin cos(B - - +-) (22);3 3

x = 1,2,3.For mreFI.I, the leg voltage is of square waveform

with peak-to-peak value equal to VsMin• For the last two cases,

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The 7th International Conference on Power ElectronicsOctober 22-26, 2007 / EXCO, Daegu, Korea

the active voltages can be deduced from the defined legvoltages after rejecting the zero sequence component.Principle control between two limit trajectories: for a givenmodulation index firef, active voltages can be deduced from

the active voltages V x12,mA' V x12 ,mB ~ corresponding two

defined limit modulation indexes of mA and mB :

control characteristic of proposed method compared toothers can be obviously followed for case of small number oflevels (Fig.2,4 and 8) and large difference ofdc source values.For dc source unbalance, the implementing of SSPWMmethod can produce SOfie even harmonics of low orders. Inthe studies, the proposed SS PWM can favorably contributeto reducing their amplitudes (Fig.3,5 and 7).

After having the active voltages, the further step similarly asthe above described algorithm can be implemented forovermodulation.

• d ~ 16 1~ 26 o&er 36 3~ ~ 45 56

• amplitude b)

Fourilr analysis of va:1.:5...,.---------~

1.0

o. III I. II

0.:5

a)

Fourier anollysis of va:1.:5-,.-------------,

1.0

0.0 .1 II

d ~ 16 1~ 26 ~ 36 3~ ~ ~ :56• order

••• amplitude

0.:5

-1.:5

-2.0'" :=::::;:=:::::;:=:::::;::;::::::;::::::::::;::=::;:::=~10·3

• d 16 1~1 Tf~E 2~ Jb 3~ ~

1.:5

2.0-,.---------------,

0.5

0.0 o~o 0~2 0~3 0~4 0~5 0~6 0~7 0~8 0~9 1 ~Omref

o F5COM + F5UNCOM .i:J. F51deal x LinMod

1.0

2.5

2.0

1.5

Figure 3: 5-level inverter. Influence of dc voltage unbalance on theoutput. Diagrams ofphase load voltage and harmonic analysis in SSPWM for case a) conventional SS PWM and b) proposed SSPWM. Dc sources: Vd1=1.2; Vd2=O.6;Vd3=O.9; Vd4=1.4 ; mreFO.6.

Figure 2: Five-level inverter. Diagrams of Control characteristicsofSingle-state PWM methods for unbalanced dc sources: Vd1 =1.2;Vd2=O. 6;Vd3=O.9; Vd4=1.4.

(24)

(23)

SIMULATION AND CHARACTERISTICSv.

V x12 ,m =(1 -lJ)Vx12 ,mA + 1]Vx12 ,mB

m-mA1]=----

mB-mA

A generalised conclusion for PWM method for variouschanges of dc voltage sources, would be impossible. Theresults would be deduced case by case. Because the method isproposed for possible minimised voltage error ~ it can expectan improvement of output voltage compared with anotherconventional SS PWM method for similar number ofswitchings.The control characteristics expressed as the function ofamplitude of the fundamental voltage for variable referencemodulation index. In the diagrams, for several discretereference modulation indexes selected as 0.1 ~0.2, ..,1 thefundamental voltage were calculated for 5-, 7- ang 11- levelinverters and drawn as shown in Fig.2,4 and 6. Fordemonstration, the offset was proposed with medium

common mode voltage VOr~l = (VOMax + V OMin ) /2 [2]. In

the diagrams, FkCOM, presents the amplitude offundamental voltage obtained from the proposed method,FkUNCOM presents the amplitude of fundamental voltageobtained from conventional single-state PWM withoutconsideration of dc-source unbalance. FkIdeal presents thecontrol characteristic of SS PWM for dc balance condition.The LinMod presents a linear control characteristic ofthree-state and four-state PWM methods on condition of dcsource balance.A significant advantage of the proposed method is that

approximate linearity of control characteristic can beobtained in a large range of modulation index (Fig. 2.4,6,8and 9). As a result, the reducing of harmonic content in theproposed method compared to conventional single-statePWM would be expected in most voltage range. Fordemonstration, the diagrams of harmonic analysis formreFO.6 for 5-,7- and II-level inverters were drawn for twocases of : a) SS PWM method without unbalanceconsideration and b) proposed SS PWM method with dcunbalance consideration. If the difference between dcsources are held low (compare Fig. 4 and 9)~ and particularlyif the number of level is high (Fig.7). then the obtainedcontrol characteristics are nearly linear . The advantageous

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The 7th International Conference on Power ElectronicsOctober 22-26, 2007 I Exeo, Daegu, Korea

4.0...,,..--------------------,

Figure 4: Seven-level inverter. Diagrams of Single-state PWMmethods for unbalanced de sources: Vdl=1.2~ Vd2=O.6~ Vd3=O.9~

Vd4=l.I ~ Vd5=O.5~ Vd6=1.3~

advantages of proposed PWM method for improving thecontrol characteristic and possible reducing the harmonics oflow orders. Since the described features of output voltageswere studied for open loop control, it is expected to obtaineven better output performances in closed loop control.

x LinMod+ F7UNCOM L!. F71deal

o~ o~ d4 o~ o~ oS o~ o~ 1~mref

I! F7COM

0.5

0.0o~o

1.5

1.0

3.5

2.0

2.5

3.0

o F11COM + F11 UNCOM .a.. F111deal x LinMod

Fourier oInoilysis of Vol:

2.5

2.0

3.0

1.5

1.0

3.5,.,,......--------.....,

·1

1.5

2.5

1.0-

3.0-

3.5.,rr-----------.,

2.0-

·1

-2

·3

.4,..l ~::::;:::::::::;::::::::;::::::;:==;:=:::::;:===;~10·3 -4,..l ~::::;:::::::::;::::::::;::::::;:==;:=:::::;:==;~10·3

• J 1~ T~E ~ ~.6 1~ T~E 2~ 4bFourier oInoilysis ofn: Fourier oInoilysis of Vol:

Figure 6: II-level inverter. Diagrams of Control characteristics ofSingle-state PWM methods for unbalanced de sources : Vdl= 1.2~

Vd2=O.6~ Vd3=O.9; Vd4=l.I; Vd5=l.O~ Vd6=1.3~ VdFO.6~ Vd8=1 ~

Vd9=1.2; VdlO=1.5.

Fourier oInoll\lSiS of Vol:2.0.,,......----------,

1.8

1.6

1.4

1.2

1.00.8

0.6

0.4

0.2

0.0 I I

.6 16 ~~ 26 o;:er~ ~ ~ ~ 56

JiI ..mplitudeb)

6 ~ 116 1~ 26 2~ 36 3~ 4b .i 56• order

JiI ..mplitudea)

"':=::::::;::::::::;::::::::;::::::::;:::::::;:::::::::;:::::::::;::::::::10.3

16 1~ :z6 2~ 36 3~ ~TIME

2.n-. ....-----------,

1.8

1.6

Figure 7: II-level inverters . Single-state PWM method forunbalanced de sources : Vdl=1.2~ Vd2=O.6~ Vd3=O.9~ Vd4=l.I ~

Vd5=l.O~ Vd6=1.3~VdFO.6~ Vd8=1~ Vd9=1.2~VdlO=1.5. Diagrams ofphase load voltage and harmonic analysis of phase load voltage formreFO.6 for a) without de source unbalance consideration and b)with de source unbalance consideration.

Figure 5: Seven-level inverter. Single-state PWM method forunbalanced de sources Vd1=1.2; Vd2=O.6~ Vd3=O.9~ Vd4=l.I;Vd5=O.5; Vd6=1.3. Diagrams of phase load voltage and harmonicanalysis of phase load voltage for mreFO.6 for a) without de sourceunbalance consideration and b) with de source unbalanceconsideration.

VI. CONCLUSIONS

The paper has proposed a single-state PWM techniquewith minimised voltage error for multilevel inverter oncondition of unbalanced dc sources. The flexible behavior ofthe method is presented by possible control of commonmode, whose proper selection can be efficient for optimisingthe switching losses. The algorithm has shown the

0.5

o0-' :=:~::::::~~~~=:;::::::;::~

• 6 ~ 16 1~ 26 o::er 36 ~ .il ~ 56Ji amplitude a)

0.5

Ji amplitude b)

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The 7th International Conference on Power ElectronicsOctober 22-26, 2007 I Exeo, Daegu, Korea

2.5-' ,...------------------------,

2.0

1.5

1.0

0.5

o.01..J ~==:::;:==::::::;====:;====;:::::::==:;:::::::==::;===:::;:::==::::;::::==::::;::==~O~O 0~2 0~3 0~4 0~5 0~6 0~7 0~8 O~Q 1~0

mref

o F5COM +F5UNCOM .D. F5ldeal x LinMod

Figure 8: Diagrams of Control characteristics of Single-state PWMmethods in 5-level inverters for unbalanced dc sources Vdl=O.8~

Vd2=1.3~ Vd3=O.9~ Vd4=1.2.

4.01.,,....------------------------..,

[3] Wei, S., Wu, B., Li, F., and Liu, C.: "A general space vector PWM controlalgorithm for multilevel inverters'. Proc. IEEE Conf APEC, 2003, pp.562-568[4] Celanovic, N., and Boroyevich, D.: "A fast space vector modulationalgorithm for multilevel three phase converters', IEEE Trans., 2001 ,IA-37,pp.637-641[5]Jose Rodriguez, Luis Moran, Pablo Correa and Cesar Silva,"A VectorControl Technique for Medium-Voltage Multilevel Inverters', IEEETRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 49, NO.4,AUGUST 2002[6] N. Celanovic, D. Borojevic," A comprehensive study of neutral-pointvoltage balancing problem in the three-level neutral-point-clamped voltagesource PWM inverters" APEC '99 Proceedings, Volume: 1 , Page(s): 535-541

[7] M.D. Manjrekar, P.K. Steimer, and T. A. Lipo," Hybrid MultilevelPower Conversion System:A Competitive Solution for High-Power Applications", IEEETRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 36, NO.3,MAYIJUNE 2000,pp. 834[8] N. V.Nho,H.H. Lee,Generalized Carrier PWM Algorithms For MultilevelInverters With Unbalanced DC Voltages,Proceeding ofthe 37th IEEE PowerElectronics Specialists Conference PESC 18_22nd June 2006, Jeju , Korea[9] N.V.Nho,H.H.Lee,"Carrier PWM Algorithm For Multi-leg MultilevelInverters', EPE 2007 - 12th European Conference on Power Electronics andApplications 2 - 5 September 2007, Aalborg, Denmark

3.5

3.0

2.5

2.0

1.5

1.0

0.5

[I F7COM

O.O.J ~I==::::;:==:::::;1====;:1==::::;:1==:::::;'====;::1==::::;:,==:::::;1====;:'==~I0.0 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

mre1

i F7UNCOM i F71deali LinMod

Figure 9: Diagrams of Control characteristics of Single-state PWMmethods in 7-level inverters for unbalanced dc sources :Vdl=1.3;Vd2=O.9; Vd3=O.9: Vd4=1.2; Vd5=O.8; Vd6=1.2.

ACKNOWLEDGMENT

The authors would like to thank Vietnam NationalUniversity-HCM for partly supported. The authors wouldlike to also thank to Korea Ministry of Commerce~ Industryand Energy and Ulsan Metropolitan City which partlysupported this research through the Network-basedAutomation Research Center (NARC) at University ofUlsan.

REFERENCES[1] G. Carrara, S.Gardella,M. Marchesoni,R. Salutari, andG. Sciutto, "A new multilevel PWM method- A theoreticalanalysis," IEEE Trans. Power Electronics, vol.7, pp.497-505 1992

[2] B. P. McGrath, D.G .Holmes," Multi-carrier PWM strategies formultilevel inverters," IEEE Trans. Industrial Electronics, vol. 49,pp.858-867, August 2002

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