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Low Voltage Cascode Current Mirror in a 1.8 GHz

Variable Gain Low Noise Amplifier (VGLNA)Lini Lee*, Roslina Mohd Sidek*, S. S. Jamuar* and Sabira Khatunt

Department of Electrical & Electronic Engineering,tDepartment of Computer & Communication Systems Engineering,

Faculty of EngineeringUniversity Putra Malaysia, 43400 Serdang,

Selangor, MalaysiaE-mail: , {roslina, ssjamuar, sabira geng.upm.edu.my}

Abstract- A high frequency CMOS variable gain low noiseamplifier (VGLNA) employing a low voltage cascode currentmirror cell is proposed. The 'variable' concept is to prevent theunwanted saturation phenomenon due to large input signal. Adesign technique based on the proposed low voltage cascode cellconsumes minimal voltage headroom without sacrificing theaccuracy of the circuit. With a 0.18 um CMOS technology, thistechnique is applied to design a 1.8 V VGLNA operating at 1.8GHz for GSM band application. The simulation results revealthat the maximum gain is 15.18 dB with gain tuning range of 4.6dB and noise figure is less than 1.9 dB with the powerconsumption of 74 mW.

I. INTRODUCTION

Current sources are widely used in amplifiers, either single-stage or differential amplifiers. In these circuits, currentsources act as a large resistor without consuming excessivevoltage headroom. Some digital-to-analog converters (DAC)employed an array of current sources to produce an analogoutput proportional to digital input signal. Current sources, inconjunction with "current mirrors" can perform usefulfunctions in analog signals. Some modifications to a currentmirror, act as a low voltage cell can bring in lots ofadvantages to the analog world especially in the wirelesscommunication field. With the trend towards fully integratedwireless transceivers which demand portable and low powerconsumption devices [1], a breakthrough of design techniquesin transceivers is highly desirable.

This paper presents a design of variable gain stage utilizinga cascode current mirror as a low voltage cascode cell for avariable gain low noise amplifier (VGLNA). A variable gainin a LNA is to prevent saturation of the receiver when theinput signal is relatively large. There has been several gaincontrol techniques presented, such as using a bypass switch inthe main amplifier and achieving different gain levels [2].However, the gain, linearity and the return loss are no longercontrollable parameters and the switch path may induce losses.Another popular method is splitting a portion of current fromthe amplifier [3-4]. However, in this technique, the return lossbecomes worse and higher noise is introduces in low gainmode.

In this paper, a high frequency VGLNA employing acascode current mirror which could eliminate the accuracy

and voltage headroom trade-off to achieve gain control ispresented. This work demonstrates a CMOS VGLNAworking at 1.8 GHz frequency band, capable to achieve gaincontrol as well as maintaining its input and output return lossin different mode (high gain and low gain modes) withoutdegrading the noise performance.

II. VARIABLE GAIN Low NOISE AMPLIFIER CIRCUITDESIGN

Among the common structure of single-ended amplifiers,namely, resistive termination, 1/gm termination, shunt-seriesfeedback and inductive source degeneration, the last one hasthe best noise performance. Here, a single stage cascode LNAwith inductive source degeneration topology is used, asshown in Fig. 1. A single-stage topology is chosen tominimize the power dissipation and to improve third-orderintercept point (IP3) performance.The proposed VGLNA can meet two merits, the

unconditionally stability in each stage and low powerconsumption. A LNA is the first functional block in a wirelessreceiver. At the early stage of a receiver, the noise figure (NF)of the LNA is the dominant issue as the received signal isvery small. However, as the received signal becomes large,the 11P3 becomes an important parameter to prevent thereceiver from reaching saturation. Therefore, a cascodecurrent mirror is added to act as the variable gain stage,completing the gain-adjustable mechanism [5].

Vdd

L3

Ld

|M2NMOS

L2RFin ~~~NMOe

Lg

Ls

Fig. 1. Cascode low noise amplifier (LNA) with inductive sourcedegeneration structure.

0-7803-9740-X/06/$20.00 C 2006 IEEE F3D)-2 ISCIT1 200(6

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A. Cascode stage with inductive degenerationFor the cascode structure, the inductive source degeneration

topology is adopted in order to obtain the best NF [5].Referring to Fig. 1, the inductively degenerated commonsource (CS) input consists of transconductors, MI - M2 andgate and source inductors, Ls and Lg, respectively. Theinductor, Ls has the benefit of simultaneously achieving bothinput and noise matching. Using this topology, a controllablereal term at the input impedance which is equivalent toLs.gm/Cgs can be generated. At the frequency of operation,value of Ls can be chosen in order for the real term to be madeequal to 50Q. Thus maximum signal is delivered with thegain optimized. For the power matched at resonance, the realpart of input impedance also need to be equaled to sourceresistance. For the noise figure calculation, the size of theinput transistor is chosen such that it minimizes the noise asshown in the following expressions [5]:

F.in =1+ .. ) (1)

where COT = gm/Cgs, the unity gain frequency with gm is thetransistor transconductance and Cgs is the gate sourcecapacitor. y = 3/2 is the channel thermal noise, c is thecomplex correlation term which is equal to jO.395, 6 = 4/3 isthe coefficient of gate noise. As observed from (1), Fmin iseffective for CO<COT and the NF increases with frequency.Owing to the down scale of CMOS process, the COT raises,allowing circuits to operate at higher frequency whilemaintaining the minimum noise figure. With the Fmin at thefrequency of interest, the optimal transistor size can becalculated as:

w''opt

1

3.*t*.L.Cco .R5

then the cascode current source M4 and M6 consumesminimum headroom (the overdrive of M4 plus that of M6)while M3 and M4 sustain equal drain-source voltages,allowing accurate copying of IREF. Comparing this structurewith the traditional cascode current mirror in Fig. 3, theminimum allowable voltage is two overdrive voltage plus onethreshold voltage. One threshold voltage is "wasted" in theheadroom [6]. Therefore, in this work, the proposed cascodemirror with two overdrive voltage headroom can be termed as"low-voltage cascode" and implemented as variable gainstage. The gain tuning range achieved in this work is 4.6 dB.The advantage of this gain controlled mechanism is that thegain variation is achieved without degrading the noiseperformance.At the output, the inductor Lo and capacitor CO formed an

output LC-tank circuit to tune the VGLNA to resonancefrequency, 1.8 GHz as well as to match the output impedance.Combined the circuits of Fig. 1 and 2, a VGLNA is

proposed as shown in Fig. 4. The VGLNA is designed towork at 1.8 GHz and it is simulated to meet the best desiredrequirements.

(2)

with R,=50Q and L is the gate length. It is noted that the noiseparameters:y, 6 and c in the above calculation are consideredindependent of the bias voltage.

B. Variable gain stage with current mirrorIn this work, a modified cascode current mirror is used to

achieve gain control function. As shown in Fig. 2, a cascodecurrent mirror comprised of transistors M3-M6 are employedwith a reference current, IREF and bias voltage, Vb. Thesetransistors are controlled by the bias voltage, Vb. Voltage,Vcon from the LNA stage steers the current between thecascode current mirror and LNA stage.The key property of a current mirror is to allow precise

copying of the current with no dependence on process andtemperature. Therefore, to suppress these dependence like thechannel-length modulation, a cascode current mirror as shownin Fig. 2 that have identical drain-source voltage and a highoutput resistance is proposed. These transistors are insaturation and proper ratioing ensures that VGS5 = VGS6. If

VCon = VGS5 + (VGS3 -VTH3 ) = VGS6 + (VGS4 VTH4 ), (3)

Fig. 2. Proposed cascode current mirror as variable gain stage.

Vdd

IREF -

M3 M4X NOS NOS

l < M2N Os OS

Fig. 3. Cascode current mirror with voltage headroom consumed.

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Fig. 4. Schematic of the proposed VGLNA.

III. SIMULATION RESULTS

The VGLNA is simulated and Fig. 5 to 9 shows thesimulation results. The VGLNA obtains gains of 15.2 dB and10.6 dB in the high gain mode (HGM) and low gain mode(LGM) respectively. As shown in Fig. 6, the noise figure of1.82 dB is achieved regardless of operating in HGM or LGM.In the HGM, the input return loss is -14.2 dB while in theLGM, the Si 1 is equal to -18.8 dB. In Fig. 8, it shows that thereverse isolation at the HGM is better than the LGM with theoverall reverse isolation less than -38 dB. In the HGM, theoutput return loss is -4.6 dB. Since this LNA would beintegrated with the mixer in the same chip, there is nothing toworry about this low output return loss. As for the two tonetesting, two tones are located at 1.80 GHz and 1.82 GHz andthe IIP3 simulated in the HGM is 0.912 dBm. The powerconsumed by the 1.8 GHz VGLNA is reported to be 74 mW.

15-

10-5-

0-

-5--10-

1-5-

1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3

freq, GHz

Fig. 6. Noise figure (NF) of the proposed VGLNA in low gain mode(LGM) and high gain mode (HGM).

LGM E E E E

Fig. 5. Voltage gains in the low gain mode (LGM) and high gainmode (HGM).

2

freq, GHz

Fig. 7. S of the proposed VGLNA in low gain mode (LGM) andhigh gain mode (HGM).

1. 0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0

freq, GHz

/ I

HGM :3 c c e---c

co7;

1100

U)

-70-1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0

freq, GHz

Fig. 8. S12 of the proposed VGLNA in low gain mode (LGM) and highgain mode (HGM).

0- LGM

HGM-2-

(1)

REFERENCES

[1] C. Guo, et al., "A fully integrated 900-MHz CMOS wirelessreceiver with on-chip RF and IF filters and 79-dB imagerejection," IEEE J. Solid-State Circuits, vol. 37, pp 1084-1089,2002.

[2] R. Point, M. Mendes, W. Foley, "A Differential 2.4 GHzSwitched-Gain CMOS LNA for 802.1 lb and Bluetooth," IEEERadio and Wireless Conference 2002, RAWCON 2002, pp. 221-224, Aug. 2002.

[3] E. Sacchi, I. Bietti, F. Gatta, F. Svelto and R. Castello, "A 2 dBNF, fully differential, variable gain, 900 MHz CMOS LNA,"Symp. On VLSI Circuits 2000, pp. 94-97, June 2000.

[4] K. L. Fong, "Dual-band High Linearity Variable-Gain LowNoise Amplifiers for Wireless Applications," IEEE Int. Solid-State Conference 1999.

[5] T. H. Lee, The design of CMOS Radio Frequency IntegratedCircuit, 2nd ed., Cambridge University Press, 1998.

[6] D. A. Johns and K. Martin, Analog Integrated Circuit Design,John Wiley & Sons, Inc., 1997.

freq, GHz

Fig. 9. S22 of the proposed VGLNA in low gain mode (LGM)and high gain mode (HGM).

IV. CONCLUSIONS

A 1.8 GHz VGLNA has been designed in 0.18 ptm CMOSprocess for GSM application. The VGLNA uses a modifiedcascode current mirror technique to achieve gain controlfunction. Only minimal voltage headroom is required in thecascode current mirror for the variable gain stage. Regardlessof gain modes, the VGLNA achieves NF of less than 1.82 dBwith input return loss of -14.2 and -18.8 in HGM and LGMrespectively. Operating at 1.8 V supply voltage, the circuitprovides a maximum gain of 15.2 dB and a minimum gain of10.6 dB. In the linearity response, the VGLNA acquires IIP3of 0.912 dBm in HGM. The achieved low NF, gain andoverall results fulfill the specifications for a 1.8 GHz LNAdesign. Thus, this VGLNA can be used to achieveamplification in a wireless receiver front-end which requires afully integrated, low noise and low power consumptionarchitectures.

ACKNOWLEDGMENT

This research is supported by Ministry of Science,Technology and Innovation (MOSTI) of Malaysia throughNational Science Fellowship (NSF).