IEEE® 1588 Precision Time Protocol for Telecom and ... · • IEEE 1588 is the standard for a...
Transcript of IEEE® 1588 Precision Time Protocol for Telecom and ... · • IEEE 1588 is the standard for a...
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.
June 2012
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• Introduction of IEEE 1588
• Basics of Precision Time Protocol
• Basics of Synchronization
• Hardware: IEEE 1588 hardware assist block
− Timer
− Time-stamping
− Interrupts, Registers and signals
• Software: Device driver and application
• Test setup and results
• Usage
• Summary
• References
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• IEEE 1588 is the standard for a precision clock synchronization
protocol for networked measurement and control
− The standard defines a Precision Time Protocol (PTP) designed to
synchronize real-time clocks in a distributed system
− Intended for local area networks
− Targeted accuracy of microsecond to sub-microsecond with easy
configuration and fast convergence between components
− IEEE 1588-2002 (Version 1) approved September 2002 and
published November 2002
− IEEE 1588-2008 (Version 2) approved March 2008 and published
August 2008
Available from the IEEE 1588 web site
(http://www.nist.gov/el/isd/ieee/ieee1588.cfm)
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NTP GPS TTP IEEE 1588
Target Uses Autonomous systems
dispersed over a wide
area. Time information
passed via messages
on the Internet.
Autonomous systems
dispersed over a wide
area. Time information
passed via satellite.
Tightly integrated ,
closed systems usually
connected via a bus or
specialized TDMA
network
Groups of relatively
stable components,
locally networked (a
few subnets),
cooperating on a set
of well defined tasks
Target Accuracy under 1ms possible,
1-10ms typical in LAN,
<100ms over the
Internet
Sub microsecond
Sub microsecond
Sub microsecond (±
50ns typ)
Synchronization
Resolution Time Minutes to hours < Minute
Resource
Requirements Moderate network and
compute footprint
Moderate compute
footprint
Moderate compute
footprint
Small network and
compute footprint
Latency Correction Yes Yes Configured Yes
Update Interval Variable, but normally
seconds
Approximately every
second
Milliseconds Approximately every
2 seconds
Hardware Required No Yes Yes Yes, to achieve
greatest accuracy
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Example:
• A = 106 – 101 = 5
• B = 108 – 111 = -3
• Delay = (5-3) / 2 = 1
• Offset = (5+3) / 2 = 4
PTP Appl.
Master Clock
G/MII G/MII
Slave Clock
PTP Appl.
t0
t3
t2
t1
Estimated
Send Time
(100)
Precise
Send
Time
(101)
Precise
Receive
Time (106)
Precise
Send Time
(111)
Precise
Receive
Time
(108)
Offset
Computation
100
102
110
104
106
108
112
104
106
114
108
110
112
116
A
B
Key Equations:
• A = t1 – t0 = Delay + Offset
• B = t3 - t2 = Delay – Offset
• Delay = (A+B) / 2
• Offset = (A-B) / 2
UDP port 319: Sync and Delay_Req
UDP port 320: Follow_up,
Delay_Resp, and Mgmt
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SYNC Messages
• Master sends an estimate of the
sending time
• When received by a slave clock,
the receipt time is noted
FOLLOW_UP messages:
• Always associated with the
preceding Sync message
• Contain the „precise sending time‟
of SYNC message measured
close to the physical layer of the
network
DELAY_REQ messages:
• Issued by clock nodes in the
„Slave‟ state
• When received by the master
clock the receipt time is noted
DELAY_RESP messages:
• Always associated with a
preceding Delay_Req message
from a specific slave clock
• Contain the receipt time of the
associated Delay_Req message
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PTP
UDP
IP
MAC
PHY
Master Clock
PTP
UDP
IP
MAC
PHY
Slave Clock
Milliseconds
of delay and
variation
introduced
by protocol
stack
Network
Hardware time-stamping
removes protocol stack delay
Milliseconds
of delay and
variation
introduced
by protocol
stack
IEEE 1588 PTP Code
Network protocol
stack & OS
PHY
Timestamp
generation /
message
detection
MII /
GMII
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PTP
UDP
IP
MAC
PHY
(Slave)
PTP
UDP
IP
MAC
PHY
(Master)
Switch / Router with
Boundary Clock
PTP
UDP
IP
MAC
PHY
Master Clock
PTP
UDP
IP
MAC
PHY
Slave Clock
Network 1
Synchronization across multiple network/subnets
Network 2
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Node A Node B
Clocks advancing at the same rate,
but are 8 minutes apart
Clocks in frequency alignment, with constant offset*
: : : :
*also called Syntonous clocks
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Node A Node B
Clocks start at the same time,
but are advancing at different rates
Clocks not in frequency alignment, with zero initial offset
: : : :
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Node A Node B
Clocks advancing at the same rate,
with the same initial offset
Clocks in frequency alignment, with zero offset (same time)
: : : :
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• Timer Logic
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Time-Stamp
Nominal
Clock
External
Clock Ref
Platform
Clock Ref
32-bit Accum Carry
Bypass Enable
32-bit
Addend
64-bit Counter
TMR_CNTH/L
TCLK_PERIOD
+
+
RTC Clock
eTSEC Tx
Clock
Software
Tip – ADDEND is modified to fine tune the slave clock
Tip – TMR_CNTL/H are modified when difference between master and slave is huge
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• Four choices of input clock
• Addend and accumulator provides a digital fractional divider
• Provision for bypassing the divider logic
• ADDEND = 232 ÷ FreqDivRatio
− If input clock = 150MHz & desired nominal clock = 100MHz
− ADDEND = 232 ÷ (150/100) = 0xAAAA_AAAA
Nominal
Clock
External
Clock Ref
Platform
Clock Ref
32-bit Accum Carry
Bypass Enable
32-bit Addend
64-bit Counter
TMR_CNTH/L
TCLK_PERIOD
+ +
RTC Clock
eTSEC Tx
Clock
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• The 64-bit counter increments by TCLK_PERIOD on every pulse of “nominal clock”
• To represent time in nanoseconds, TCLK_PERIOD should be equal to reciprocal of frequency of “nominal clock”
− It is recommended to have TCLK_PERIOD as integral factor of 109
Example:
− Few integral factors of 109 : 2, 4, 8, 10, 16, 20…
− For Input clock = 333MHz, recommended choices for nominal clock are 100MHz,
125MHz, 200MHz and 250MHz
Nominal
Clock
External
Clock Ref
Platform
Clock Ref
32-bit Accum Carry
Bypass Enable
32-bit Addend
64-bit Counter
TMR_CNTH/L
TCLK_PERIOD
+
+
RTC Clock
eTSEC Tx
Clock
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• Example assumes the accumulator overflows after “9”, therefore ADDEND= 9 /
(150/100) = 6
• The resultant clock may not have 50% duty cycle or uniform period
6
+
Input Clock = 150MHz
Nominal Clock = 100MHz
Addend
= 9 / 1.5
= 6
Accumulator
Carry after 9
6 2 8 4 0
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• Systems which require to synchronize an external clock may
choose to bypass internal fine-tuning
• The counter runs on the input clock
• SPI or IIC can be used to fine-tune VCXO
Nominal
Clock
External
Clock Ref
Platform
Clock Ref
Carry
Bypass
Enable
Accum
Addend
Counter
TMR_CNTH/L
TCLK_PERIOD
+ RTC
Clock
eTSEC Tx
Clock
VCXO
IIC/SPI
DAC
+
Tip – External clock needs to be tuned
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Nominal
Clock
External
Clock Ref Platform
Clock Ref 32-bit Accum
Carry
Bypass Enable
32-bit
Addend
+
RTC Clock
eTSEC Tx
Clock
64-bit Counter
TMR_CNTH/L
TCLK_PERIOD
+
64 –bit ALARM
≥
32-bit FIPER
TCLK_PERIOD
−
Prescaler GCLK
PULSE_OUTn
ALARM_OUTn
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• ALARM_OUT is generated when counter is equal to or greater than ALARM
− can be used to trigger the periodic pulse generator
• With FIPER as the initial value, a down-counter decrements by TCLK_PERIOD on every pulse of nominal clock
• A pulse is generated when the down counter reaches zero or less than TCLK_PERIOD
− Generates periodic pulse with a width of one period of the pre-scaled output clock
− Down counter is reloaded; the process repeats
• GCLK outputs pre-scaled output clock
Nominal
Clock
64-bit Counter
TMR_CNTH/L
TCLK_PERIOD
+
64 –bit ALARM
≥
32-bit FIPER
TCLK_PERIOD
−
Prescaler GCLK
PULSE_OUTn
ALARM_OUTn
23 TM
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• FIPER should be programmed to an integer multiple of TCLK_PERIOD value to ensure a period pulse being generated correctly
• To generate 1PPS signal:
− FIPER = <109 nanoseconds> / TCLK_PERIOD
• To align PPS signal with TMR_CNT:
− Program ALARM to a value which is a whole number of seconds, and greater than the present TMR_CNT
ALARM = (floor{(TMR_CNT/109) + n})*109
Example: For TMR_CNT = 5.3s and n=2, ALARM = 7s
− Set TMR_CTRL[FS] to trigger FIPER by ALARM
Tip – Only ALARM1 can trigger FIPER1.
Nominal
Clock
64-bit Counter
TMR_CNTH/L
TCLK_PERIOD
+
64 –bit ALARM
≥
32-bit FIPER
TCLK_PERIOD
−
PULSE_OUTn
ALARM_OUTn
24 TM
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mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
• Should user need to change the
value of TMR_CNT, the following
procedure should be followed to
realign the PPS signal:
− Calculate the new value of ALARM
− Write new values to TMR_CNTL/H
− Write calculated values to ALARM1L/H
− Rewrite FIPER to reset the down
counter
− Set TMR_CTRL[FS]
Nominal
Clock 64-bit Counter
TMR_CNTH/L
TCLK_PERIOD
+
64 -bit ALARM
≥
32-bit FIPER
TCLK_PERIOD
−
PULSE_OUTn
ALARM_OUTn
25 TM
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
• TMR_CNT_L should be read first to get correct 64-bit TMR_CNT_H/L
counter values
− Reads from the TMR_CNT_L register copies the entire 64-bit clock time into
shadow registers
• TMR_CNT_L should be written first
− Contents of the shadow registers are copied into the TMR_CNT_L and
TMR_CNT_H registers following a write into the TMR_CNT_H register
• Writing the TMR_ALARMn_L register deactivates the alarm event
• Writing the TMR_ALARMn_L followed by the TMR_ALARMn_H
register rearms the alarm function with the new compare value
• Writing new value to FIPER register resets the down counter used in
PULSE_OUT generation
ATTENTION – Above recommendations should be strictly followed.
Any violation may result in unpredictable results.
TM
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire,
ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC,
Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of
Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack,
CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and
Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service
names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
.
26
27 TM
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
• There are three different time-stamp capture triggers
− Reception of a packet
− Transmission of a packet
− On the positive or negative edge of the external trigger
28 TM
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mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
For eTSEC:
− On detection of SFD, the value of TMR_CNT_H/L is copied to TMR_RXTS_H/L if RCTRL[TS] in eTSEC is set to 1
− In addition, the time-stamp is inserted into the packet data buffer as padding alignment bytes if:
TMR_CTRL[RTPE] is set to 1 AND
RCTRL[PAL] (receive pad alignment length) is set to a value greater than or equal to 8
− eTSEC indicates reception of PTP packet to CPU
− CPU reads time-stamp from RxBuffer or TMR_RXTS_H/L
29 TM
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
For dTSEC:
− When enabled by setting RCTRL[RTSE] in dTSEC, every incoming
packet will be accompanied with an 8-byte time-stamp
− The BMI will extract the timestamp and copy it to the timestamp field
within the internal buffer
− The whole frame together with timestamp is copied into external
buffers and FD is enqueued to indicate reception of PTP packet to
CPU
− CPU reads time-stamp from Frame Descriptor
30 TM
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
• eTSEC supports a two-step clock
− The time-stamp of frame being transmitted is stored in registers or frame control buffer
− The follow-up packet carries the actual time-stamp of previous packet
• eTSEC supports selective time-stamping for Tx packets using TxFCB[PTP]
• In dTSEC, setting TCTRL[TTSE] to 1 ensures that all the packets will be time-stamped during transmission
• The packet ID and time-stamp are stored in the TMR_TXTS1-2_ID and TMR_TXTS1-2_H/L registers
31 TM
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
For eTSEC:
To get time-stamps of transmit packets on FCB, the following
requirements should be met:
TMR_CTRL[RTPE], TxBD[TOE] and TxFCB[PTP] should be set to 1
A minimum of two TxBDs are used per packet
• The first points to the start of the 8 byte TxFCB
• The second points to the start of frame data
The TxFCB, and at least the first 16 bytes of the TxPAL, must be located
in contiguous memory locations
− The time-stamp is written to memory location TxBD[Data Buffer
Pointer]+ 0x10
32 TM
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
For dTSEC:
− When enabled by setting TCTRL[TTSE], every requested transmit
packet will cause the return of a time-stamp value from the dTSEC
− The BMI receives the actual time-stamp after the frame is
transmitted
− In the TX confirmation phase, The BMI writes the time-stamp into
the time-stamp field in the internal buffer of the sent frame and
issues DMA request to internal buffer to external memory
− dTSEC also supports two-step clock
33 TM
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
• The polarity of TRIG_IN signal can be chosen using
TMR_CTRL[ETEPn]
• TMR_TEVENT[ETSn] is set if external trigger is received
• TMR_ETTS1–2_H/L stores the time-stamp
Attention – P1010 has 16 pairs of TMR_ETTSn_H/L registers
TM
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire,
ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC,
Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of
Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack,
CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and
Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service
names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
.
34
35 TM
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
• Generally PowerQUICC processors and QorIQ
communications processors have more than one
eTSEC/dTSEC(s)
• There is a single IEEE 1588 block shared among all eTSEC(s)
in a device
• Every FrameManager has its own instance of a 1588 hardware
assist block
− All dTSECs corresponding to an FM share the 1588 hardware assist
• However, there are some registers and interrupts dedicated per
eTSEC/dTSEC
Tip – Since the common 1588 time-stamping registers exist within the eTSEC1
memory space, the eTSEC1 controller must remain enabled in order to use 1588 time-stamping for any Ethernet port.
36 TM
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
• The Interrupt controller has different interrupt numbers
associated with IEEE 1588 interrupts of different eTSECs
• Interrupts generated on transmission or reception of Ethernet
packet are dedicated per-eTSEC
− These interrupts are indicated by TMR_PEVENT
• Interrupts generated by ALARM, FIPER and external trigger
(TRIG_IN) are registered to “eTSEC1 1588 timer”
− These events are shown by TMR_TEVENT
Internal Interrupt Number Interrupt Source
52 eTSEC1 1588 timer
53 eTSEC2 1588 timer
54 eTSEC3 1588 timer
37 TM
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
• All the registers of Hardware Assist IEEE 1588 are valid only
on the eTSEC1 memory region, except for the registers listed
below:
− TMR_TXTS1–2_ID : Transmit Time Stamp Identification Register
− TMR_TXTS1–2_H/L : Transmit Time Stamp Register
− TMR_RXTS_H/L : Receive Time Stamp Register
− TMR_PEVENT: Timer PTP Packet Event Register
− TMR_PEMASK : Timer Event Mask Register
− TMR_STAT : Timer Status Register
Attention – Access to any other register of “Hardware Assist IEEE 1588” from memory region other than eTSEC1 is illegal
38 TM
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
For dTSEC:
• All the registers of Hardware Assist IEEE 1588 are valid on FMan‟s 1588 timer module memory region except registers listed below which reside in the dTSEC‟s memory region:
− TMR_CTRL – is not the same to the TMR_CTRL register in the 1588 timer module
− TMR_PEVENT - Time-stamp event register
− TMR_PEMASK - Timer event mask register
• Comparing to eTSEC:
− No TMR_TXTS1–2_ID Register
− No TMR_TXTS1–2_H/L Register
− No TMR_RXTS_H/L Register
The BMI gets the time-stamp to put into the IC time-stamp field
39 TM
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
• TSEC_1588_CLK_IN: One of the four choices of input clocks
• TSEC_1588_CLK_OUT: Output of pre-scalar
• TSEC_1588_TRIG_IN[1:n] : External trigger input
• TSEC_1588_PULSE_OUT[1:n] : Output of FIPER
• TSEC_1588_ALARM_OUT[1:n]: Output of ALARM
Attention –
1. The number of TSEC_1588_TRIG_IN, TSEC_1588_PULSE_OUT
and TSEC_1588_ALARM_OUT may vary from device to device
2. There might be some variation in the name of the signal from device
to device
TM
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire,
ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC,
Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of
Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack,
CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and
Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service
names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
.
40
41 TM
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
• The application interacts with the
network layer to send/receive PTP
messages
• Using IEEE 1588 APIs, the
application gets the time-stamps of
packets sent or received
• Based on time-stamps, it decides to
tune the clock using IEEE 1588
APIs Hardware
Kernel
IEEE 1588
Timer APIs Network
Layer
Application Layer
Clock Servo
Mechanism
Messaging
Unit
42 TM
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
• Get the frequency of the input clock
− Calculate as explained earlier and feed results in ADDEND and TCLK_PERIOD
• Write desired value to TMR_PRSC and FIPER
• Calculate and feed ALARM register
• Set TMR_CTRL[FS] to trigger FIPER with ALARM
• Choose input clock using TMR_CLK[CKSEL]
• Start timer by setting TMR_CTRL[TE] to 1
• Initialize rest of the registers for time-stamps and interrupts are required
43 TM
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
• GET_RX_TIMESTAMP : To read time-stamp of packet received
• GET_TX_TIMESTAMP : To read time-stamp of packet transmitted
• GET_CNT : Read value of TMR_CMT
• SET_CNT : Write new value of TMR_CNT along with reinitializing
FIPER and ALARM
• ADJ_ADDEND : Write new data to ADDEND
• GET_ADDEND : Read ADDEND
TM
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire,
ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC,
Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of
Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack,
CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and
Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service
names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
.
44
45 TM
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
-200
-150
-100
-50
0
50
100
150
200
1 5 9 13 17 21 25 29 33 37 41 45 49 53 57 61 65 69 73 77 81 85 89 93 97 101 105 109 113 117 121 125 129 133 137
Plot the “Offset from Master” Raw Data
PTP stack evaluation version - will stop after 4 hours
-0,085857248; 0,000000000; 0,000000000; 0,000000000; 2152;
-0,000002152;-0,000002152; 0,000000000; 0,000000000; 3132;
-0,000002056;-0,000002056; 0,000000000; 0,000000000; 2960;
-0,000000856;-0,000000856; 0,000000000; 0,000000000; 2268;
0,000000264; 0,000000216; 0,000000808;-0,000000048; 1792;
0,000000608; 0,000000560; 0,000000808;-0,000000048; 1648;
0,000000448; 0,000000400; 0,000000808;-0,000000048; 1760;
0,000000112; 0,000000064; 0,000000808;-0,000000048; 1944;
-0,000000128;-0,000000176; 0,000000808;-0,000000048; 2032;
IEEE 1588 Master (MPC8313E-MDS-PB)
IXXAT IEEE 1588 application software IEEE 1588 Slave (MPC8313E-MDS-PB)
IXXAT IEEE 1588 application S/W
46 TM
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
Series1, 0
-100
-80
-60
-40
-20
0
20
40
60
80
100
1
215
429
643
857
1071
1285
1499
1713
1927
2141
2355
2569
2783
2997
3211
3425
3639
3853
4067
4281
4495
4709
4923
5137
5351
5565
5779
5993
6207
6421
6635
6849
7063
7277
7491
7705
7919
8133
8347
8561
8775
8989
9203
9417
9631
9845
10059
10273
10487
10701
Off
set
in n
s
Master to Slave Clock Offset
TM
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire,
ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC,
Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of
Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack,
CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and
Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service
names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
.
47
48 TM
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
• IEEE 1588 allows precision
control over a distributed
Ethernet network
• Precise timing delivery allows
drive units to be placed where
required − Traditional mechanical control
mechanisms can limit the
placement of systems
• Timing synchronization at the
drive enables flexibility in
system configuration − Issues due to mismatched
cable lengths are minimized
− Servos can be added or
deleted without having to
rewire other servos
• Industrial Control applications
typically augment IEEE 1588
hardware to provide trigger
inputs and outputs
Servo
Drive
Servo
Drive
Servo
Drive
Switch
E
E
E
Master Time
Motion Controller
ControllerE
Ethernet
Adapter
Servo
Drive
Servo
Drive
Servo
Drive
Switch
E
E
E
Master Time
Motion Controller
ControllerE
Ethernet
Adapter
Motion Controller
ControllerControllerE
Ethernet
Adapter
Peer Controlling Other Peers
Distributed Control
Switch
Master Time
Servo
Drive E
Motion Controller
Controller E
Ethernet
Adapter
Servo
Drive E
Motion Controller
Controller E
Ethernet
Adapter
Servo
Drive E
Motion Controller
Controller E
Ethernet
Adapter
Switch
Master Time
Servo
Drive E
Motion Controller
Controller E
Ethernet
Adapter
Servo
Drive E
Motion Controller
Controller E
Ethernet
Adapter
Motion Controller
Controller E
Ethernet
Adapter
Servo
Drive E
Motion Controller
Controller E
Ethernet
Adapter
Servo
Drive E
Motion Controller
Controller E
Ethernet
Adapter
Motion Controller
Controller E
Ethernet
Adapter
Servo
Drive E
Motion Controller
Controller E
Ethernet
Adapter
Servo
Drive E
Motion Controller
Controller E
Ethernet
Adapter
Motion Controller
Controller E
Ethernet
Adapter
49 TM
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
• IEEE 1588 allows
coordination and control of
Test and Measurement
equipment over a distributed
Ethernet network
• Precise timing delivery allows
test equipment to deliver
patterns and measure
responses at specific times
− Enables accurate time
stamping of measured data
− Allows coordination of input
stimuli and any associated
measured data
• Trigger inputs and outputs
enable coordination of other
devices
Remote Test
Controller
Pattern
Generator Test Board
Oscilloscope
Spectrum Analyzer
Logic Analyzer
Ethernet
Network
Trigger In
Test Point
Trigger Out
50 TM
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
Wireline Service Provider
BSC
IP Network
(Ethernet)
Ethernet
Ethernet
Head End/
Aggregation
Point
Head End/
Aggregation
Point
Synch/
Time
Server
Packet
Network
Broadband
(DSL/Cable)
Broadband
(DSL/Cable)
Femtocell /
router
Femtocell /
router
Femtocell /
router
Head End/
Aggregation
Point
Head End/
Aggregation
Point
Ethernet
Ethernet Synch/
Time
Server
Home
Home
Home
Wireline Service Provider
BSC
IP Network
(Ethernet)
Ethernet
Ethernet
Head End/
Aggregation
Point
Head End/
Aggregation
Point
Synch/
Time
Server
Packet
Network
Packet
Network
Broadband
(DSL/Cable)
Broadband
(DSL/Cable)
Femtocell /
router
Femtocell /
router
Femtocell /
router
Head End/
Aggregation
Point
Head End/
Aggregation
Point
Ethernet
Ethernet Synch/
Time
Server
Home
Home
Home
TM 51
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
Tweeting? Please use hashtag
#FTF2012
Facebook.com/Freescale Tag yourself in photos
and upload your own!
Session materials will be posted @ www.freescale.com/FTF Look for announcements in the FTF Group on LinkedIn or follow Freescale on Twitter
• Using IEEE 1588 Hardware Assist logic, sub-50ns
synchronization can be achieved over the network
• Hardware support for IEEE 1588 is available in all of the
devices of QorIQ communications processor family
• Currently used in industrial, telecom and consumer (audio-
video sync) applications
• Synchronized pulses and alarm functionality available in
the QorIQ communications processor family
TM 52
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C-Ware, the Energy Efficient Solutions logo, Kinetis,
mobileGT, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc.,
Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine,
Ready Play, SafeAssure, the SafeAssure logo, SMARTMOS, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All
other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc.
• Reference Manuals of QorIQ communications processor
• AN3423: Application note on IEEE 1588
• AN4326: Verification of the IEEE 1588 Interface
• http://www.nist.gov/el/isd/ieee/ieee1588.cfm
TM