ICC1 200703 LG 02 Placement

Placement and Power Optimization Lab 2-1Synopsys 20-I-071-SLG-007

During this lab, you will perform design exploration then perform placement and optimization (timing, area and power).

After completing this lab, you should be able to:

Apply placement constraints

Apply routing blockages

Verify design setup

Perform standard cell placement and optimization

Recognize and resolve congestion issues

Perform incremental optimization

Placement and Power Optimization

2

Lab Duration:90 minutes

Learning Objectives

Lab 2

Introduction

In this lab, you are provided with complete ORCA_TOP design data (netlist, timing constraints and floorplan) in a Milkyway database. You will apply placement constraints then perform standard cell placement

You will also perform power analysis and optimization after the placement has been completed.

Answers / Solutions

There is an ANSWERS / SOLUTIONS section at the back of each lab. You are encouraged to refer often to this section to verify your answers, or to obtain help with the execution of some steps.

Relevant Files and Directories

All files for this lab are located in the lab2_placement directory under your home directory.

lab2_placement/

orca_lib.mw/CEL

ORCA_TOP The synthesized and floorplanned design saved in Synopsys Milkyway format.

scripts/

physical_constraints.tcl A script used to add other physical constraints.

inputs_toggle_rate.tcl A script used to set statistical toggle rates for the input ports.

Lab 2-2 Placement and Power OptimizationSynopsys IC Compiler 1 Workshop

Lab 2

Instructions

Task 1. Checking Logical Design Setup

1. Start IC Compiler from the lab2_placement directory.

UNIX$ cd lab2_placement

UNIX$ icc_shell

2. Open the design library, and then make a copy for a working design cell. Open the copied design cell to perform the placement exploration.

open_mw_lib orca_lib.mw

copy_mw_cel -from ORCA_TOP -to explore

open_mw_cel explore

Note: Making a copy of a cell is optional. However, it is a good practice to work on a copy of a design cell to avoid accidentally overwriting the starting design cell.

3. Verify that the clock definitions are complete:

report_clock

report_clock –skew

report_port –v *clk

Question 1. Is the clock port specification complete?

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Question 2. What type of a port is SD_DDR_CLK defined on?

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Placement and Power Optimization Lab 2-3Synopsys IC Compiler 1 Workshop

Lab 2

4. Perform a timing sanity check using zero-interconnect delay mode:

set_zero_interconnect_delay_mode true

report_timing

Note: You can bring up the timing report in a separate window using “view report_timing” or “v rt”.

Question 3. Does the design meet setup timing? Should you worry?

....................................................................................................

5. Review the answer to question 1 in the Answers section.

6. Turn off timing for the scan enable net, since it will be handled later by place_opt:

set_ideal_network [get_ports scan_en]

7. Rerun the timing report. You should not see any violations now.

8. Check all constraint violations:

report_constraint –all (or better: v rc)

You should find that there are a number of hold violations, which we don’t care about now. Also, there are max transition and max capacitance violations on the reset networks, which high fanout synthesis will take care of during place_opt.

9. Don’t forget to turn off ZIC:

set_zero_interconnect_delay_mode false


Lab 2

Task 2. Placement Exploration

1. Open the graphical user interface (GUI).

gui

Note: “gui” is a function created for this workshop. It calls start_gui and end_gui to open and close the GUI depending on the current state.

2. Check for potential floorplan issues:

check_physical_design -for_placement

check_physical_constraints

Question 4. How many soft placement blockages exist in this design?

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Question 5. Does the floorplan contain narrow placement areas?

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Question 6. What is the design utilization reported after the “Narrow Placement Area” messages?

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3. So how is it possible that utilization is so high even before starting? Use the following command to get a quick picture of what is going on:

create_placement –quick

4. Have a look at the layout.

Question 7. What may be the cause of the high utilization?

....................................................................................................

5. If you have an answer to the question, validate your idea by executing a command to solve the problem. If you don’t know, check the answer section for this question, and execute the commands given there.


Lab 2

Run check_physical_constraints one more time. The utilization should be less than 80% now. But there are still some narrow channels reported, for which the macros are responsible.

Question 8. What is the easiest solution to prevent congestion in the narrow channels for this floorplan?

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6. Apply soft and hard keepouts to the floorplan as learned in lecture:

set physopt_hard_keepout_distance 5

set physopt_soft_keepout_distance 15

Note: Of course, you may perform a placement first to confirm that the settings above actually improve congestion, or you can take our word for it.

7. Perform placement, so you can see how the settings applied so far affect the design:

create_placement

legalize_placement

8. Generate and Analyze a placement congestion map.

Select the Reload button, confirm with OK, you should then see the congestion patterns in the layout view.

So far so good. The congestion is relatively distributed. There is what you could call a small congestion hot spot around the middle of the design, and between some of the RAM blocks. The bottom areas of the design seem to be a little more congested.

9. Have a look at a cell density map, to see whether the cell distribution may be problematic.

Select “Pin Density” from the already open dialog that is used to display the congestion, or choose PlacementPin Density Map. Set the Grid Dimension to 2 std cell heights and apply.


Lab 2

You should see that the pin distribution is pretty even, mostly in the 1-22 range, but you also see that there is higher density in the bottom areas of the design.

Close the density map.

10. Run placement with congestion options to see if congestion in the bottom areas of the design improves:

create_placement –congestion

legalize_placement

Did Congestion improve?

It seems that the hotspot in the middle of the design has gotten better.

Also, hardly visible, congestion in the bottom did improve every so slightly.

Follow up with a high effort congestion placement:

create_placement –congestion –congestion_effort high

legalize_placement

Many of the hot edges have disappeared, but the hotspot in the middle is still there, although lighter overall.

11. Follow up with a global route congestion map. Compare this with the results seen in the placement congestion map. You should see that congestion is better in the GR map. That is due to the nature of the GR that it can route around congested areas.

Task 3. Timing

It seems that congestion is more or less under control, although every crossing with the power grid shows congested edges. It is difficult to judge right now whether this is going to cause unsolvable problems at the routing stage.

You have to consider that place_opt uses even more efficient congestion algorithms, and the timing optimization and buffering can change things a bit.

1. Before going any further, analyze the timing of the placed design.

Question 9. What do you conclude from the reports?

....................................................................................................

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Lab 2

2. To see whether the timing can be improved by better placement, run the following command. This will enable the timing-driven placement:

create_placement –timing_driven –congestion \ –congestion_effort high

legalize_placement

3. Generate another timing report.

Question 10. Did the situation improve?

....................................................................................................

There are a number of things that you could still do to improve congestion, but for now, we will turn the design over to placement, and see how good the algorithms really perform.

Task 4. Perform Placement and Optimization

1. Close and discard the current “explore” cell:

close_mw_cel

2. Copy and open a working design cell to perform the placement and optimization.

copy_mw_cel -from ORCA_TOP -to place_opt

open_mw_cel place_opt

3. Apply the provided script to add the physical design constraints you found during the previous tasks:

source –e –v scripts/physical_constraints.tcl

4. Before running place_opt, you need to make sure that scan information has been annotated on the design. Execute the following command:

report_scan_chain

If you don’t see anything, this means that no scan chain information was loaded.


Lab 2

5. Load the SCANDEF file:

read_def ../ref/design_data/ORCA_TOP.scandef

v report_scan_chain

You should see scan chains now! This information will be used during place_opt to optimize the scan chain wiring.

6. Report the settings for high fanout synthesis:

report_ahfs_options

7. Based on the above, and knowing the defaults (see man-page) have a look at which nets are candidates for high fanout synthesis:

all_high_fanout -nets -threshold 100

As you can see, all the reset nets (3) and the scan_en net will be buffered. The clock nets will not be buffered by place_opt.

8. Based on your observations earlier, perform a placement and optimization run while optimizing :

place_opt -optimize_dft -congestion

You may observe the output of place_opt to get an idea of the optimizations that occur, or you may take a 5-10 minute break…

9. Save the current design as “placed”.

save_mw_cel -as placed


Lab 2

Question 11. What is the standard cell utilization as reported by the chip summary in the log?

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Question 12. Is there a congestion hot spot that would make it difficult for the final routing?

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Question 13. Has the design met setup timing?

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10. Run the following command to have a look at your high fanout nets:

report_buffer_tree_qor -from [all_high_fanout -nets \ -threshold 100 -through_buf_inv]

You can see that the reset nets and scan_en have been buffered.

11. Perform an incremental area recovery:

set_max_area 0

set physopt_area_critical_range 0.1

psynopt -area_recovery

Note: Any area recovery will lower the utilization of the standard cells and may help lower the congestion.

Question 14. What is the design utilization after the area recovery run?

....................................................................................................


Lab 2

Task 5. Incremental Dynamic Power Optimization

The goal of this task is to show the flow and the user interface of the integrated Power Compiler. Instead of using the recommended flow where SAIF is required, you are provided with statistical inputs for the design.

1. Enable dynamic power optimization (disabled by default):

report_power_options

set_power_options -dynamic true

report_power_options

2. Set the toggle rates for the design:

source scripts/inputs_toggle_rate.tcl

Note: Not using SAIF prevents Power Compiler from achieving a realistic power reduction.

3. Report and record the current dynamic power dissipation:

report_power

Cell Internal Power

Net Switching Power

Total Dynamic Power

You can also see the power using “report_constraint”.

4. Perform incremental power optimization and generate a power report for comparison:

psynopt -power

report_power

The power reduction is very small since this is an incremental optimization and is not based on SAIF data. Enabling power optimization during placement and optimization (place_opt) would show a bigger reduction. Power optimization during placement was skipped due to lab time.


Lab 2

If you wish though, you can start a power optimization using the full place_opt flow, and look at the results in the morning! Start with a clean design, and make sure you set the following options:

set_power_options –dynamic true \

-low_power_placement true

place_opt –congestion –optimize_dft -power

5. Exit IC Compiler.

Congratulations! You have completed the placement and power optimization lab.


Answers / Solutions Lab 2

Answers / Solutions

Question 1. Is the clock port specification complete?

The clock ports have a defined driving cell, and a capacitive loading is attached as well. The maximum transition on the clock seems a little high (2 ns), but this may be the way it was intended.

Question 2. What type of a port is SD_DDR_CLK defined on?

SD_DDR_CLK is a generated clock, defined on the output port sd_CK. Sd_CK is listed in the report_clock report, with :report_port –v sd_CK” you can find out about the direction of the port.

Question 3. Does the design meet setup timing? Should you worry?

For the normal paths, yes. There is a path starting at scan_en that has a very large violation though. Although this path will be taken care of by High Fanout Synthesis during place_opt, a big violation like this will throw off any timing-driven placement. Best to hide the violation during the exploration phase.

Question 4. How many soft placement blockages exist in this design?

There are no soft placement blockages reported by the check_physical_constraints command.

Question 5. Does the floorplan contain narrow placement areas?

Yes, many, scattered all over the design.

Question 6. What is the design utilization reported after the “Narrow Placement Area” messages?

Close to 130%!! Placement will not be possible with utilization that high.

Question 7. What may be the cause of the high utilization?

The high utilization is caused by the fact that placement is not occurring under the power straps. Run the command report_pnet_options and you will see that no placement was allowed under METAL2, METAL3 and METAL4. It will not be possible to place the design this way. A complete power net keepout is only recommended if you have a lot of room in your floorplan. This is not the case


Lab 2 Answers / Solutions

here. Issue the following commands to allow cells to “slide” in under the power nets if no shorts are caused:

set_pnet_options -none {METAL2 METAL3 METAL4}

set_pnet_options -partial {METAL2 METAL3 METAL4}

report_pnet_options

Question 8. What is the easiest solution to prevent congestion in the narrow channels for this floorplan?

You can control the congestion in the narrow channels by using placement keepouts. The easiest way is to use placement blockage variables to define soft and hard keepouts near the macros.

Question 9. What do you conclude from the reports?

The timing violations are pretty severe in some cases, about 15-20% of the overall path delay. We paid much attention to congestion, but not much to timing.

Question 10. Did the situation improve?

The situation improved somewhat. The timing is now better, but the congestion has degraded again slightly.

Question 11. What is the standard cell utilization as reported by the chip summary in the log?

Around 83%.

Question 12. Is there a congestion hot spot that would make it difficult for the final routing?

Not really, there are similar congestion patterns as found earlier though (make sure you are looking at a global route congestion map).

Question 13. Has the design met setup timing?

There should be no violations at all.

Question 14. What is the design utilization after the area recovery run?

Around 82%. A reduction of almost 1%!


ICC1 200703 LG 02 Placement

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