IC Fabrication - An Introduction
-
Upload
deepti-chandrasekharan -
Category
Documents
-
view
251 -
download
24
Transcript of IC Fabrication - An Introduction
-
7/29/2019 IC Fabrication - An Introduction
1/144
Theory and Fabrication of Integrated
CircuitsWhere students create integrated circuits from scratch
-
7/29/2019 IC Fabrication - An Introduction
2/144
Thermal Oxidation
Photolithography
Etching
Dopant Diffusion
Metal Evaporation
Electrical Testing
-
7/29/2019 IC Fabrication - An Introduction
3/144
Thermal OxidationSilicon is the dominant semiconductor used in integrated circuit processing,
in large part due to its ability to form a robust (tough) native oxide.
This oxide is used for multiple purposes in the fabrication of ICs:
Diffusion barrier for selectively doping (adding impurities to) silicon
Dielectric (insulator) for MOS devices
Passivation and protection of the silicon surface
Of particular importance in semiconductor processing is cleanliness. Foroxidation, cleanliness must be targeted to the molecular level. Aspecialized process called the RCA Clean is implemented beforeoxidation to remove
organic contaminants (oils)
trace metals
alkali ions (sodium).
-
7/29/2019 IC Fabrication - An Introduction
4/144
Thermal Oxidation
After cleaning with the RCA clean, silicon wafersare placed into a high temperature furnace(900C < T < 1200C) in the presence ofoxygen or water where the following reactionoccurs:
Si + O2 SiO2
or
Si + 2H2O SiO2 +H2
By controlling temperature and oxidation timeprecisely, oxide thickness can be predicted andcontrolled accurately.
ECE444 students performing anoxidation process in a high
temperature furnace.
-
7/29/2019 IC Fabrication - An Introduction
5/144
Photolithography and
EtchingAfter oxidation, the silicon wafer is completely covered with silicon dioxide. This
oxide will prevent dopants from reaching the underlying silicon wafer.
In order to create integrated circuits, the silicon wafer must be doped withimpurities (boron and phosphorus are the most common) selectively this isaccomplished by removing the oxide in specific areas so the dopants are
allowed to diffuse (movement due to high temperature) into the exposedsilicon.
Selective removal of the oxide is performed using Ultraviolet light (UV) sensitive photoresist (PR) to coat the wafer An alignment/illumination system (mask aligner or stepper) to expose
the PR A mask or reticle with desired circuit pattern that only allows the UV lightto be transmitted in the shape of the circuit pattern
Acid to etch the oxide through openings created in the PR mask byphotolithography
-
7/29/2019 IC Fabrication - An Introduction
6/144
Photolithography and
EtchingPhotolithography is very much like taking a picture:
PR coated wafer = film
Mask aligner or stepper = camera
Mask or reticle = subject of the picture
But photolithography is binary either the film is exposed or notexposed; there are no shades of gray.
-
7/29/2019 IC Fabrication - An Introduction
7/144
Photolithography
Mask or Reticle:
The mask is tranparent plate of fused silica(high purity glass) with an opticallyopaque film applied to one surface. Adetailed layout of the circuit is createdusing computer aided design (CAD)software, and this pattern is etched intothe opaque film. The etched film on themask creates the hard copy of the circuitpattern.
The mask/reticle is then used to transmitUV light in the pattern of the circuit.
CAD full adder layou
Isometric detail view of the ECE444CAD layout
-
7/29/2019 IC Fabrication - An Introduction
8/144
Photolithography
PR Application:
Photoresist (an organic polymer sensitive toUV light and resistant to attack by acids)is applied to the oxidized wafer using aphotoresist spinner. This process usescentrifugal force from high speed rotationof the wafer.
The PR is applied as a small puddle in the
center of the wafer. When the waferspins, the PR spreads out over the waferdue to centrifugal force. After spinning, auniform layer of PR remains on thesurface.
ECE444 student dispensing photoresistonto an oxidized silicon wafer. Note theyellow cast to the picture shortwavelength light (green, blue, violet, andultraviolet) exposes PR, so it has beenfiltered out of the room light, leaving onlyred, orange, and yellow to see with!
-
7/29/2019 IC Fabrication - An Introduction
9/144
Photolithography
Alignment and Exposure:
The PR coated wafer is placed into asystem (mask aligner or stepper)
which allows the mask to be aligned
to the wafer. After alignment, thesystem opens a shutter to allow UVlight to illuminate the PR through themask for a controlled period of time.
The PR which is exposed to UV lightundergoes a photochemical reactionto make the PR more acidic (indenecarboxylic acid is produced).
ECE444 student loading PR coated wafer into anUltratech 1000WF Step and Repeat Projection
Alignment system (also known as a stepper).
-
7/29/2019 IC Fabrication - An Introduction
10/144
Photolithography
Development:
After the wafer is exposed to UV light through the mask, the acidic regions ofPR are removed by dipping the wafer into an alkaline (base) developingsolution. The acidic PR reacts chemically with the basic developer to
form water soluble salts that dissolve in the developer.
At this point the mask image can be seen in the PR (remember that the PRwas illuminated with UV light through the mask, so only light in the shapeof the circuit reaches the PR the rest of the PR did not change!).
Note: the image from the mask has only been transferred to the PR. ThePR will be used as a mask for etching the underlying oxide in an acidbath.
-
7/29/2019 IC Fabrication - An Introduction
11/144
Etching
The previous steps produced a pattern in the PRlayer coating the oxidized wafer. This patternedPR will now be used for selectively etching theoxide areas that are exposed.
The patterned, PR coated wafer is placed into a
hydrofluoric (HF) acid bath to remove theexposed oxide. HF will react chemically withthe oxide to form water soluble products thatdissolve in the water used to dilute the acid.
When the oxide is etched away, the silicon beneath
the oxide can be seen. Fortunately, HF doesnot react with silicon (this is ideal the HF isselective with regards to the two materialspresent on the wafer).
The PR is then removed, leaving a permanent
pattern etched into the oxide.
Oxidized and etched 100mm diameter
wafer fabricated in the ECE444laboratory. Mask level 1 used forphotolithography. Purple areas aresilicon dioxide, silver areas are exposedsilicon.
-
7/29/2019 IC Fabrication - An Introduction
12/144
Dopant Diffusion
physicsSilicon is a column IV element this means there are four electrons in the
outermost shell of the atom. It is these electrons that are used whenbonding to other atoms. In a wafer, each silicon atom bonds to four othersilicon atoms (each Si-Si bond shares one electron). So in an intrinsic(pure) silicon wafer, all the electrons in the outer shell are part of a bondthey are stuck between the bonded silicon atoms.
In order for current to flow in a material there must be loose electrons. But allthe electrons in silicon are working at holding the atoms together, whichmeans it is not a good conductor of current.
So what can be done to allow the silicon to conduct current more easily? Freecarriers of current must be added. The goal is to find an element about the
same size as a silicon atom so that it fits together well with the silicon, butwith more electrons in its outer shell.
-
7/29/2019 IC Fabrication - An Introduction
13/144
Dopant Diffusion
physicsIn the periodic table, the closer elements are to each other, the more similar
they are. So the best candidates would come from column V (which havefive outer shell electrons). The element closest to silicon in column V isphosphorus.
If phosphorus is inserted into the silicon wafer in a certain way, it will take theplace of a silicon atom and bond with its four neighbor silicon atoms. Afterbonding, phosphorus has an electron left over that is not bonded to a siliconatom. It turns out this extra electron is not strongly held by the phosphorusatom any more, so it can be removed easily. This electron then becomes acarrier for current it is free to move around the wafer. So the conductivityof the silicon wafer increases. This type of silicon doped with phosphorusis called an n-type semiconductor.
-
7/29/2019 IC Fabrication - An Introduction
14/144
Dopant Diffusion
physicsExtending this idea of inserting an element with a different number of valence
electrons, a column III element (such as boron) could be added to thesilicon wafer. In this case, the boron will try to bond with four siliconatoms, but it only has three electrons to bond with. This means there isan incomplete bond with one of the silicon atomsa hole where anelectron would normally be. This hole behaves much like an electronand can move around the wafer, but with an opposite charge (+). So a
different type of current carrier is present in the wafer that increases thewafers conductivity. This type of silicon doped with boron is called ap-type semiconductor.
By adding impurities to silicon, the conductivity increases. This conductivitycan be adjusted by the amount of impurity added.
-
7/29/2019 IC Fabrication - An Introduction
15/144
Dopant Diffusion
physicsNow for the interesting part - when n-type silicon comes into contact with p-type
silicon. A built-in potential (voltage) develops that must be overcome beforecurrent can flow from the n-type to p-type regions.
Think of carriers as being able to only move across a flat surface ordown aslope. The built in potential is a hill that the carrier can not go up. So in
order for the carrier to keep moving, the low part must be pushed up to belevel or higher than the top of the hill. In the case of an n-type / p-typejunction, the energy to push up the low side comes in the form of a voltageapplied to the wafer. The voltage is used to push up the ground on the low
side of the hill before current flows from n-type to p-type regions.
But if the voltage is reversed, the energy is used to push the low side lowerwhile keeping the high side at the same height! That means the carrierprobably wont ever make it up the higher hill, so it is stuck (no current
flows).
-
7/29/2019 IC Fabrication - An Introduction
16/144
Dopant Diffusion
physicsSo when n-type silicon is brought into contact with p-type silicon (apn junction),
current can flow in only one direction. This is the fundamentalsemiconductor device a pn junction diode a one way switch for current.
The devices used in integrated circuits are specialized combinations of pnjunctions. The junctions are formed by the addition of impurity atoms fromcolumns III and V of the periodic table into the silicon wafer throughdiffusion.
-
7/29/2019 IC Fabrication - An Introduction
17/144
Dopant Diffusion -
PredepThe goal of the dopant predeposition diffusion is to
move dopant atoms from a source to the wafer,and then allow the dopants to diffuse into thewafer.
The source of dopant can be in several forms solid(boron nitride and phosphorus oxide ceramicdiscs), liquid (boron tribromide and POCl3), or gas(diborane or phosphine).
In order for the dopants to move into the silicon, theymust be given energy, usually in the form of heat.In order for the diffusion to occur in a reasonabletime, the temperature must be very high (900C
-
7/29/2019 IC Fabrication - An Introduction
18/144
Dopant Diffusion - Drive
After the predeposition diffusion the dopants are situatedclose to the surface of the wafer. However, they mustdiffuse even farther to lower the overall concentrationin order for some of the devices to work properly.
The first diffusion (predeposition) introduces dopants intothe wafer.
The second diffusion (drive) redistributes the dopants andallow the dopants to diffuse into the wafer moredeeply (up to ~3 micrometers)
In addition, oxygen and water vapor are introduced duringthe drive diffusion to grow a new oxide over the areaswhich were exposed to bare silicon during thephotolithography process. This new oxide can bepatterned again so that other selective diffusion
processes can be performed to create other types ofdevices.
100mm diameter wafer fabricated in
the ECE444 laboratory followingboron predeposition, boron drive,and re-oxidation.
-
7/29/2019 IC Fabrication - An Introduction
19/144
Repeat the process
At this point, the process of oxidation-photolithography-etching-diffusion canbe repeated to produce the various types of electronic devices required for acircuit.
Some modern processes may require more than 20 iterations of this
sequence!Oxidation
Photo-lithography
Etching
Diffusion(Ion
Implantatio
n)
The following slides show the rest of theprocesses performed in the ECE444 lab.
-
7/29/2019 IC Fabrication - An Introduction
20/144
ECE444 Process
Phosphorus Diffusion
Photolithography Mask 2
Etch
Phosphorus Predeposition
Gate Oxide Formation
Photolithography Mask 3
Etch
Gate oxidation
-
7/29/2019 IC Fabrication - An Introduction
21/144
ECE444 Process
Electrical contact vias (holes) to silicon
Photolithography Mask 4
Etch
Metal definition
Photolithography Mask 5
-
7/29/2019 IC Fabrication - An Introduction
22/144
Metallization
After all diffusion and oxidation steps arecompleted, metal is deposited ontothe surface of the wafer. This metal isused to wire the devices fabricated in
the silicon together.
The wafers are put into a large chamberand the air is pumped out of thesystem. A piece of aluminum locatedon a tungsten boat in the system is
heated to high temperature, causing
the aluminum to melt and evaporate.The evaporated aluminum will solidifyinto a thin film when it touches thesilicon wafer.
Thermal evaporation vacuum system usedin the ECE444 laboratory. This tool wasdesigned and built for an independent
study project.
-
7/29/2019 IC Fabrication - An Introduction
23/144
Metallization
After metallization, the wafer is completely covered by the aluminum.
It must be patterned and etched to form the actual wires connecting
individual devices into a circuit.
Wafer after aluminum evaporation
-
7/29/2019 IC Fabrication - An Introduction
24/144
Completed wafer
Time to see if it works
Steps to create ECE444 wafer:
1. Initial oxidation2. Photolithography Mask 13. Oxide etch4. Boron predep5. Boron drive and re-
oxidation6. Photolithography Mask 2
7. Oxide etch8. Phosphorus predeposition9. Photolithography Mask 310.Gate oxidation11.Photolithography Mask 412.Etch13.Photolithography Mask 514.Metal evaporation15.Metal definition
-
7/29/2019 IC Fabrication - An Introduction
25/144
Testing
After completion of the wafer, it must betested to verify operation.
The devices fabricated are extremelysmall (some dimensions are as smalla 1micrometer!), so specialized
probes are used to make electricalcontact.
Once contact is made, several differentinstruments are used to measureelectrical performance.
ECE444 Probe station
Example of electrical data from a devicefabricated in the ECE444 laboratory
-
7/29/2019 IC Fabrication - An Introduction
26/144
Silicon Manufacturing
-
7/29/2019 IC Fabrication - An Introduction
27/144
HISTORY 19th Century - Solid-State
Rectifiers
1907 - Application of CrystalDetector in Radio Sets
1947 - BJT Constructed byBardeen and Brattain
1959 Integrated Circuit
-
7/29/2019 IC Fabrication - An Introduction
28/144
SemiconductorManufacturing Process
-
7/29/2019 IC Fabrication - An Introduction
29/144
SemiconductorManufacturing ProcessFundamental Processing Steps
1.Silicon Manufacturinga) Czochralski method.b) Wafer Manufacturingc) Crystal structure
2.Photolithographya) Photoresists
b) Photomask andReticles
c) Patterning
-
7/29/2019 IC Fabrication - An Introduction
30/144
3.Oxide Growth & Removala) Oxide Growth & Depositionb) Oxide Removalc) Other effectsd) Local Oxidation
4. Diffusion & Ion Implantationa) Diffusion
b) Other effectsc) Ion Implantation
SemiconductorManufacturing Process(cont)
-
7/29/2019 IC Fabrication - An Introduction
31/144
Silicon ManufacturingCrystal Growth and WaferManufacturing
-
7/29/2019 IC Fabrication - An Introduction
32/144
FABRICATINGSILICON Quartz, or Silica, Consists of Silicon
Dioxide
Sand Contains Many Tiny Grains ofQuartz
Silicon Can be Artificially Produced by
Combining Silica and Carbon inElectric Furnice
Gives Polycrystalline Silicon (multitude
of crystals)
-
7/29/2019 IC Fabrication - An Introduction
33/144
CRYSTAL GROWTH Czochralski Process is
a Technique in Making
Single-Crystal Silicon A Solid Seed Crystal is
Rotated and SlowlyExtracted from a Pool
of Molten Si Requires Careful
Control to GiveCrystals Desired Purity
and Dimensions
-
7/29/2019 IC Fabrication - An Introduction
34/144
CYLINDER OFMONOCRYSTALLINE
The Silicon Cylinder isKnown as an Ingot
Typical Ingot is About 1 or2 Meters in Length
Can be Sliced intoHundreds of SmallerCircular Pieces Called
Wafers Each Wafer Yields
Hundreds or Thousands ofIntegrated Circuits
-
7/29/2019 IC Fabrication - An Introduction
35/144
WAFER MANUFACTURING
The Silicon Crystal is Sliced by Using a Diamond-Tipped Saw
into Thin Wafers
Sorted by Thickness
Damaged Wafers Removed During Lapping
Etch Wafers in Chemical to Remove any Remaining Crystal
Damage
Polishing Smoothes Uneven Surface Left by Sawing Process
-
7/29/2019 IC Fabrication - An Introduction
36/144
THE CRYSTALSTRUCTURE OF SILICON
A Unit Cell Has 18Silicons Atoms
Weak Bonding AlongCleavage Planes
Wafer Splits into 4 or6 Wedge-ShapedFragments
Miller Indices is Usedto Assign to EachPossible PlanePassing Through theCrystal Lattice
-
7/29/2019 IC Fabrication - An Introduction
37/144
Silicon ManufacturingPhotolithography
-
7/29/2019 IC Fabrication - An Introduction
38/144
Photolithography
Photolithographyis a technique thatis used to definethe shape ofmicro-machined
structures on awafer.
-
7/29/2019 IC Fabrication - An Introduction
39/144
PhotolithographyPhotoresistThe first step in the photolithography process is todevelop a mask, which will be typically be a
chromium pattern on a glass plate.
Next, the wafer is then coated with a polymerwhich is sensitive to ultraviolet light called a
photoresist.
Afterward, the photoresist is then developed whichtransfers the pattern on the mask to thehotoresist la er.
-
7/29/2019 IC Fabrication - An Introduction
40/144
PhotolithographyPhotoresistThere are two basic types of Photoresists Positive and Negative.
Positive resists.
Positive resists decomposes ultraviolet light. The resist isexposed with UV light wherever the underlying material is to beremoved. In these resists, exposure to the UV light changes thechemical structure of the resist so that it becomes more soluble in
the developer. The exposed resist is then washed away by thedeveloper solution, leaving windows of the bare underlyingmaterial. The mask, therefore, contains an exact copy of thepattern which is to remain on the wafer.
-
7/29/2019 IC Fabrication - An Introduction
41/144
PhotolithographyPhotoresistNegative resists
Exposure to the UV light causes the negative resist to become
polymerized, and more difficult to dissolve. Therefore, thenegative resist remains on the surface wherever it is exposed, andthe developer solution removes only the unexposed portions.Masks used for negative photoresists, therefore, contain theinverse (or photographic "negative") of the pattern to be
transferred.
-
7/29/2019 IC Fabrication - An Introduction
42/144
PhotolithographyModel
Figure 1a shows a thin filmof some material (eg,silicon dioxide) on a
substrate of some othermaterial (eg, a siliconwafer).
Photoresist layer (Figure 1b
)
Ultraviolet light is thenshone through the maskonto the photoresist (figure1c).
-
7/29/2019 IC Fabrication - An Introduction
43/144
PhotolithographyModel (cont)
The photoresist is thendeveloped which transfersthe pattern on the mask to
the photoresist layer (figure1d).
A chemical (or some othermethod) is then used toremove the oxide where it isexposed through theopenings in the resist(figure 1e).
Finally the resist is removed
leaving the patterned oxidefi ure 1f .
-
7/29/2019 IC Fabrication - An Introduction
44/144
PhotolithographyPhotomasks andReticles
PhotomaskThis is a square glass plate with a patterned emulsion of metal filmon one side. The mask is aligned with the wafer, so that the patterncan be transferred onto the wafer surface. Each mask after the firstone must be aligned to the previous pattern.
-
7/29/2019 IC Fabrication - An Introduction
45/144
PhotolithographyPhotomasks andReticles
When a image on the photomask is projected several time side by side ontothe wafer, this is known as stepping and the photomask is called a reticle.
An common reticle is the 5X
The patterns on the 5X reticle are reduced 5 times whenprojected onto the wafer. This means the dies on the
photomask are 5 times larger than they are on the finalproduct. There are other kinds of reduction reticles (2X, 4X,and 10X), but the 5X is the most commonly used. Reductionreticles are used on a variety of steppers, the most commonbeing ASM, Canon, Nikon, and GCA.
-
7/29/2019 IC Fabrication - An Introduction
46/144
PhotolithographyPhotomasks andReticles
Examples of 5X Reticles:
-
7/29/2019 IC Fabrication - An Introduction
47/144
PhotolithographyPhotomasks andReticles
Once the mask has been accurately aligned with the pattern on thewafer's surface, the photoresist is exposed through the pattern on themask with a high intensity ultraviolet light. There are three primaryexposure methods: contact, proximity, and projection.
-
7/29/2019 IC Fabrication - An Introduction
48/144
PhotolithographyPatterningThe last stage of Photolithography is a process called ashing. This processhas the exposed wafers sprayed with a mixture of organic solvents thatdissolves portions of the photoresist .
Conventional methods of ashing require an oxygen-plasma ash, often incombination with halogen gases, to penetrate the crust and remove thephotoresist. Usually, the plasma ashing process also requires a follow-upcleaning with wet-chemicals and acids to remove the residues and non-volatile contaminants that remain after ashing. Despite this treatment, it is
not unusual to repeat the "ash plus wet-clean" cycle in order to completelyremove all photoresist and residues.
-
7/29/2019 IC Fabrication - An Introduction
49/144
Silicon ManufacturingOxidation of Silicon
-
7/29/2019 IC Fabrication - An Introduction
50/144
SiO2 growth is a key process step inmanufacturing all Si devices
- Thick ( 1m) oxides are used for fieldoxides (isolate devices from oneanother )
- Thin gate oxides (100 ) control MOS
devices - Sacrificial layers are grown andremoved to clean up surfaces
The stability and ease of formation of SiO2 wasone of the reasons that Si replaced Ge as thesemiconductor of choice.
Th i l t th d f d i
-
7/29/2019 IC Fabrication - An Introduction
51/144
The simplest method of producing
an oxide layer consists of heating a
silicon wafer in an oxidizing
atmosphere.
-
7/29/2019 IC Fabrication - An Introduction
52/144
Dry oxide -Pure dry oxygen is employedDisadvantage
- Dry oxide grows very slowly.Advantage
- Oxide layers are very uniform.
- Relatively few defects exist at the oxide-silicon
interface (These defects interfere with the properoperation of semiconductor devices)
- It has especially low surface state charges and thusmake ideal dielectrics for MOS transistors.
-
7/29/2019 IC Fabrication - An Introduction
53/144
Wet oxide - In the same way as dry oxides, butsteam is injected
Disadvantage- Hydrogen atoms liberated by the decomposition
of the water molecules produce imperfectionsthat may degrade the oxide quality.
Advantage- Wet oxide grows fast.
- Useful to grow a thick layer of field oxide
-
7/29/2019 IC Fabrication - An Introduction
54/144
Deposited Oxides
Oxide is frequently employed as an insulatorbetween two layers of metalization. In suchcases, some form ofdeposited oxide must beused rather than the grown oxides.
Deposited oxides can be produced by variousreactions between gaseous silicon compoundsand gaseous oxidizers. Deposited oxides tendto possess low densities and large numbers of
defect sites. Not suitable for use as gatedielectrics for MOS transistors but stillacceptable for use as insulating layers betweenmultiple conductor layers, or as protective
overcoats.
-
7/29/2019 IC Fabrication - An Introduction
55/144
Key Variables in
Oxidation
Temperature
- reaction rate
- solid state diffusion
Oxidizing species
- wet oxidation is much faster than dry oxidation
Surface cleanliness- metallic contamination can catalyze reaction
- quality of oxide grown (interface states)
-
7/29/2019 IC Fabrication - An Introduction
56/144
Etching
Etching is the process where unwanted areas of filmsare removed by either dissolving them in a wet
chemical solution (Wet Etching) or by reacting themwith gases in a plasma to form volatile products (DryEtching).
Resist protects areas which are to remain. In somecases a hard mask, usually patterned layers of SiO2 orSi3N4, are used when the etch selectivity to photoresistis low or the etching environment causes resist to
delaminate.
-
7/29/2019 IC Fabrication - An Introduction
57/144
-
7/29/2019 IC Fabrication - An Introduction
58/144
Wet ChemicalEtching Wet etches:
- are in general isotropic
(not used to etch features less than 3m)- achieve high selectivities for most filmcombinations
- capable of high throughputs- use comparably cheap equipment- can have resist adhesion problems
- can etch just about anything
-
7/29/2019 IC Fabrication - An Introduction
59/144
Example Wet Processes For SiO2 etching
- HF + NH4F+H20 (buffered oxide etch or BOE) For Si3N4
- Hot phosphoric acid: H3PO4 at 180 C- need to use oxide hard mask
Silicon- Nitric, HF, acetic acids
- HNO3 + HF + CH3COOH + H2O Aluminum
- Acetic, nitric, phosphoric acids at 35-45 C- CH3COOH+HNO3+H3PO4
-
7/29/2019 IC Fabrication - An Introduction
60/144
What is a plasma(glow discharge)? A plasma is a partially ionized gas made up of equal
parts positively and negatively charged particles.
Plasmas are generated by flowing gases through anelectric or magnetic field.
These fields remove electrons from some of the gasmolecules. The liberated electrons are accelerated,
or energized, by the fields. The energetic electrons slam into other gasmolecules, liberating more electrons, which areaccelerated and liberate more electrons from gasmolecules, thus sustaining the plasma.
-
7/29/2019 IC Fabrication - An Introduction
61/144
Dry or Plasma Etching
-
7/29/2019 IC Fabrication - An Introduction
62/144
Dry or Plasma Etching
-
7/29/2019 IC Fabrication - An Introduction
63/144
Dry or Plasma EtchingCombination of chemical and physical
etching Reactive Ion Etching (RIE)Directional etching due to ion assistance.
In RIE processes the wafers sit on the poweredelectrode. This placement sets up a negative bias
on the wafer which accelerates positively charge ionstoward the surface. These ions enhance the
chemical etching mechanisms and allowanisotropic etching.
Wet etches are simpler, but dry etches providebetter line width control since it is anisotropic.
-
7/29/2019 IC Fabrication - An Introduction
64/144
Other Effects of OxideGrowth and Removal Oxide Step
- The differences in oxide thickness and in thedepths of the silicon surfaces combine toproduce a characteristic surface discontinuity
The growth of a thermal oxide affects the dopinglevels in the underlying silicon
The doping of silicon affects the rate of oxidegrowth
-
7/29/2019 IC Fabrication - An Introduction
65/144
Local Oxidation ofSilicon (LOCOS) LOCOS: localized oxidation of silicon using
silicon nitride as a mask against thermaloxidation.
A technique called local oxidation of silicon
(LOCOS) allows the selective growth thickoxide layers
CMOS and BiCMOS processes employLOCOS to grow a thick field oxide over
electrically inactive regions of the wafer
-
7/29/2019 IC Fabrication - An Introduction
66/144
Silicon ManufacturingDiffusion and IonImplantation
WN J ti F b i ti
-
7/29/2019 IC Fabrication - An Introduction
67/144
WN-Junction Fabrication
(Earliest method)
Process: Opposite polarity doping atoms are added to
molten silicon during the Czochralski process tocreate in-grown junctions in the ingot.
Repeated counterdopings can produce multiple
junctions within the crystal.
Disadvantages Inability to produce differently doped areas in
different parts of the wafer.
The thickness and planarity of grown junctions aredifficult to control. Repeated counterdopings degrade the electrical
properties of the silicon.
-
7/29/2019 IC Fabrication - An Introduction
68/144
The Planar Process Advantages:
The planar process does not require multiplecounterdopings of the silicon ingot.
This process allows more precise control ofjunction depths and dopant distributions.
-
7/29/2019 IC Fabrication - An Introduction
69/144
Methods of planarprocess Diffusion
A uniformly doped ingot issliced into wafers.
An oxide film is thengrown on the wafers. The film is patterned and
etched usingphotolithography exposingspecific sections of the
silicon. The wafers are then spunwith an opposite polaritydoping source adheringonly to the exposed areas.
The wafers are then heated
in a furnace (800-1250deg.C) to drive the doping
Ion Implantation A particle accelerator is
used to accelerate a
doping atom so that it canpenetrate a silicon crystalto a depth of severalmicrons
Lattice damageto the
crystal is then repaired byheating the wafer at amoderate temperature for afew minutes. This processis called annealing.
-
7/29/2019 IC Fabrication - An Introduction
70/144
Diffusion Process IonImplantation
-
7/29/2019 IC Fabrication - An Introduction
71/144
Comparison of Diffusionand Ion Implantation Diffusion is a cheaper and more simplistic
method, but can only be performed from thesurface of the wafers. Dopants also diffuseunevenly, and interact with each other
altering the diffusion rate.
Ion implantation is more expensive andcomplex. It does not require hightemperatures and also allows for greater
control of dopant concentration and profile. Itis an anisotropic process and therefore doesnot spread the dopant implant as much asdiffusion. This aids in the manufacture ofself-aligned structures which greatly improve
the performance of MOS transistors.
-
7/29/2019 IC Fabrication - An Introduction
72/144
ReferencesThe Art of Analog Layout by Alan Hastings 2001 Prentice-Hall
Semiconductor Devices by Mauro Zambuto 1989 McGraw-Hill
Semiconductor Manufacturing Technology by Quirk and Serda 2001
Prentice-Hall
-
7/29/2019 IC Fabrication - An Introduction
73/144
Introduction to theSemiconductor Industry
-
7/29/2019 IC Fabrication - An Introduction
74/144
ObjectivesAfter studying the material in this chapter, you will be able to:
1. Describe the current economic state and the technicalroots of the semiconductor industry.
2. Explain what is an integrated circuit (IC) and list the fivecircuit integration eras.
3. Describe a wafer, including how it is layered and describethe essential aspects of the five stages of waferfabrication.
4. State and discuss the three major trends associated withimprovement in wafer fabrication.
5. Explain what is a critical dimension (CD) and how Mooreslaw predicts future wafer fabrication improvement.
6. Describe the different eras of electronics since theinvention of the transistor up to modern wafer fabrication.
7. Discuss different career paths in the semiconductor
industry.
-
7/29/2019 IC Fabrication - An Introduction
75/144
Microprocessor Chips
Photo courtesy ofAdvanced Micro Devices
Photo courtesy ofIntel Corporation
Photo 1.1
Development of an
-
7/29/2019 IC Fabrication - An Introduction
76/144
Development of an
Industry Industry Roots Vacuum Tubes
Radio Communications
Mechanical Tabulators
Inventors
Disadvantages
The Solid State
Solid State Physics
The First Transistor
Benefits
-
7/29/2019 IC Fabrication - An Introduction
77/144
Vacuum Tubes
Photo 1.2
The Semiconductor
-
7/29/2019 IC Fabrication - An Introduction
78/144
Industry
PRODUCTAPPLICATIONS
INFRASTRUCTURE
Consumers: Computers Automotive
Aerospace Medical other industries
Customer Service
Original EquipmentManufacturers
Printed Circuit Board Industry
Industry Standards(SIA, SEMI, NIST, etc.)
Production Tools
UtilitiesMaterials & Chemicals
Metrology Tools
Analytical Laboratories
Technical Workforce
Colleges & Universities
Chip
Manufacturer
Figure 1.1
The First Transistor from
-
7/29/2019 IC Fabrication - An Introduction
79/144
The First Transistor from
Bell Labs
Photo courtesy of Lucent Technologies Bell Labs Innovations
Photo 1.3
The First Planar
-
7/29/2019 IC Fabrication - An Introduction
80/144
The First Planar
Transistor
Figure 1.2
-
7/29/2019 IC Fabrication - An Introduction
81/144
Circuit Integration
Integrated Circuits (IC)
Microchips, chips
Inventors
Benefits of ICs
Integration Eras
From SSI to ULSI
1960 - 2000
Jack Kilbys First
-
7/29/2019 IC Fabrication - An Introduction
82/144
Jack Kilby s First
Integrated Circuit
Photo courtesy of Texas Instruments, Inc.
Photo 1.4
Top View of Wafer with
-
7/29/2019 IC Fabrication - An Introduction
83/144
Top View of Wafer with
ChipsA single integratedcircuit, also known as adie, chip, andmicrochip
Figure 1.3
Circuit Integration of
-
7/29/2019 IC Fabrication - An Introduction
84/144
Circuit IntegrationSemiconductor
Industry Time Period
Number ofComponents per
Chip
No integration (discrete components) Prior to 1960 1
Small scale integration (SSI) Early 1960s 2 to 50
Medium scale integration (MSI) 1960s to Early 1970s 50 to 5,000
Large scale integration (LSI)Early 1970s to Late
1970s5,000 to 100,000
Very large scale integration (VLSI)Late 1970s to Late
1980s100,000 to 1,000,000
Ultra large scale integration (ULSI) 1990s to present > 1,000,000
Circuit Integration of
Semiconductors
Table 1.1
-
7/29/2019 IC Fabrication - An Introduction
85/144
ULSI Chip
Photo courtesy of Intel Corporation, Pentium III
Photo 1.5
-
7/29/2019 IC Fabrication - An Introduction
86/144
IC Fabrication Silicon
Wafer Wafer Sizes
Devices and Layers
Wafer Fab Stages of IC Fabrication Wafer preparation
Wafer fabrication
Wafer test/sortAssembly and packaging
Final test
-
7/29/2019 IC Fabrication - An Introduction
87/144
Evolution of Wafer Size
2000
1992
1987
1981
1975
1965
50 mm 100 mm 125 mm 150 mm 200 mm 300 mm
Figure 1.4
Devices and Layers from
-
7/29/2019 IC Fabrication - An Introduction
88/144
Devices and Layers from
a Silicon Chip
Silicon substrate
drain
Silicon substrate
Top protective layer
Metal layer
Insulation layers
Recessed conductivelayer
Conductive layer
Figure 1.5
-
7/29/2019 IC Fabrication - An Introduction
89/144
Stages of IC Fabrication
Wafer Preparationincludes crystal
growing, rounding,slicing and polishing.
Wafer Fabrication
includes cleaning,layering, patterning,etching and doping.
Assembly and Packaging:
The wafer is cutalong scribe lines
to separate each die.
Metal connections
are made and thechip is encapsulated.
Test/Sort includes
probing, testing and
sorting of each die on
the wafer.
Final Test ensures IC
passes electrical and
environmental
testing.
Defective die
1.
2.
3.
Scribe line
A single die
Assembly Packaging
4.
5.
Wafers sliced from ingot
Single crystal silicon
Figure 1.6
Preparation of Siliconf
Polysilicon S d t l
-
7/29/2019 IC Fabrication - An Introduction
90/144
Wafers1. Crystal Growth
2. Single Crystal Ingot
3. Crystal Trimming andDiameter Grind
4. Flat Grinding
5. Wafer Slicing
6. Edge Rounding
7. Lapping
8. Wafer Etching
9. Polishong
10. Wafer Inspection
Slurry
Polishing table
Polishinghead
Polysilicon Seed crystal
Heater
Crucible
(Note: Terms in Figure 1.7 are explained in Chapter 4.)
Figure 1.7
W f F b
-
7/29/2019 IC Fabrication - An Introduction
91/144
Wafer Fab
Photo courtesy of Advanced Micro Devices-Dresden, S. Doering
Photo 1.6
Sample of Microchip
-
7/29/2019 IC Fabrication - An Introduction
92/144
Sample of Microchip
Packaging
Figure 1.8
S i d t T d
-
7/29/2019 IC Fabrication - An Introduction
93/144
Semiconductor Trends
Increase in Chip Performance
Critical Dimension (CD)
Components per Chip
Moores Law Power Consumption
Increase in Chip Reliability
Reduction in Chip Price
C iti l Di i
-
7/29/2019 IC Fabrication - An Introduction
94/144
Critical DimensionCommon IC Features
Contact Hole
Line Width Space
Figure 1.9
Technology Nodes for
-
7/29/2019 IC Fabrication - An Introduction
95/144
1988 1992 1995 1997 1999 2001 2002 2005
CD
(m)1.0 0.5 0.35 0.25 0.18 0.15 0.13 0.10
Technology Nodes for
Device Critical
Dimension (CD)
Table 1.2
Increase in Total
T i t /Chi
-
7/29/2019 IC Fabrication - An Introduction
96/144
Transistors/Chip
1997 1999 2001 2003 2006 20122009
1600
1400
1200
1000
800
600
400
200MicroprocessorTotalTransistorsinM
illions
Year
Redrawn from Semiconductor Industry Association, The NationalTechnology Roadmap for Semiconductors, 1997.
Figure 1.10
Moores Law for
-
7/29/2019 IC Fabrication - An Introduction
97/144
Year
4004
8080
8086
80286
80386
80486
PentiumPentium Pro
100M
10M
1M
100K
10K
1975 1980 1985 1990 1995 2000
500
25
1.0
.1
.01
Used with permission from Proceedings of the IEEE, January, 1998, 1998 IEEE
Moore s Law for
Microprocessors
Figure 1.11
The number of transistors on a chip double every 18 months.
Size Comparison of Earlyd M d
-
7/29/2019 IC Fabrication - An Introduction
98/144
and Modern
Semiconductors
Figure 1.12
1990s Microchip(5~25 million transistors)
1960s Transistor
U.S. coin, 10 cents
Reduction in Chip PowerConsumption per IC
-
7/29/2019 IC Fabrication - An Introduction
99/144
Consumption per IC10
8
6
4
2
0
1997 1999 2001 2003 2006 2009 2012
AveragePowe
rinmicroWatts(1
0-6W
)
Year
Redrawn from Semiconductor Industry Association,National Technology Roadmap, 1997
Figure 1.13
Reliability Improvement
-
7/29/2019 IC Fabrication - An Introduction
100/144
y p
of Chips
1972 1976 1980 1984 1988 1992 1996 2000
Year
700
600
500
400
300
200
100
0
Long-TermFailureRateGoals
inpartsperm
illion(PPM)
Figure 1.14
Price Decrease ofS i d t Chi
-
7/29/2019 IC Fabrication - An Introduction
101/144
Semiconductor Chips
Redrawn from C. Chang & S. Sze, McGraw-Hill, ULSI Technology, (New York: McGraw-Hill, 1996), xxiii.
Figure 1.15
1930 1940 1950 1960 1970 1980 1990 2000Year
104
102
1
10-2
10-4
10-6
10-8
10-10
Relativevalue
Device size=
Price=Bipolar transistor
MSI
LSI
VLSI
ULSI
Standard
tube
Electrontubes
Semiconductor devices
Integrated circuits
Miniature tube
The Electronic Era
-
7/29/2019 IC Fabrication - An Introduction
102/144
The Electronic Era
1950s: Transistor Technology
1960s: Process Technology
1970s: Competition 1980s: Automation
1990s: Volume Production
Start-Up Cost of Wafer
-
7/29/2019 IC Fabrication - An Introduction
103/144
p
Fabs$100,000,000,00
0
$10,000,000,000
$1,000,000,000
$100,000,000
$10,000,000
Cost
1970 1980 1990 2000 2010 2020
Year
Actual CostsProjectedCosts
Used with permission from Proceedings of IEEE, January, 1998 1998 IEEE
Figure 1.16
Career Paths in theSemiconductor Industry
-
7/29/2019 IC Fabrication - An Introduction
104/144
Semiconductor Industry
Manufacturing Technician
Wafer Fab Technician
Maintenance Technician Lab Technician
Yield & Failure Analysis TechnicianEquipment Technician
Equipment Engineer Associate Engineer
Process EngineerProduction Supervisor
Production Manager
Maintenance Supervisor
Fab Manager
Maintenance Manager
Process Technician
Engineering Manager
Production Operator
HS +
AS+
AS
BS
MS
HS
Educatio
n
BSET*
* Bachelor of Science inElectronics Technology
Figure 1.17
u v y uin a Wafer FabMisprocessing
-
7/29/2019 IC Fabrication - An Introduction
105/144
Metallization
Production Bay
Etch
Production Bay
Thin Films
Production Bay
DiffusionProduction Bay
PhotoProduction Bay
Ion ImplantProduction Bay
Production Equipment Inspection
Rework
Inspection
Scrap
ProductionEquipment
Inspection
ProductionEquipmen
t
Inspection
ProductionEquipment
Inspection
ProductionEquipment
Inspection
ProductionEquipment
Wafer Starts
1 2 3 46 7 8 9 10 11
2 13 14 15 16 17 18
9 20 21 22 23 24 25
6 27 28 29 30 31
1
2 3 4 5 6 7 8
9 10 11 12 13 14 15
16 17 18 19 20 21 22
23 24 25 26 27 28 29
30 31
Wafer Outs
Time In Time Out
12
3
6
9
Cycle Timeper Operation
Production Cycle Time = (Date and Time of Wafer Start) - (Date and Time of WaferOut)
Wafer Outs = Wafer Starts - Wafers Scrapped
Operator Efficiency = Theoretical Cycle Time / Actual Cycle Time
Wafer Moves
Figure 1.18
Wafer Fab
-
7/29/2019 IC Fabrication - An Introduction
106/144
Photograph courtesy of Advanced Micro Devices
Photo 1.7
Technician in Wafer Fab
-
7/29/2019 IC Fabrication - An Introduction
107/144
Technician in Wafer Fab
Photo courtesy of Advanced Micro Devices
Photo 1.8
IC Fabrication An Introduction
-
7/29/2019 IC Fabrication - An Introduction
108/144
IC Fabrication An Introduction
-
7/29/2019 IC Fabrication - An Introduction
109/144
Integrated circuit showingmemory blocks, logic andinput/output pads aroundthe periphery
-
7/29/2019 IC Fabrication - An Introduction
110/144
-
7/29/2019 IC Fabrication - An Introduction
111/144
Six Level of
-
7/29/2019 IC Fabrication - An Introduction
112/144
Six Level ofInterconnection
IC device
-
7/29/2019 IC Fabrication - An Introduction
113/144
drain
-
7/29/2019 IC Fabrication - An Introduction
114/144
Silicon chip High lead solder die attach
Tin/lead plated copperleadframe
Semiconductor Applications
-
7/29/2019 IC Fabrication - An Introduction
115/144
3C : Computer--- /Communication / Consumables
Personal Computer--- Desktop Computer (DT) /Notebook (NB)
Communication---ADSL / Cable Modem /
IEEE802.11X / Bluetooth / VoIP
Consumables---
Game / DVD / Digital Camera 3C merge--- Digital Home
Types of Chips Dynamic Random Access Memory chips
-
7/29/2019 IC Fabrication - An Introduction
116/144
Dynamic Random Access Memory chips(DRAMs) -serve as the primary memory forcomputers
Microprocessors (MPUs) - act as the brains ofcomputers.
Application Specific Integrated Circuits (ASICs)
- are custom semiconductors designed for very specificfunctions
Digital Signal Processors (DSPs) - process signals,such as image and sound signals or radar pulses.
Programmable memory chips (EPROMs,EEPROMs, and Flash)- are used to performfunctions that require programming on the chip.
-
7/29/2019 IC Fabrication - An Introduction
117/144
Semiconductor Fabrication
-
7/29/2019 IC Fabrication - An Introduction
118/144
Front-End Processing (Wafer fabrication)
Back-End Processing (Assembly andTesting)
Processes
Logic Circuit Design / Layout
-
7/29/2019 IC Fabrication - An Introduction
119/144
A logic circuit diagram is drawn to determine theelectronic circuit required for the requested function.
Once the logic circuit diagram is complete,
simulations are performed multiple times to test thecircuits operation.
Design
Photomask Creation
-
7/29/2019 IC Fabrication - An Introduction
120/144
The photomask is a copy of the circuit pattern,
drawn on a glass plate coated with a metallic film. The glass plate lets light pass, but the metallic film
does not.
Due to increasingly high integration andminiaturization of the pattern, the size of thephotomask is usually magnified four to ten timesthe actual size.
The
-
7/29/2019 IC Fabrication - An Introduction
121/144
Thephotomask
of a RF ICChip
Wafer Fabrication A high-purity, single-crystal silicon called
-
7/29/2019 IC Fabrication - An Introduction
122/144
A high purity, single crystal silicon called"99.999999999% (eleven-nine)" is grown from a
seed to an ingot. The wafers are generally available in diameters of
150 mm, 200 mm, or 300 mm, and are mirror-polished and rinsed before shipment from the
wafer manufacturer.
Deposition the wafer is placed in a high-temperature furnace to
-
7/29/2019 IC Fabrication - An Introduction
123/144
the wafer is placed in a high temperature furnace tomake the silicon react with oxygen or water vapor, andto develop oxide films on the wafer surface (thermaloxidation).
To develop nitride films and polysilicon films, thechemical vapor deposition (CVD) method is used, inwhich a gaseous reactant is introduced to the silicon
substrate, and chemical reaction produce the depositedlayer material.
The metallic layers used in the wiring of the circuit arealso formed by CVD, spattering (PVD: physical vapordeposition)
Photoresist Coating
-
7/29/2019 IC Fabrication - An Introduction
124/144
A resin called "photoresist" is coated over theentire wafer. (~1m thick coating.)
Photoresist is a special resin similar inbehavior to photography films that changesproperties when exposed to light.
Masking/Exposure
-
7/29/2019 IC Fabrication - An Introduction
125/144
Placed over the photoresist-coated wafer, whichis then irradiated to have the circuit diagramtranscribed onto it.
An irradiation device called the "stepper" is usedto irradiate the wafer through the mask withultraviolet (UV) light.
-
7/29/2019 IC Fabrication - An Introduction
126/144
Lithography area in clean room
-
7/29/2019 IC Fabrication - An Introduction
127/144
Patterning: Development
-
7/29/2019 IC Fabrication - An Introduction
128/144
The photoresist chemically reacts and dissolves in thedeveloping solution, only on the parts that were notmasked during exposure (positive method).
Development is performed with an alkalinedeveloping solution.
After the development, photoresist is left on thewafer surface in the shape of the mask pattern.
Etching
-
7/29/2019 IC Fabrication - An Introduction
129/144
"Etching" refers to the physical or chemical etchingof oxide films and metallic films using the resistpattern as a mask.
Etching with liquid chemicals is called "wet
etching" and etching with gas is called "dryetching".
-
7/29/2019 IC Fabrication - An Introduction
130/144
Photoresist Stripping
-
7/29/2019 IC Fabrication - An Introduction
131/144
pp g
The photoresist remaining on the wafer surfaceis no longer necessary after etching is complete.Ashing by oxygen plasma or the likes isperformed to remove the residual photoresist.
Device Insulation Layer (Field-Oxide Film) Formation
-
7/29/2019 IC Fabrication - An Introduction
132/144
)
After the oxide film and nitride film aredeveloped, a resist pattern is formed on theregions that will become the deviceinsulation layer.
Ion implantation is performed on the wafer,forming a p-type diffusion layer.
Next, the oxide film and nitride film on thediffusion layer are etched.
Using the nitride film pattern as the mask,
the oxide film that will become the deviceinsulation layer is developed.
-
7/29/2019 IC Fabrication - An Introduction
133/144
Transistor Formation
A d d h
-
7/29/2019 IC Fabrication - An Introduction
134/144
A transistor is a semiconductor device with aswitching function and three terminals:source, drain, and gate.
An insulation layer called "gate oxide" is firstformed on the wafer surface.
A polysilicon film is deposited onto the gateoxide, and a polysilicon gate for controllingthe flow of electrons between the sourceregion and the drain region is formed bylithography and etching.
After the polysilicon gate is formed, an n-type diffusion layer consisting of both thesource and the drain regions is formed byimplantation of impurities
-
7/29/2019 IC Fabrication - An Introduction
135/144
Polysilicon GateCross-Section Image
Metallization Interconnecting the devices such as transistors
-
7/29/2019 IC Fabrication - An Introduction
136/144
Interconnecting the devices, such as transistors,formed on the silicon wafer completes the circuit.
the wafer is first covered with a thick and flatinterlayer insulation film (oxide film). Next, contactholes are drilled by lithograph and etching, throughthe interlayer insulation film, above the devices tobe connected.
Nine-layer Copper Interconnect Architecture
Wafer Inspection
-
7/29/2019 IC Fabrication - An Introduction
137/144
Each IC on the completed wafer is electronically
tested by the tester. After this inspection, the front-end processing iscomplete.
-
7/29/2019 IC Fabrication - An Introduction
138/144
Dicing
In back end processing a wafer completed in
-
7/29/2019 IC Fabrication - An Introduction
139/144
In back end processing, a wafer completed infront end processing is cut into individual IC
chips and encapsulated into packages.
Mounting
After the IC chips are cut apart they
-
7/29/2019 IC Fabrication - An Introduction
140/144
After the IC chips are cut apart, theyare sealed into packages. The ICchips must first be attached to aplatform called the "lead frame.
Wire bonding
-
7/29/2019 IC Fabrication - An Introduction
141/144
g
The mounted IC chips are connected to thelead frames.
Encapsulation
-
7/29/2019 IC Fabrication - An Introduction
142/144
The IC chips and the lead frame islands are
encapsulated with molding resin forprotection.
Characteristic Selection
-
7/29/2019 IC Fabrication - An Introduction
143/144
The packaged IC chips are tested andselected.
Printing and Lead Finish
-
7/29/2019 IC Fabrication - An Introduction
144/144
The final step of IC chip manufacturing is the
printing onto the package surface and thefinishing of leads. After this step, the ICchips are complete.