HSMC Ethernet Quad-PHY Daughter Board

Reference Guide

V2.0 - September 2013

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HSMC Ethernet Quad-PHY

Daughter Board

Reference Guide

Reference Guide


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Table of Contents

1 INTRODUCTION ...................................................................................................................... 4

2 FEATURES .............................................................................................................................. 5

3 BOARD DESCRIPTION ........................................................................................................... 6

3.1 BLOCK DIAGRAM ................................................................................................................... 6 3.2 COMPONENTS ....................................................................................................................... 7

3.2.1 LEDs .......................................................................................................................... 8 3.2.2 MDIO Connector J2 ................................................................................................... 8

4 MAC INTERFACE CLOCKING ............................................................................................... 9

4.1 COMBINED MII/GMII MAC INTERFACE PORT 0 ....................................................................... 9 4.2 RGMII MAC INTERFACE PORTS 1 TO 3 ................................................................................. 9 4.3 SGMII MAC INTERFACE ....................................................................................................... 9

5 POWER-UP STRAP OPTIONS ............................................................................................. 10

6 MDIO MANAGEMENT ........................................................................................................... 12

6.1 MAC INTERFACE OPTIONS .................................................................................................. 12 6.2 RGMII INTEGRATED DELAY OPTIONS .................................................................................. 13

6.2.1 Receive Direction ..................................................................................................... 14 6.2.2 Transmit Direction .................................................................................................... 14

7 HIGH SPEED MEZZANINE CARD (HSMC) CONNECTOR ................................................. 15

7.1 HSMC CONNECTOR PINOUT TABLE..................................................................................... 15 7.2 PIN OUT DESCRIPTION ......................................................................................................... 18

8 PIN OUT FOR ALTERA STRATIX II GX PCIE BOARD ....................................................... 21

9 PIN OUT FOR ALTERA CYCLONE-III STARTER KIT BOARD .......................................... 23

10 PIN OUT FOR ALTERA ARRIA-GX PCIE DEVELOPMENT BOARD............................ 25

11 REFERENCES ................................................................................................................. 28

12 CONTACT ........................................................................................................................ 29

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List of Tables Table 1: LEDs ............................................................................................................................................... 8 Table 2: RJ45 LEDs .................................................................................................................................... 8 Table 3: MDIO Connector J2 ..................................................................................................................... 8 Table 4: Power-Up Strap Options ............................................................................................................11 Table 5: MAC Interface Default Configurations (HWCFG) ...................................................................12 Table 6: Possible MAC Interface Configurations (HWCFG) ................................................................13 Table 7: HSMC Connector Pin out ...........................................................................................................15 Table 8: HSMC Connector Pin out Description ......................................................................................18 Table 9: HSMC Interface Signals (Stratix II GX PCIe Board) ..............................................................21 Table 10: HSMC Interface Signals (Cyclone-III Starter Kit Board) ......................................................23 Table 11: HSMC Interface Signals (Arria-GX PCIe Board) ..................................................................25

List of Figures Figure 1: Quad-PHY Daughter Board ....................................................................................................... 4 Figure 2: Board Block Diagram.................................................................................................................. 6 Figure 3: Board Components ..................................................................................................................... 7 Figure 4: Samtec ASP - 122952 - 01 .......................................................................................................15

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1 Introduction

The Nine Ways PhyworkX Quad-PHY Ethernet Development Kit provides an Ethernet PHY Daughter Board enabling triple-speed 10/100/1000 Ethernet copper connectivity using four standard RJ45 connectors.

The board implements four independent Ethernet interfaces with several system interface options and can be used in single and multi-channel applications.

The daughter board implements a High Speed Mezzanine Card (HSMC) connector to the main board that implements parallel (GMII, RGMII) and serial interfaces (e.g SGMII) and provides the necessary 3.3V power supply.

In combination with the Nine Ways/MorethanIP Ethernet Cores (e.g. MAC, Switch, IEEE 1588) the PHY daughter board can be used to quickly design, implement, prototype and test embedded Ethernet Telecom or Industrial / Military applications from 10 Mbps to Gigabit speeds.

The board is optionally available with reference designs using a MAC, with support for IEEE1588, for precise time synchronization applications, or with a 4-port Switch application.

The board can be used with any Altera (e.g. Arria GX, Stratix II GX, Cyclone III) or Nine Ways board that implements a HSMC connector.

Figure 1: Quad-PHY Daughter Board

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2 Features

High Performance Marvell 88E1145 10/100/1000 Quad Ethernet PHY

o Four independent PHYs in one device

o Auto negotiation for automatic speed selection

o Automatic cable crossover configuration

o GMII, RGMII and SGMII Interfaces

o PHY Management Interface (MDIO/MDC) for configuration/status

o Virtual Cable Tester Feature

4x Standard Ethernet Copper RJ45 connector (10/100/1000 Base-T)

Status LEDs for current speed, link and traffic indications

168pin High Speed Mezzanine Card (HSMC) Connector to main board providing all parallel and serial interfaces

Implements a combined MII/GMII or RGMII on one port (Port 0)

Implements RGMII on the other 3 ports (Ports 1 to 3)

Implements serial 1.25Gbps MII (SGMII) or 1000Base-X (GBIC) interfaces on all ports as an option allowing use of embedded SERDES technologies (e.g. ArriaGX or Stratix IIGX).

Single 3.3V power supply from HSMC Connector

2.5V I/O interfaces (limited 3.3V support available upon request).

Example Reference Designs available for several Altera Main boards upon request

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3 Board Description

3.1 Block Diagram

The Board implements the copper line interfaces using a 4x RJ45 array with integrated magnetics. The MAC interfaces are available at the HSMC connector using 2.5V LVCMOS signaling. The HSMC pin out allows for one port (port0) to use GMII or RGMII. The other 3 ports (1..3) provide the reduced GMII (RGMII).

In addition, all serial interfaces (SGMII) using differential 1.25Gbps signaling (CML) are also available at the HSMC connector. The PHY defaults to parallel interface operation (GMII for port 0 and RGMII for ports 1-3) after power-up and can be configured through the management interface (MDIO) to use the serial interfaces as necessary.

HSMC

Connector

down-

converter

3.3V -> 2.5V

Quad-PHY

88E1145

RJ45

(0)

RJ45

(1)

parallel

interfaces

Oscillator

25 MHz

3.3V from

HSMC VCC_25

MDIO

Connector

(testpoints)

(3x1)

down-

converter

3.3V -> 1.0V

VCC_10

1x MII/GMII

4x Serial (1.25 Gbps)

RJ45

(2)

RJ45

(3)

Serial

(SGMII)

RJ45 Array

including Magnetics

LEDs

3x RGMII

Figure 2: Board Block Diagram

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3.2 Components

1

TX

RX

4x RJ45

Port 0

Port 3

HSMC

(bottom)

MDIO

green: fullduplex

orange: gigabit

Figure 3: Board Components

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3.2.1 LEDs

Table 1: LEDs

LED # Description

1 Port 0 RX traffic

2 Port 0 TX traffic

3 Port 1 RX traffic

4 Port 1 TX traffic

5 Port 2 RX traffic

6 Port 2 TX traffic

7 Port 3 RX traffic

8 Port 3 TX traffic

In addition the RJ45 connector provides a green and orange LED on its front side individual per port.

Table 2: RJ45 LEDs

LED Description

orange (l) Gigabit: Lit when link operates at Gigabit speed

green (r) Duplex: Lit when the link operates in full duplex mode

3.2.2 MDIO Connector J2

To allow for external access to the MDIO interface for testing purposes, if the MDIO is not used through the HSMC connector by the main board’s FPGA application, the interface is available on the 3-pin connector J2.

Table 3: MDIO Connector J2

Pin # Name Description

1 MDIO Serial data input/output

2 MDC Serial clock

3 GND ground

Note: use this connector only when the MDIO/MDC are not driven from the main board

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4 MAC Interface Clocking

After power-up the PHY is configured to implement parallel MAC interfaces using 2.5V LVCMOS I/Os available at the HSMC connector. Due to pin restrictions at the HSMC connector, port 0 has the full GMII wired (allowing GMII and RGMII modes) and ports 1 to 3 have the reduced GMII (RGMII) wired to the connector.

Additionally the serial differential signals of the PHY are available on the HSMC connector to allow implementation of SGMII, which can be enabled through the MDIO management.

4.1 Combined MII/GMII MAC Interface Port 0

The Port 0 MAC interface provides a standard MII/GMII parallel interface. The clocks are:

The receive clock is always provided by the PHY (rxclk_0).

The transmit clock is provided by the PHY only in 10/100 mode of operation (txclk_0). In Gigabit mode of operation the MAC must drive a 125MHz clock on gtxclk_0 to the PHY.

The port can also be used in RGMII mode by configuring the PHY through MDIO accordingly. Then the clocking scheme changes to the following:

The receive clock is always provided by the PHY (rxclk_0).

The transmit clock is always provided by the MAC on gtxclk_0 to the PHY.

4.2 RGMII MAC Interface Ports 1 to 3

Ports 1 to 3 default to RGMII mode of operation. The clocks are:

The receive clock is always provided by the PHY (rxclk_1/2/3).

The transmit clock is always provided by the MAC on gtxclk_1/2/3 to the PHY.

Note that the daughter board does not implement any clock trace delays, hence the PHY must be used in transmit RGMII-ID (integrated delay) mode applying delay to the tx clock input. The MAC RGMII receive interface must implement its DDR input sampling assuming clock edge is aligned with rx data, or use the PHY's receive RGMII-ID applying delay to its rx clock output.

See the RGMII specifications [2], [3] or MorethanIP/Nine Ways RGMII converter core reference guide [1] for more details on timing and typical implementation examples.

4.3 SGMII MAC Interface

The PHY can be programmed to implement the 1.25Gbps serial GMII (SGMII). Each port can be configured individually through the MDIO control interface and the serial interfaces are available in the dedicated bank1 of the HSMC connector.

When SGMII mode is enabled the parallel interface of the corresponding port is no longer used and clocks are recovered from the data on the serial interfaces by the embedded SERDES.

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5 Power-Up Strap Options

When the device powers up it is configured to the following settings.

It defines to use only the MDIO pins of port 0 to access all internal PHY devices. Each PHY has its own address. This MDIO bus is available on the HSMC connector.

The MDIO addresses for the ports 0 to 3 are defined to be 0 to 3 respectively.

The MAC interface modes are set to GMII (port0) and RGMII (ports 1-3).

Auto negotiation is enabled for all ports

Automatic cable crossover is enabled for all ports

The optional 125MHz clock output of the PHY is enabled (dis_125=0) which is wired to the HSMC connector for convenience and can be used as necessary (not required).

Interrupt output 0 is used for all interrupt indications (due to single MDIO interface)

The interrupt output is configured for active high operation (a pull-down resistor is implemented on the daughter board).

Refer to the Marvell 88E1145 datasheet for full detail.

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Table 4: Power-Up Strap Options

Pin Bit3 Bit2 Bit1 Bit0 Value Pin Note

p0_config0 0 0 0 0

0000 (P0_duplex)

PHY addresses 0..3 p1_config0

0 0 0 1 0001 (p0_link1000)

p2_config0 0 0 1 0

0010 (p0_link100)

p3_config0 0 0 1 1

0011 (p0_10)

p0_config1 1 1 1 1

1111 (p3_link10)

GMII

p1_config1 1 0 1 1

1011 (p2_link10)

RGMII

p2_config1 1 0 1 1

1011 (p2_link10)

RGMII

p3_config1 1 0 1 1

1011 (p2_link10)

RGMII

p[3:0]_config2 aneg aneg aneg aneg 1111 (p3_link10)

identical for all 4

p[3:0]_config3 phy4=0 ena_xc=1 dis_fc=1 dis_slp=0 0110 (p1_link100)

identical for all 4

p[3:0]_config4 0 0 sel_twsi=0 en_paus=1 0001 (p0_link1000)

identical for all 4

gconfig0 dis_dte=1 50ohm=0 1MDIO=1 dis_125=0 1010 (p2_link100)

gconfig1 ledsolid=1 pwrup=1 forcesd=1 polhi=0 1110 (p3_link100)

Note: The column "Value Pin" is informal, indicating the wiring to set the 4-bit value according to Table 34 of the Marvell 88E1145 datasheet. Leftmost bit is bit 3.

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6 MDIO Management

The PHY can be configured for several modes of operation through the 2-wire MDIO/MDC management interface. The device is configured to use the signals of Port 0 to communicate with all four internal PHYs. Each PHY has a different address on this MDIO interface, with port 0 being at address 0 and port 3 being at address 3.

6.1 MAC Interface Options

To change the type of MAC interface (GMII, RGMII, SGMII) a vendor specific control register is available in each PHY (HWCFG configuration bits of register 27). The register can be programmed to enable the proper mode of operation for a port. After power-up the interfaces default to the following settings for each port (see also Table 4 page 11):

Table 5: MAC Interface Default Configurations (HWCFG)

Port HWCFG Configuration

Port 0 1111 GMII to Copper

Port 1 1011 RGMII to Copper



The HWCFG column shows the hardware configuration settings available in the PHY MDIO register 27, bits 3:0. To change the mode of MAC interface operation the following procedure must be followed:

read register 27 of the PHY

replace bits 3:0 with the wanted HWCFG setting and keep all other bits unchanged.

write register 27 of the PHY

Issue a software reset to the PHY to apply the change, by reading register 0 (CONTROL) and writing it back with bit 15 (reset) set to 1.

The following settings for HWCFG are possible and the required pins are available at the HSMC connector. The modes need according implementation of the MAC interfaces within the main board application.

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Table 6: Possible MAC Interface Configurations (HWCFG)

HWCFG (3:0) Configuration

1111 GMII to Copper.

Only available for Port 0, as on the other ports the necessary interface pins are not available at the HSMC connector.

1011 RGMII to Copper.

Available for all ports.

0000 SGMII with Clock with SGMII Auto-neg to copper.

Available for Port 0 only as the differential clock is only available for port0 at the HSMC connector (sclk_p/n_0).

0100 SGMII without Clock with SGMII Auto-neg to copper.

Available for all ports using the serial MAC interface pins of the HSMC connector (sin/sout).

1000 1000Base-X without Clock with 1000Base-X Auto-neg to copper (GBIC).


1100 1000Base-X without Clock without 1000Base-X Auto-neg to copper


6.2 RGMII Integrated Delay Options

For operation of RGMII, the RGMII standard ([2], [3]) defines that the clock edge is located inside the valid data window at the DDR input of any device. This can be achieved by either implementing a board trace delay of ~2ns which delays the clocks with respect to the data, or by integrating the delay into the devices (RGMII-ID) allowing for equal trace length board layouts.

The Quad-PHY daughter board does not implement board trace delays. All traces have equal length.

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6.2.1 Receive Direction

The FPGA can accept clock edge aligned input data by adding pin-delay to the data inputs ensuring proper DDR sampling. This can be achieved by applying negative hold-time constraints (e.g. -1.5ns) to the data input pins of the FPGA. The reference designs use this method.

If the pin-delay should not be used, alternatively the PHY can be instructed to add delay to its clock output pin by setting bit 7 of the MDIO register 20. To do so, the following procedure should be followed:

read register 20

set bit 7 to enable rx clock pin output delay preserving all other bits

write register 20


6.2.2 Transmit Direction

A typical DDR output implementation supporting multiple speeds in RGMII will provide the clock edge aligned with the data edge. However, as the board does not implement a board trace delay, the clock needs to be shifted by 2ns to ensure proper timing at the PHY device inputs.

This can be done by either implementing a corresponding shift in the FPGA, or by setting the integrated delay transmit option (bit 1) within the MDIO register 20 of the PHY. To set the transmit delay option; the following procedure should be followed.

read register 20

set bit 1 to enable tx clock pin input delay preserving all other bits

write register 20


All reference designs use the transmit integrated delay setting within the PHY.

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7 High Speed Mezzanine Card (HSMC) Connector

The connector used in HSMC applications is a custom version of the 0.5mm-pitch QTH-DP and mating QSH-DP series from Samtec, Inc. There are three “banks” in this connector. Bank 1 will have every third pin removed as is done in the QSH-DP/QTH-DP series. Bank 2 and Bank 3 have all of the pins populated as done in the QSH/QTH series. The default mating connector is the ASP-122952-02. The ASP-122952-01 connector can plug directly into hosts with QSH-060-01-L-D-DP or QSH-060-01-L-D connectors with the –DP version having slightly better signal integrity.

Figure 4: Samtec ASP - 122952 - 01

7.1 HSMC Connector Pinout Table

Table 4 shows for every pin of the HSMC connector on the board and the corresponding PHY signal. The signal suffix _0.._3 indicates the port number. Unused pins are left blank.

Table 7: HSMC Connector Pin out

HSMC Pin

Function Bank No Function HSMC

Pin

1 HSMC BANK 1

2

3 4

5 6

7 8

9 10

11 12

13 14

15 16

17 sin_p_3 sout_p_3 18

19 sin_n_3 sout_n_3 20






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33 MDIO_0 MDC_0 34

35 36

37 38

39 gtxclk_0 rxclk_0 40

41 txer_0 HSMC BANK 2

rxint_0 42

43 txen_0 txclk_0 44

45 3,3 V 12 V 46

47 txd[7]_0 rxcol_0 48

49 txd[6]_0 rxcrs_0 50

51 3,3 V 12 V 52

53 txd[5]_0 rxerr_0 54

55 txd[4]_0 rxdv_0 56

57 3,3 V 12 V 58

59 txd[3]_0 rxd[7]_0 60

61 txd[2]_0 rxd[6]_0 62

63 3,3 V 12 V 64

65 txd[1]_0 rxd[5]_0 66

67 txd[0]_0 rxd[4]_0 68

69 3,3 V 12 V 70

71 rxd[3]_0 72

73 rxd[2]_0 74

75 3,3 V 12 V 76

77 rxd[1]_0 78

79 reset_n rxd[0]_0 80

81 3,3 V 12 V 82

83 led1000_0 84

85 led1000_1 rxint_3 86

87 3,3 V 12 V 88

89 led1000_2 rxint_2 90

91 led1000_3 rxint_1 92

93 3,3 V 12 V 94

95 sclk_p_0 96

97 sclk_n_0 98

99 3,3 V 12 V 100

101 gtxclk_1

HSMC BANK 3

rxclk_1 102

103 txen_1 rxdv_1 104

105 3,3 V 12 V 106

107 txd[3]_1 rxd[3]_1 108

109 txd[2]_1 rxd[2]_1 110

111 3,3 V 12 V 112

113 txd[1]_1 rxd[1]_1 114

115 txd[0]_1 rxd[0]_1 116

117 3,3 V 12 V 118


121 txen_2 rxdv_2 122

123 3,3 V 12 V 124

125 txd[3]_2 rxd[3]_2 126

127 txd[2]_2 rxd[2]_2 128

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129 3,3 V 12 V 130

131 txd[1]_2 rxd[1]_2 132

133 txd[0]_2 rxd[0]_2 134

135 3,3 V 12 V 136


139 txen_3 rxdv_3 140

141 3,3 V 12 V 142

143 txd[3]_3 rxd[3]_3 144

145 txd[2]_3 rxd[2]_3 146

147 3,3 V 12 V 148

149 txd[1]_3 rxd[1]_3 150

151 txd[0]_3 rxd[0]_3 152

153 3,3 V 12 V 154

155 clk125 156

157 158

159 3,3 V PSNTn (gnd) 160

Notes:

Port 0 has a complete MII/GMII wired to the connector. Can be used in MII/GMII or RGMII mode and it defaults to MII/GMII

Ports 1..3 can only be used in RGMII mode

SGMII clocks for ports 1-3 (sclk_p/n_[1..3]) are not available. Only port 0 may be used in SGMII with clock (non-CDR) mode, the others can be used only in SGMII without clock mode, using CDR.

PSNTn is wired to GND on the daughter board (presence detect).

Only the 3.3V power pins are used. The 12V pins are left unconnected.

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7.2 Pin out description

The following table describes the pin functions. The suffix _0/_1/_2/_3 corresponds to the port number 0 to 3 respectively.

Table 8: HSMC Connector Pin out Description

Function/Name Direction (at PHY)

Description

reset_n input Hardware reset when driven low (0). Must be 1 during normal operation.

Use of the dedicated reset is not required as the power-on reset should be sufficient. Can be used as necessary.

Serial MAC Interfaces (SGMII)

sin_p/n _0/1/2/3 input Serial MAC interface transmit input. When SGMII mode is active this signal pair provides the transmit data.

Should be left unconnected (floating) if not used.

Available for all 4 ports.

sout_p/n _0/1/2/3 output Serial MAC interface receive output. When SGMII mode is active this signal pair provides the receive data.


Available for all 4 ports.

sclk_p/n _0 output Serial MAC interface receive clock output. Is used when SGMII mode with clock is enabled for port0. It provides a 625MHz synchronous clock for sin_p/n_0.


Available for port 0 only

MDIO Management

mdc in Management clock input. The device supports up to 8MHz (standard is 2.5 MHz).

Note: only one MDIO interface is available and all internal PHY devices communicate through this single interface using different MDIO addresses.

mdio inout Management data input/output

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GMII Parallel MAC Interface Port 0

rxclk_0 out 2.5/25/125 MHz receive clock from PHY depending on the link speed.

txclk_0 out 2.5/25 MHz transmit clock from PHY used for 10/100 Mbps operation

Used in GMII/MII mode only. Unused in RGMII mode.

gtxclk_0 in In GMII mode a 125MHz transmit clock to the PHY used for 1Gbps operation

In RGMII mode, the MAC must provide a 2.5/25/125MHz clock depending on the link speed.

rxcol_0 out Receive collision indication from PHY. Used in half-duplex only.

rxcrs_0 out Receive carrier sense indication from PHY. Used in half-duplex only.

rxd[7:0]_0 out Receive data.

Bits 3:0 are used in 10/100 (MII)

Bits 7:0 are used in Gigabit (GMII)

rxdv_0 out receive data valid from PHY

rxer_0 out receive error indication from PHY

txd[7:0]_0

in Transmit data to PHY.

Bits 3:0 are used in 10/100 (MII)

Bits 7:0 are used in Gigabit (GMII)

txer_0 in transmit error indication to PHY

txen_0 in transmit enable to PHY

RGMII Parallel MAC Interface Ports 1 to 3

rxclk_1/2/3 out 2.5/25/125MHz receive clock from PHY

rxdv_1/2/3 out receive control from PHY (DDR) (combined crs/dv)

rxd[3:0] _1/2/3 out receive data from PHY (DDR)

gtxclk_1/2/3 in 2.5/25/125MHz transmit clock to PHY

txen_1/2/3 in transmit control to PHY (DDR) (combined en/err)

txd[3:0]_1/2/3 in transmit data to PHY (DDR)

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Status / Interrupt

led1000 _0/1/2/3 out Active low indication when the link operates at Gigabit speed.

rxint_0 out Interrupt (active high) from PHY.

Note all ports use this port 0 interrupt pin (due to single MDIO management interface mode).

rxint_1/2/3 out Unused, all PHYs share the interrupt of port 0.

PSTNn -- Pin wired to GND on the daughter board. Used as presence detect by the main board.

clk125 out A 125MHz reference clock provided by the PHY. It is available for convenience and can be used for arbitrary purposes or left unconnected.

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8 Pin out for Altera Stratix II GX PCIe Board

The following table shows the pin out for the HSMC-A and HSMC-B connectors available on the Stratix-II GX PCIe development board.

Note that the HSMC-B serial interfaces (sin/sout) are available only when the board is equipped with a 2SGX130 device. HSMC-A is fully populated for 2SGX90 and 2SGX130 variants.

Table 9: HSMC Interface Signals (Stratix II GX PCIe Board)

HSMC A

HSMC B

HSMC Pin

Function Bank

No Function

HSMC Pin

HSMC B

HSMC A

1 Signal HSMC BANK 1

Signal 2

3 Signal Signal 4

5 Signal Signal 6

7 Signal Signal 8

9 Signal Signal 10

11 Signal Signal 12

13 Signal Signal 14

15 Signal Signal 16

G4 AW6 17 sin_p_3 (tx) sout_p_3 (rx) 18 AW3 G1

G5 AW7 19 sin_n_3 sout_n_3 20 AW4 G2

E4 AU4 21 sin_p_2 sout_p_2 22 AU1 E1

E5 AU5 23 sin_n_2 sout_n_2 24 AU2 E2

A6 AN4 25 sin_p_1 sout_p_1 26 AN1 A3

A7 AN5 27 sin_n_1 sout_n_1 28 AN2 A4

C4 AR4 29 sin_p_0 sout_p_0 30 AR1 C1

C5 AR5 31 sin_n_0 sout_n_0 32 AR2 C2

F38 AD34 33 MDIO_0 MDC_0 34 AG30 H36

35 FPGA_3V3_JTAG_TCK FPGA_3V3_JTAG_TMS 36

37 HMSC_3V3_JTAG_TDO FPGA_3V3_JTAG_TDO 38

G22 AN22 39 gtxclk_0 rxclk_0 40 W37 V37

D22 AR22 41 txer_0

rxint_0 42 AT22 F22

A22 AT21 43 txen_0 txclk_0 44 AP22 B22

45 3,3 V 12 V 46

G33 AA33 47 txd[7]_0 rxcol_0 48 AE37 J39

G32 AB33 49 txd[6]_0 rxcrs_0 50 AE36 J38

51 3,3 V 12 V 52

J32 Y27 53 txd[5]_0 rxerr_0 54 AE39 K38

J31 AA26 55 txd[4]_0 rxdv_0 56 AE38 K37

57 3,3 V 12 V 58

K32 AA27 59 txd[3]_0 rxd[7]_0 60 AF39 L37

K31 AB27 61 txd[2]_0 rxd[6]_0 62 AG39 L36

63 3,3 V 12 V 64

K30 AD33 65 txd[1]_0 rxd[5]_0 66 AG38 M37

L31 AE33 67 txd[0]_0 rxd[4]_0 68 AG37 M36

69 3,3 V 12 V 70

M32 AB30 71 -- rxd[3]_0 72 AH39 N38

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M31 AB29 73 -- HSMC BANK 2

rxd[2]_0 74 AH38 N37

75 3,3 V 12 V 76

N32 AB25 77 -- rxd[1]_0 78 AJ39 P37

N31 AC25 79 reset_n rxd[0]_0 80 AK39 P36

81 3,3 V 12 V 82

P30 AD26 83 led1000_0 -- 84 AK38 R35

R31 AD25 85 led1000_1 rxint_3 86 AK37 R34

87 3,3 V 12 V 88

R30 AE27 89 led1000_2 rxint_2 90 AN39 T38

T29 AE26 91 led1000_3 rxint_1 92 AM39 T37

93 3,3 V 12 V 94

W32(p) AM34 95 -- sclk_p_0 96 W39 C39(p)

Y31(n) AM33 97 -- sclk_n_0 98 W38 C38(n)

99 3,3 V 12 V 100

N27 Y34 101 gtxclk_1

HSMC BANK

3

rxclk_1 102 AE35 U37

P28 Y33 103 txen_1 rxdv_1 104 AE34 U36

105 3,3 V 12 V 106

K34 AA32 107 txd[3]_1 rxd[3]_1 108 AF37 N36

K33 AA31 109 txd[2]_1 rxd[2]_1 110 AF36 N35

111 3,3 V 12 V 112

L34 AB32 113 txd[1]_1 rxd[1]_1 114 AG36 K39

L33 AB31 115 txd[0]_1 rxd[0]_1 116 AG35 L39

117 3,3 V 12 V 118

P27 AC34 119 gtxclk_2 rxclk_2 120 AH37 R37

R27 AC33 121 txen_2 rxdv_2 122 AH36 R36

123 3,3 V 12 V 124

N34 AD32 125 txd[3]_2 rxd[3]_2 126 AJ37 M39

N33 AD31 127 txd[2]_2 rxd[2]_2 128 AJ36 M38

129 3,3 V 12 V 130

P34 AC30 131 txd[1]_2 rxd[1]_2 132 AK36 N39

P33 AD30 133 txd[0]_2 rxd[0]_2 134 AK35 P39

135 3,3 V 12 V 136

R33 AB26 137 gtxclk_3 rxclk_3 138 AL39 T35

R32 AC27 139 txen_3 rxdv_3 140 AL38 T34

141 3,3 V 12 V 142

T33 AD27 143 txd[3]_3 rxd[3]_3 144 AP39 R39

T32 AE28 145 txd[2]_3 rxd[2]_3 146 AP38 R38

147 3,3 V 12 V 148

U34 Y25 149 txd[1]_3 rxd[1]_3 150 AR39 U39

U33 AA25 151 txd[0]_3 rxd[0]_3 152 AT39 T39

153 3,3 V 12 V 154

T31(p) AE32 155 -- clk125 156 AU39 V39(p)

T30(n) AE31 157 -- -- 158 AU38 V38(n)

159 3,3 V PSNTn (gnd) 160

Reference Guide


23

9 Pin out for Altera Cyclone-III Starter Kit Board

The following table shows the pin out for the HSMC connectors available on the Cyclone-III Starter Kit development board.

The serial interfaces (sin/sout) are not available with this development board.

Table 10: HSMC Interface Signals (Cyclone-III Starter Kit Board)

FPGA Pin

HSMC Pin

Function Bank

No Function

HSMC Pin

FPGA Pin

1 HSMC BANK 1

2

3 4

5 6

7 8

9 10

11 12

13 14

15 16

17 sin_p_3 (tx) sout_p_3 (rx) 18








E1 33 MDIO_0 MDC_0 34 F3



A1 39 gtxclk_0 rxclk_0 40 A9

H6 41 txer_0, 3.3V HSMC BANK 2

rxint_0 42 D3

M5 43 txen_0, 3.3V txclk_0 44 L6

45 3,3 V 12 V 46

T1 47 txd[7]_0 rxcol_0 48 M3

N7 49 txd[6]_0 rxcrs_0 50 T2

51 3,3 V 12 V 52

N8 53 txd[5]_0 rxerr_0 54 H15

J13 55 txd[4]_0 rxdv_0 56 H16

57 3,3 V 12 V 58

N10 59 txd[3]_0 rxd[7]_0 60 N16

N11 61 txd[2]_0 rxd[6]_0 62 N15

63 3,3 V 12 V 64

K17 65 txd[1]_0 rxd[5]_0 66 R16

P11 67 txd[0]_0 rxd[4]_0 68 T16

69 3,3 V 12 V 70

B2 71 -- rxd[3]_0 72 C2

B1 73 -- rxd[2]_0 74 C1

75 3,3 V 12 V 76

Reference Guide


24

G2 77 --

rxd[1]_0 78 H2

G1 79 reset_n rxd[0]_0 80 H1

81 3,3 V 12 V 82

K2 83 led1000_0 -- 84 K5

K1 85 led1000_1 rxint_3 86 L5

87 3,3 V 12 V 88

L2 89 led1000_2 rxint_2 90 L4

L1 91 led1000_3 rxint_1 92 L3

93 3,3 V 12 V 94

D14 95 -- sclk_p_0 96 F17

C14 97 -- sclk_n_0 98 F18

99 3,3 V 12 V 100

M2 101 gtxclk_1

HSMC BANK

3

rxclk_1 102 P2

M1 103 txen_1 rxdv_1 104 P1

105 3,3 V 12 V 106

R2 107 txd[3]_1 rxd[3]_1 108 T3

R1 109 txd[2]_1 rxd[2]_1 110 R3

111 3,3 V 12 V 112

E17 113 txd[1]_1 rxd[1]_1 114 G17

E18 115 txd[0]_1 rxd[0]_1 116 G18

117 3,3 V 12 V 118

H17 119 gtxclk_2 rxclk_2 120 K18

H18 121 txen_2 rxdv_2 122 L18

123 3,3 V 12 V 124

L17 125 txd[3]_2 rxd[3]_2 126 L16

M18 127 txd[2]_2 rxd[2]_2 128 M17

129 3,3 V 12 V 130

L14 131 txd[1]_2 rxd[1]_2 132 L13

L15 133 txd[0]_2 rxd[0]_2 134 M14

135 3,3 V 12 V 136

P17 137 gtxclk_3 rxclk_3 138 R17

P18 139 txen_3 rxdv_3 140 R18

141 3,3 V 12 V 142

R5 143 txd[3]_3 rxd[3]_3 144 M6

R4 145 txd[2]_3 rxd[2]_3 146 N6

147 3,3 V 12 V 148

T17 149 txd[1]_3 rxd[1]_3 150 M13

T18 151 txd[0]_3 rxd[0]_3 152 N13

153 3,3 V 12 V 154

U18 155 -- clk125 156 N17

V18 157 -- -- 158 N18

159 3,3 V PSNTn (gnd) 160

Reference Guide


25

10 Pin out for Altera Arria-GX PCIe Development Board

The following table shows the pin out for the HSMC connectors available on the Arria-GX PCIe Development Board.

Table 11: HSMC Interface Signals (Arria-GX PCIe Board)

FPGA Pin

HSMC Pin

Function Bank

No Function

HSMC Pin

FPGA Pin

1 HSMC BANK 1

2

3 4

5 6

7 8

9 10

11 12

13 14

15 16

N4 17 sin_p_3 (tx) sout_p_3 (rx) 18 N1

N5 19 sin_n_3 sout_n_3 20 N2

L4 21 sin_p_2 sout_p_2 22 L1

L5 23 sin_n_2 sout_n_2 24 L2

C4 25 sin_p_1 sout_p_1 26 E1

C5 27 sin_n_1 sout_n_1 28 E2

E4 29 sin_p_0 sout_p_0 30 G1

C5 31 sin_n_0 sout_n_0 32 G2

A20 33 MDIO_0 MDC_0* 34 A18



A15 39 gtxclk_0* rxclk_0 40 T25

A25 41 txer_0* HSMC BANK 2

rxint_0 42 A26

A23 43 txen_0* txclk_0 44 A24

45 3,3 V 12 V 46

F24 47 txd[7]_0 rxcol_0 48 C28

F23 49 txd[6]_0 rxcrs_0 50 C27

51 3,3 V 12 V 52

E26 53 txd[5]_0 rxerr_0 54 D28

E25 55 txd[4]_0 rxdv_0 56 D27

57 3,3 V 12 V 58

G24 59 txd[3]_0 rxd[7]_0 60 E28

G23 61 txd[2]_0 rxd[6]_0 62 F28

63 3,3 V 12 V 64

H23 65 txd[1]_0 rxd[5]_0 66 F27

H22 67 txd[0]_0 rxd[4]_0 68 F26

69 3,3 V 12 V 70

K24 71 -- rxd[3]_0 72 G28

J23 73 -- rxd[2]_0 74 G27

75 3,3 V 12 V 76

G26 77 -- rxd[1]_0 78 H28

G25 79 reset_n rxd[0]_0 80 J28

Reference Guide


26

81 3,3 V 12 V 82

H26 83 led1000_0 -- 84 L28

H25 85 led1000_1 rxint_3 86 M28

87 3,3 V 12 V 88

J25 89 led1000_2 rxint_2 90 N28

J24 91 led1000_3 rxint_1 92 P28

93 3,3 V 12 V 94

AC23 95 -- sclk_p_0 96 U26

AC22 97 -- sclk_n_0 98 U25

99 3,3 V 12 V 100

K26 101 gtxclk_1

HSMC BANK

3

rxclk_1 102 R28

K25 103 txen_1 rxdv_1 104 T28

105 3,3 V 12 V 106

M25 107 txd[3]_1 rxd[3]_1 108 V28

M24 109 txd[2]_1 rxd[2]_1 110 W28

111 3,3 V 12 V 112

P25 113 txd[1]_1 rxd[1]_1 114 Y28

P24 115 txd[0]_1 rxd[0]_1 116 AA28

117 3,3 V 12 V 118

Y25 119 gtxclk_2 rxclk_2 120 Y27

Y24 121 txen_2 rxdv_2 122 Y26

123 3,3 V 12 V 124

AA26 125 txd[3]_2 rxd[3]_2 126 AB28

AA25 127 txd[2]_2 rxd[2]_2 128 AB27

129 3,3 V 12 V 130

AA23 131 txd[1]_2 rxd[1]_2 132 AC28

AA22 133 txd[0]_2 rxd[0]_2 134 AD28

135 3,3 V 12 V 136

AB22 137 gtxclk_3 rxclk_3 138 AC27

AB21 139 txen_3 rxdv_3 140 AC26

141 3,3 V 12 V 142

AB24 143 txd[3]_3 rxd[3]_3 144 AE28

AB23 145 txd[2]_3 rxd[2]_3 146 AE27

147 3,3 V 12 V 148

AC25 149 txd[1]_3 rxd[1]_3 150 AF28

AC24 151 txd[0]_3 rxd[0]_3 152 AF27

153 3,3 V 12 V 154

AE26 155 -- clk125 156 R26

AE25 157 -- -- 158 R25

159 3,3 V PSNTn (gnd) 160

Reference Guide


27

ArriaGX PCIe Board specific notes:

The pins mdc, p0gtxclk, p0txen, p0txer (*) are wired to 3.3V banks. Set the voltage levels to 3.3V for these outputs. All other outputs must be set to 2.5V.

Set the following current strength on the outputs:

o 4mA for p1gtxclk, p2gtxclk, p3gtxclk o 12mA for all others

(Setting the RGMII output clocks with a lower current strength delays these pins with respect to the data pins which is desired to fulfill the RGMII specifications)

General note for ArriaGX: When using input clocks only to feed PLL inputs, no logic, you must set the global signal/global clock attribute within Quartus for these inputs. Otherwise it has been seen that the PLLs do not lock properly. The .qsf should contain: set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to clk1_p

Reference Guide


28

11 References

[1] MorethanIP/Nine Ways RGMII Converter Core

[2] Reduced Gigabit Media Independent Interface (RGMII), 12/10/2000 Version 1.3

[3] Reduced Gigabit Media Independent Interface (RGMII), 4/1/2002 Version 2.0

Reference Guide


29

12 Contact

MorethanIP GmbH

E-Mail : [email protected]

Internet : www.morethanip.com

Europe

Muenchner Str. 199

D-85757 Karlsfeld

Germany

Tel : +49 (0) 8131 333939 0

FAX : +49 (0) 8131 333939 1

`Nine Ways Research & Development Ltd

E-Mail : [email protected]

Internet : www.nineways.co.uk

UK

Unit G.15, iDCentre, Lathkill House, rtc Business Park

London Road, Derby. DE24 8UP

United Kingdom

Tel : +44 (0) 1332 258847

FAX : +44 (0) 1332 258823

mailto:[email protected]

http://www.morethanip.com/

mailto:[email protected]

HSMC Ethernet Quad-PHY Daughter Board

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