HS/DSL ProjectHS/DSL Project

Yael Grossman Arik Krantz

Implementation and Synthesis of a 3-Port PCI-Express

Switch

Project DescriptionProject Description

We will implement:

3 - port switch for PCI-Express Transfer rate: 2.5 GBit/sec 1 upstream, 2 downstream full-duplex

ports CRC support at the DLL layer Arbitration mechanism for incoming

packets Packet routing through lookup tables

Switch Relative to SystemSwitch Relative to System

Layered Switch ModelLayered Switch Model

CRC computation and verification mechanism Applied in the Data Link layer

Transport control mechanism Via ACK/NACKs

Applied in the Data Link layer Unacknowledged TLPs retransmitted after timeout

Routing mechanism Forwarding based on central lookup table Applied in the Transaction layer

Initial configuration mechanism Static loading of lookup tables at startup

Primary StructuresPrimary Structures

1. Detailed design 2 weeks Data flow diagram (transmitter/ receiver) for ports Queue and buffer structure for ports Lookup table structure and algorithm Packet handling algorithms

2. System block design 2 weeks Division of the system into interconnected entities Definition of appropriate architecture per entity Preparation for VHDL implementation

3. VHDL coding 4 weeks In accordance with architecture design

Semester PlanSemester Plan