Hrushikesh ChavanYounggyun Cho

Structural Fault Tolerance for SOC

• Motivation

• Introduction

• BISER FF & Razor FF

• FITO

• Implementation

• Simulation result

• Conclusion

• Future work

Agenda

Motivation• Number of transistors increasing

• Cramming more components in a single Chip

• Device parameters are not as intended by the designer

• SoC design more vulnerable to internal and external noise

• Important to design a fault tolerant circuit

Introduction• Transient Fault

• Temporary faults in flip-flop or latch or any memory cell (SEU)

• Temporary faults in a combinational circuit (SET)

Introduction• Single Event Upset (SEU)

• Another name of Soft Error

• Changing state

• Ionizing radiations

• Electromagnetic interference

Introduction• Soft Error Fault Tolerant System

• Detect and correct the soft errors

[Mitra-05]

Introduction

• How to make the fault tolerant circuits?

• Redundancy

• Hardware & Time

• BISER FF & Razor FF

BISER FFs

• Built-In Soft Error Resilience

• C-element

• Four Latches

[Ravindran-09]

BISER FFs

• C-element

[http://en.wikipedia.org/wiki/C-element]

BISER FFs• C-element with four latches

[Ravindran-09]

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Razor FFs

• Razor FF

[Ravindran-09]

Razor FFs

• How to select CLK Delay

• The shortest path is more than CLK delay

• Time violation can corrupt the system

• More buffers on the path can prevent

Working of Razor F/F (Fault in Sequential Part)

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Working of Razor F/F (Fault in Combinational Part)

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FITO

• Fault Injection Tool

• High observability and controllability

• A key to evaluating fault-tolerant techniques

FITO

• Synthesizable bit-flip fault model

[Reddy-13]

Implementation

• Implemented 5 Stage Pipeline to test BISER and Razor flop.

• Pipeline implements ADD, ADDI, SUB, AND, OR, SLL, LW, SW, BEQ, JUMP and HLT.

• Replaced ID/EX and EX/MEM flops with fault tolerant flops.

• Executed 4 test benches to test the system.

Pipelined Processor Architecture

Tools• Verilog HDL

• Synopsis Design Vision

Testing Methodology• Clock Period ~ 20ns• Clock Delay ~ 4ns (for Razor F/F)• Transient fault duration < 4ns• Number of faults injected/iteration = 5• Random duration between two consecutive

faults.

Circuit Modifications with FITO (BISER)

Circuit Modifications with FITO (Razor)

Simulation and Results

INDIVIDUAL AREA AND POWER

Area and Power after 2 Pipelines Swapped with BISER and Razor F/F

Performance for Normal Operation

Performance with BISER F/F

Performance with RAZOR F/F

• Project implemented two types of fault

tolerant design techniques.

• Choice of design application specific.

• Both techniques efficient and practical to

design systems.

Conclusion

Future Work

• Reduce cost due to latches.

• Implement Dynamic Voltage and Frequency

Scaling for Razor.

• Hybrid Flop

• Fault Tolerance for Memories

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Thank You

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Questions?