Host program Interface User design · 2019-03-08 · 5 Copyright © 2018 Future Design Systems Inc....

1

Future Design Systems

www.future-ds.com

March 2019

Connect any computer to FPGA through USB

Copyright © 2017-2018-2019 Future Design Systems, Inc. ( 2 )

Connect Linux/Windows/Android to your FPGA

board through USB 3.0

CON_FMC

FPGA

LCDCIS

Interface User designHost program

2

Copyright © 2017-2018-2019 Future Design Systems, Inc.

CON-FMC OVERVIEW


( 3 )

FPGA

CON-FMC

FPGA Carrier Card

PC Win/Linux

FPGA

CON-FMC

FPGA Carrier Card

Android


CON-FMC along with board

( 4 )

3


What is FMC

FPGA Mezzanine Card

VITA

http://www.vita.com/

VITA FMC

http://www.vita.com/fmc

VITA 57.1.1

HPC+/HPCP (HPC plus): 14x40 (560)

HPC (High Pin Count): 10x40 (400)

LPC (Low Pin Count): 4x40 (160)

( 5 )


CON-FMC

USB 3.0 and 2.0Cypress FX3

FMC/FMC+ (LPC, HPC, HPC+)VITA 57.1 LPC

Multi-board supporting up to 8CID

PlatformsWindows

Linux

Android (Java and native)

Additional featuresC API to develop user application

AMBA AXI/AHB/APB BFM

Performance~80~100Mbyte/sec (USB3.0)

~10Mbyte/sec (USB2.0)

Companion products: CON-GPIO, CON-FPGA

( 6 )

4


CON-FMC TYPICAL USAGES


( 7 )

CON-FMC FPGA

FPGA Board

AMBA BFMAny block with AMBA

Host program


Easy to install from GitHub

( 8 )

5

Copyright © 2018 Future Design Systems Inc.

Example template for AMBA AXI and AHB

AMBA AHB memory

User case using AHB template for

SHA256 (serial)

AMBA AXI memory

User case using AXI template for

AES128 (pipelined)

( 9 )

FPGA

CON-FMC

FPGA Carrier Card

USB

BFM AHB Interface

AHB Block Memory

C program

AHB

FPGA

CON-FMC

FPGA Carrier Card

USB

BFM AXI Interface

AXI Block Memory

C program

AXI

FPGA

CON-FMC

FPGA Carrier Card

USB

BFM AHB Interface

SHA256C program

AHB

FPGA

CON-FMC

FPGA Carrier Card

USB

BFM AXI Interface

AES128C program

AXI


CON-FMC multi-programming

Multi-programming

different programs access to different CID

Supported

Multi-threading

the same program access different CID

Supported

(multi-threading requires user-level

exclusion)

different programs access the same CID

Not supported yet

(it requires system-wide exclusion)

( 10 )

FGPA

CON-FMC

CON-FMC

FGPA

CON-FMC CON-FMC

FGPA

CON-FMC

FGPA

CON-FMC

6


Programming interfaces

Standard C/C++ interface Python interface

( 11 )

FGPA

CON-FMC

Device driver(usbfs/WinUSB)

libusb API(libusb-1.0)

CON-FMC API(conapi)

Python application

CON-FMC board

User Design

User design

Python wrapper (pyconfmc)

FGPA

CON-FMC

Device driver(usbfs/WinUSB)

libusb API(libusb-1.0)

CON-FMC API(conapi)

Application

Firmware(confx3)

CON-FMC board

User Design

User design


Simple API: C and C++

Minimum code: C API’s

( 12 )

GNU GCC supporting

7


Simple API wrappers

Bus Functional Module API Python

( 13 )

Generates AXI or AHB write bus transaction

with the given arguments:

• addr: address

• data: buffer containing data to be written

• size: num of bytes for each beat

• length: length of burst, i.e., num of beats


Bandwidth (highly depending on environments)

x86_64 Ubuntu 16.04 / USB 3.0~50MB/sec for pseudo-DMA loopback

(bandwidth for pure payload)

~85MB/sec for stream loopback

~250MB/sec for stream in or out

x86_64 Cygwin on Windows / USB

3.0~45MB/sec for pseudo-DMA loopback

~45MB/sec for stream loopback

~90MB/sec for stream out

~120MB/sec for stream in

( 14 )

8


CON-FMC EXAMPLES


( 15 )


Example project

AES (Advance Encryption Standard)~35 times fast result in terms of time comparing

to pure software

FPGA Board

(ML605)

CON-FMC

Odroid-XU4

Data processing speed (MB/sec)

( 16 )

interface AESCON-FMC

Board

FPGA Board

Odroid

XU4USB FMC

Image feeding &display program

9


Example project

NeuralFMC system

CON-FMC provides a path to receive

neural signal data through USB.

( 17 )


Example project

HSR/PTP (High-availability

Seamless Redundancy and

Precision Time Protocol)

CON-FMC to inject user-defined Ethernet

packets and to snoop packets on the line.

( 18 )

CON-FMC

Ethernet port

HSR ring

Pkt. Gen

Pkt. Snoop

MA

C w

ith

HS

R

MA

C w

ith

HS

R

DANH

processor system

MAC with HSR

DANH

processor system

MAC with HSR

DANH

processor system

MAC with HSR

DANH

processor system

MAC with HSR

RedBox

RedBox

10


(주)퓨쳐디자인시스템

FUTUREDesign Systems

• 주소: 대전광역시유성구문지로 193,

KAIST 문지캠퍼스학부동 F723호

• 전화: (042) 864-0211~2

• 전자우편: [email protected]

• 홈페이지: www.future-ds.com

• 위치: http://ouic.kaist.ac.kr/sub04_06

( 19 )

Host program Interface User design · 2019-03-08 · 5 Copyright © 2018 Future Design Systems Inc....

Documents

Transcript of Host program Interface User design · 2019-03-08 · 5 Copyright © 2018 Future Design Systems Inc....