Host Bus Adapter Schematics for Intel(R) 8134x I/O...
Transcript of Host Bus Adapter Schematics for Intel(R) 8134x I/O...
Order Number: 315367-002US
Host Bus Adapter Schematics for Intel(R) 8134x I/O Processors
February 2007
Host Bus Adapter Schematics for Intel(R) 8134x I/O ProcessorsFebruary 2007
2 Order Number: 315367-002US
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Host Bus Adapter Schematics for Intel(R) 8134x I/O ProcessorsFebruary 2007Order Number: 315367-002US 3
Contents—Host Bus Adapter Schematics for Intel(R) 8134x I/O Processors
Contents
1.0 Schematics Overview ................................................................................................7
1.1 Product Descriptions ............................................................................................7
1.2 CRB Block Diagrams ............................................................................................7
2.0 CRB Top View ............................................................................................................9
3.0 Power Regulators Top View ..................................................................................... 10
4.0 DIP Switches ........................................................................................................... 11
5.0 Module Contents...................................................................................................... 12
6.0 SDRAM .................................................................................................................... 13
7.0 Storage/PCI-Express............................................................................................... 14
8.0 PCI-X Bus ................................................................................................................ 15
9.0 Peripheral Bus/ Misc ............................................................................................... 16
10.0 Power/ Filters ......................................................................................................... 17
11.0 Power ...................................................................................................................... 18
12.0 Ground/ No Connects .............................................................................................. 19
13.0 Differential Oscillator 125 MHz ................................................................................ 20
14.0 PCI-EXPRESS Edge Connector.................................................................................. 21
15.0 DDR2 DIMM Socket.................................................................................................. 22
16.0 VTT Generation and DIMM Power ............................................................................ 23
17.0 SAS Connector 4X1 Internal (Dual Stacked) ............................................................ 24
18.0 SAS Connector X4 Internal ...................................................................................... 25
19.0 SGPIO/ HD LED MUX ............................................................................................... 26
20.0 PCI-X Straddle Mount (SM) Slot............................................................................... 27
21.0 VREG 3P3V_BUCK .................................................................................................... 28
22.0 GBE_82545GM_Module - 1....................................................................................... 29
23.0 GBE_82545GM_Module - 2....................................................................................... 30
24.0 GBE_82545GM_Module - 3....................................................................................... 31
Host Bus Adapter Schematics for Intel(R) 8134x I/O Processors—Contents
Host Bus Adapter Schematics for Intel(R) 8134x I/O ProcessorsFebruary 2007
4 Order Number: 315367-002US
25.0 Flash - 8M ................................................................................................................32
26.0 NVSRAM...................................................................................................................33
27.0 PBI Auxiliary Connector ...........................................................................................34
28.0 CPLD Version A Module ............................................................................................35
29.0 Buzzer .....................................................................................................................36
30.0 RS232_Dual_MOD ....................................................................................................37
31.0 JTAG_CONN_Module ................................................................................................38
32.0 VREG +1P2V Linear (Not Populated)........................................................................39
33.0 VREG 1P8V Linear (Not Populated) ..........................................................................40
34.0 VREG 1P8V_5_BUCK ................................................................................................41
35.0 VREG 1P2V_BUCK ....................................................................................................42
Host Bus Adapter Schematics for Intel(R) 8134x I/O ProcessorsFebruary 2007Order Number: 315367-002US 5
Revision History—Host Bus Adapter Schematics for Intel(R) 8134x I/O Processors
Revision History
Date Revision Description
February 2007 002 Added Differential Oscillator 125 MHz page.
September 2006 001 Initial release.
Host Bus Adapter Schematics for Intel(R) 8134x I/O Processors—Revision History
Host Bus Adapter Schematics for Intel(R) 8134x I/O ProcessorsFebruary 2007
6 Order Number: 315367-002US
§ §
Host Bus Adapter Schematics for Intel(R) 8134x I/O ProcessorsFebruary 2007Order Number: 315367-002US 7
1.0—Host Bus Adapter Schematics for Intel(R) 8134x I/O Processors
1.0 Schematics Overview
This manual provides the Host Bus Adapter schematics for Intel(R) 8134x I/O Processors.
1.1 Product Descriptions
The products available from Intel in the 8134x family include:
• Intel® 81348 I/O Processor-based host bus adapter with 8-port SAS/SATA controller.
• Intel® 81341 I/O Processor-based host bus adapter with one processing core.
• Intel® 81342 I/O Processor-based host bus adapter with two processing cores.
• Intel® 413808 I/O Controller-based host bus adapter with 8-port SAS/SATA controller and 800 MHz SAS engine
• Intel® 413812 I/O Controller-based host bus adapter with 8-port SAS/SATA controller and 1200 MHz SAS engine
Note: The Intel® 81348 and Intel® 81341 and Intel® 81342 products are I/O Processors (8134x). The Intel® 413808 and Intel® 413812 products are I/O Controllers (4138xx). In this manual for simplicity, we refer to all products as “processors”.
Contact your Intel Representative for more product information.
1.2 CRB Block Diagrams
Figure 1 shows the product block diagrams.
DDRII 400/533 DIMM
SlotPCI-X Bus (100 MHz)
�����
Gig-E
Edge Connector
PC
Ie x
8
SGPIO
JTAG
I2C
SASSASSASSAS
x4 SAS/SATA
x4 SAS/SATA
4 port SAS Int.
RS-232
HEX & Discrete
LED
Local Bus
GPIONVRAMSTK14C88
8 MBFLASH
CPLD
I2C
I2C
I2C
Buzzer
PB
I Co
nn
ecto
r
RotarySwitch
2 KBSerial
EEPROM 24LC16B
DDR II SDRAM
GbE
PCI-X Con
JTAG Con
CPLD
Xtal25 MHz
P_CLKO[3:0]
P_CLKOUT
P_CLKIN
S_CLK +
P_CLKO1
P_CLKO0
TCK
SCL2 M_CK[2:0] +
M_CK[2:0] +
267 MHz
33/66/100 MHz
SCL1
SCL0
I2C Con 1
I2C Con 0
I2C Con 2
SAS 4-Port Internal Con
SCLOCK0
125 MHz Clk Synth125 MHz
Xtal25 MHz
PCI-E Con
REFCLK +
REFCLK +
SMBCLK
100 MHz
Serial EEPROM
Clock
PBI ConSCL<2..0>
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��� � ��� ��������
� ���������
������������
����� DDR II SDRAM
�����
�����
JTAG Con
CPLD
P_RST#
SRST#WARM_RST#
M_RST#
TRST#TRST#
PBI ConPB_RSTOUT#
Flash
PCI-X ConP_RSTOUT#
GbE
PE_RST#
PE_RST_B_N#
SRST#
PCI-E Con
BufPE_RST_B_N#
+3.3v
+12v
GbECPLDFlash
Misc Logic
BuzzerHex LEDNVRAM
Serial Port Buffers
Regulator+2.5v
Regulator
Regulator
PC
I-E
Con
GbE
Aux
Pow
er C
on +12vPCI PCI-X Slot
+5vPCI PCI-X Slot
+3.3vPCIRegulator PCI-X Slot
PB
I Con
Regulator
+1.5v GbE
+1_8V_B +1.8V
Resistor Dividers
+Vtt DDR
DDR II SDRAM
8134x
Iso
+1.8v_PE
+1.8v_AS
+1.2v_PE+1.2v_AS
+1.2v+1.2v_Iso
Flt
Flt
PLL_VCC
PLL_VCC
�����
Host Bus Adapter Schematics for Intel® 8134x I/O Processors 8
PAGE 26
SAS CLOCK PAGE 14
PAGE 28
PAGE 32
PAGE
30
PAGE 29
PAGES 23-25
PAGE 21
PAGE 20
PAGE 19
PAGE 18
PAGE 15
PAGES 6-13
TEST POINT
CRB TOP VIEW
PAGE 27
PAGE 31
PAGE 16-17
+3_3V
DDR_
SA<2
..0>
Tue Aug 15 09:39:13 2006 5.00-700
4
5
6
13
2
U2D5
21
R3A1
1
21R8L5
21R9L3
21
R8N4
21
R8M
42
1R8
M3
21
R8M
2
21
R2A3
7
84
2
1 U8B2
3
84
6
5 U8B2
2
1
C9C1
21
R9C1 4
5
613
2
U9C1
21R7M11
21R3N3
21
21R2N17
21R2N15
21R2N13
21R2N11
21R2N8
21R2N6
2
1
C2A9
21
R2A1
2
21R3A10
21R4A19
21R3A9
21R7M1
21R7L6
21R7L4
21R6L1
21R7M6
21R7L7
R7L5R7M3
21R5D2
74
8
56
321
U8C1
NVRAM_CS_N
SAS_RX_N<7..0>
PCI_RSTOUT_N
SMBDAT
PCI_XINT_N<7..6>
EMPTY
BATT_PRSNT_N
GPIO<7..0>
WARM_RST_PBI_N
NVRAM_CS_N
0
3A8
2B4
PCI_M66ENPCI_PAR64
+3_3V
PCI_REQ64_NPCI_ACK64_N
EMPTY 1%
8.2K
DDR_
RAS_
NDD
R_BA
<2..0
>DD
R_M
A<15
..0>
DDR_
DM<8
..0>
SAS_ACT<7..0>
DDR_
WE_
NDD
R_CA
S_N
PCI_CBE_N<7..0>PCI_M66ENPCI_PAR64PCI_REQ64_N
4.7K
4.7K
PCI_
LAN_
P WR_
GO
OD
5%5%4.
7K
PCI_PERR_N
PCI_TRDY_N
PCI_FRAME_N
PCI_ACK64_N
3B81C6
3B81C65%
PCI_
CLK_
R<3.
.0>
PCI_
REQ
_N<3
..0>
PCI_IDSEL
PCI_AD<63..0>
2A8
3B8
BATT_DISCHRGBATT_CHRG
BATT_ENABLE
DDR_MISC<3..0>
SMBCLKSDA<2..0>SCL<2..0>
DDR_CKE_B<1..0>
PBI_AUX_CE_NPE_RST_B_NWARM_RST_PBI_NBOOT_WIDTH_8_N PCI_XCAP
PCI_FRAME_N
PCI_CBE_N<7..0>
PCI_TRDY_NPCI_IRDY_N
DDR_
CS_N
<1..0
>DD
R_CK
E<1.
.0>
DDR_
ODT<
1..0
>
DDR_
CK_P
<2..0
>
2C5
SDAT
AOUT
SDAT
AINSL
OAD
SCLO
CK
74LVC2G08
74LVC2G08
2A61D3
4B8
3B8
1M
U_RXD<1..0>
PE_R
EFCL
K_N
PE_RST_N
+1_8V_B
7
8.2K
DDR_
CK_N
<2..0
>
DDR_MISC<3..0>
PE_R
_P<7
..0>
PE_R
EFCL
K_P
PCI_PAR
GPIO<7..0>
PCI_RSTOUT_N
3C5 1B7
5%
1K
PE_RST_B_N
74LVC1G58
+3_3V
CPLD_CLK
+3_3V
GPIO<6>
1UF
0
HPI_N
PBI_D<15..0>
SL_TRST_N
PCI_IRDY_N
0
DDR_CKE<1..0>
WAR
M_R
ST_J
TAG
_N
0
18
5%
WARM_RST_N
1
0.01
UF
8.2K
10K
5%
DDR_
RESE
T_N
5%8.2K
GPIO<7>
2
4444
CPLD_CLK
44
44
+3_3V
SAS_STAT<7..0>SAS_TX_N<7..0>SAS_TX_P<7..0>
SCL<
2..0
>
SDA<
2..0
>
0 22
0
16
5%
5%
0
SL_TMS
CPLD_TDO
SL_TDISL_TDO
01
8.2K 5%8.2K 5%
5%
11
118
0
0
58
17
1K 5%
+3_3V
7654321
5%5%
8.2K 5%8.2K8.2K 5%8.2K 5%8.2K 5%
10K
8.2K8.2K 5%
5%8.2K5%
8.2K5%5%
123456
BATT_CHRG
PBI_A<19..16>
8
74LVC1G58
+1_8V_B
1
00 DDR_CKE_B<1..0>
1
5%
SAS_RX_P<7..0>
THERMOSTAT_N
U_TXD<1..0>1
0
17
PCI_SERR_N
PCI_STOP_N
PCI_SERR_NPCI_PERR_N
5%
+3_3V
POK_
1P8
140K EMPT
Y75K
1%
+1_8V_B
+3_3V
33 5%
PCI_DEVSEL_NPCI_STOP_N
8.2K
3
0
PCI_CLKIN
PCI_XINT_N<7..0>2
5%
BATT_DISCHRG
NMI_N<1..0>
+3_3V
GBE_TRST_N
SL_TEST<31..0>
PBI_AUX_CE_N
PCI_PAR
PCI_GNT_N<3..0>
8.2K
SMBD
AT
2A41B7
BP_DET_N
PE_T
_P<7
.. 0>
8.2K
PBI_POE_N
24LC16B
SL_TCKGBE_TDIGBE_TDO
PCI_DEVSEL_N
PBI_A<24..0>
BATT_PRSNT_N
U_CTS_N<1..0>
PBI_PWE_N
PBI_POE_NPBI_PWE_N
BUZZ
ER_C
RTL
BOOT_WIDTH_8_N
BATT_ENABLE8.2K
5%
21
DDR_
DQS_
P<8.
.0>
DDR_
DQS_
N<8.
.0>
DDR_
DQ<6
3..0
>DD
R_CB
<7..0
>
CPLD_TDI
PE_R
ST_N
SMBC
LK
PBI_RSTOUT_NPBI_PCE_N<1..0>PBI_PWE_NPBI_POE_N
R3N2
19
15
PE_T
_N<7
..0>
U_RTS_N<1..0>
PE_R
_N<7
..0>
1D8
1C5
3B8
1B7
1A7
1B7
1B7
1B7
3C5
1D1
1D7
1A6
1B7
1C8
1B3
1D4
2A4
1C5
1A4
1A4
1D4 1B6
1C8
1D7
1D7
1D7
1B7
1A4
1C7
1B7 1B6
1B7 1B6
1A7
1B7
1B7
1B7
1B7
3C8
68
2
A
B
C
D
2 1345
D
C
B
A
8 6 5 3
MODIFIEDSHEET
4 1
DRAWING REVBOARD REV
7
7
VCC+1.8<<VCC+3.3<<
GLOBALS
CPLD_VERSION_A_MOD
REV 0.60
PBI_PCE_N1PBI_RST_N
PBI_D<7..0>
PBI_AUX_CE_N
PBI_A<19..16>
BATT_DISCHRG
CPLD_TCKNVRAM_CS_NBUZZER_CRTLBATT_ENABLE
SL_GPIO<4..0>CPLD_TDI
CPLD_TDOCPLD_TMSPCI_CLK
BATT_CHRG
PBI_POE_NPBI_PWE_N
BATT_PRSNT_N
REV 0.055
>>+3.3VGLOBALS
FLASH_28F640J3_MOD
PBI_D<15..0>PBI_RSTOUT_N
PBI_PCE0_NPBI_PWE_N
PBI_A<24..0>PBI_POE_N
BYTE_WIDTH_N
GLOBALS
+1.8V<<+3.3V<<
+12V<<
PBI_CONN_M
OD
REV:1.2
BATT_ENABLEBATT_PRSNT_N
PBI_D<15..0>PBI_CLK<1..0>
PBI_GPIO<7..0>
VBATT_1P8V
SMBDATSMBCLK
BATT_DISCHRGBATT_CHRG
PBI_NC
PE_RST_NWARM_RST_N
FLASH_16B_8BPBI_XINT_N<7..6>
PBI_I2C_SCL<2..0>PBI_I2C_SDA<2..0>
PBI_AUX_CE_NPBI_NVSRAM_CE_N
PBI_CKE<1..0>
PBI_RSTOUT_NPBI_PCE_N<1..0>
PBI_PWE_NPBI_POE_N
PBI_A<24..0>
DDR_MISC<3..0>
NAND FUNCTIONTO VCC FORSHORT PIN 3
BAVCC
VCC
GND
Y
OUT
GLOBALS>>+3_3V
JTAG_CONN_MODREV 0.90
CPLD_TDI
GBE_TRST_N
CPLD_TDO
GBE_TDOGBE_TDI
TRST_NSRST_N
TMS
TCKIOP_TDIIOP_TDO
NVRAM_32KX8_MOD
GLOBALS>>3.3V
REV 0.3
PBI_D<7..0>PBI_PCE_N
PBI_A<14..0>PBI_POE_NPBI_PWE_N
PCI EXPRESS X8
MISC
PERIPHERAL
JTAG
4-PCI-X
RS-232 UART>>+1_2V
PCI-X
I2C
7-POWER
SAS X8
HOT_SWAP
DDR2 400/533
5-PBI/GPIO/JTAG/I2C5-RS232/RESET/THERM5-NMI/HPI/RESET6-FILTERS/POWER
8-GROUND/NC
3-STORAGE/PCI-E2-SDRAM1-BLOCK/REV
8134x_MOD
>>+1_8VA>>+1_8V>>+3_3VGLOBALS:
>>+1_2VA>>+1_2VB
REV 0.80
DDR_
CKE<
1..0
>DD
R_OD
T<1.
.0>
DDR_
CB<7
..0>
DDR_
DQS_
N<8.
.0>
DDR_
MA<
15..0
>
DDR_
RAS_
NDD
R_CA
S_N
DDR_
CS_N
<1..0
>
DDR_
RESE
T_N
DDR_
CK_P
<2..0
>DD
R_CK
_N<2
..0>
DDR_
DM<8
..0>
DDR_
DQ<6
3..0
>
SDA<2..0>
SAS_RX_N<7..0>
SAS_TX_N<7..0>
NMI_N<1..0>
U_RTS_N<1..0>U_CTS_N<1..0>
PCI_XINT_N<7..0>PCI_CBE_N<7..0>
DDR_
WE_
N
DDR_
BA<2
..0>
SMBD
ATSM
BCLK
PE_R
EFCL
K_P
P_RS
T_N
PBI_A<24..0>
SL_TEST<31..0>
PCI_XCAPPCI_RSTOUT_N
PCI_PERR_NPCI_SERR_N
PCI_DEVSEL_NPCI_STOP_NPCI_TRDY_NPCI_IRDY_N
PCI_FRAME_NPCI_PAR
PCI_ACK64_NPCI_REQ64_N
PCI_PAR64PCI_M66EN
HS_ENUM_N
HS_LSTAT
PBI_POE_N
PBI_RSTOUT_N
SAS_TX_P<7..0>
SAS_RX_P<7..0>
SAS_STAT<7..0>SAS_ACT<7..0>
PE_R
_P<7
..0>
PBI_PWE_N
SL_TRST_N
THERMOSTAT_N
HS_FREQ<1..0>HS_LED_OUT
PE_R
EFCL
K_N
PE_T
_N<7
..0>
PE_T
_P<7
..0>
SL_TMSSL_TDOSL_TDISL_TCK
HPI_N
THERM_ALERT_N
U_TXD<1..0>U_RXD<1..0>
WARM_RST_N
PE_R
_N<7
..0>
PCI_GNT_N<3..0>
PCI_IDSELPCI_BMI
PCI_REQ_N<3..0>PCI_CLK_R<3..0>
PCI_AD<63..0>
PCI_CLKOUT_RPCI_CLKIN
DDR_
DQS_
P<8.
.0>
SCL<2..0>
GPIO<7..0>
PBI_D<15..0>
PBI_PCE_N<1..0>
LSB
OUT
OUT
RS232_DUAL_MOD
GLOBALS>>+3_3VREV 0.6
U_RTS_N<1..0>
U_TXD<1..0>
U_CTS_N<1..0>
U_RXD<1..0>SHDNEN_N
BUZZ
ER_S
O_M
OD
GLOB
ALS
>>3.
3VRE
V0.
05
BUZZ
ER_C
TRL
>>+3_3VGLOBALS
PCIX64_SM_SLOT_MOD
REV 0.31
PCI_IRDY_NPCI_TRDY_NPCI_STOP_N
PCI_FRAME_N
PCI_SERR_N
PCI_XCAP
PCI_XINTA_N
PCI_ACK64_N
PCI_XINTD_N
PCI_PAR
PCI_PAR64
PCI_GNT_NPCI_REQ_NPCI_CLKSLOT_IDSELPCI_AD<63..0>
PCI_XINTB_NPCI_XINTC_N
PCI_M66EN
PCI_CBE_N<7..0>
PCI_RSTOUT_NPCI_PERR_N
PCI_REQ64_N
PCI_DEVSEL_N
REV 0.6
SAS_CONN_X4_INT_MOD
GLOBAL>>3.3V
SAS_RX_N<3..0>SAS_TX_P<3..0>SAS_TX_N<3..0>SCLOCK
SDATAOUTSDATAIN
SAS_RX_P<3..0>
SLOAD
LSB
GLOBALS
GBE_82545GM_MODREV: 0.9
>>+3_3V
GBE_LAN_PWR_GOOD
PCI_CBE_N<7..0>
PCI_REQ64_NPCI_ACK64_N
PCI_FRAME_NPCI_IRDY_NPCI_TRDY_NPCI_STOP_N
PCI_RST_NPCI_PERR_NPCI_SERR_NPCI_DEVSEL_N
PCI_PME_N
PCI_AD<63..0>PCI_IDSELPCI_CLK
PCI_INTA_N
PCI_M66ENPCI_PAR64
PCI_PAR
PCI_REQ_NPCI_GNT_N
GBE_SDP7GBE_SDP6GBE_SDP1GBE_SDP0
GBE_SMBDAT
GBE_JTAG_RST_NGBE_JTAG_TMSGBE_JTAG_TDOGBE_JTAG_TDIGBE_JTAG_TCK
GBE_SMBCLKGBE_SMBALRT_N
REV 0.5
SAS_CONN_4X1_INT_MOD
SAS_TX_N<3..0>
SAS_RX_N<3..0>SAS_RX_P<3..0>
SAS_TX_P<3..0>
OUTOUT
OUT
OUT
SHORT PIN 6 TO GNDFOR BUFFER B->YSHORT PIN 6 TO VCCFOR INVERTER A->Y
SEL
AY
GND
VCC
B
A0A1A2
VSSSDASCL
WP
VCC
IN
A
GND YVC
C
B
A
GND YVC
C
B
MSB
MSB
MSB
MSB
LSBLSB
LSBLSB
DIMM_DDR2_TBBU_RA_MOD
GLOBALS
>>+3
.3V
>>+1
.8V_
Z>>
+1.8
V_B
REV 1.2
GPIO
<7>
GPIO
<6>
DDR_
S CL
DDR_
SDA
DDR_
SA<2
..0>
DDR_
DQ<6
3..0
>DD
R_CB
<7..0
>DD
R_DQ
S_P<
8..0
>DD
R_DQ
S_N<
8..0
>DD
R_DM
< 8..0
>DD
R_M
A<15
..0>
DDR_
BA<2
..0>
DDR_
RAS_
NDD
R_CA
S_N
DDR_
WE_
NDD
R_CS
_N<1
..0>
DDR_
CKE<
1..0
>DD
R_OD
T<1.
.0>
DDR_
RESE
T_N
DDR_
CK_P
<2..0
>DD
R_CK
_N<2
..0>
DDR_
MIS
C<3.
.0>
LSB
OUT
LSB
PCI_EXP_X8_EDGE_BPD_MODREV: 0.55
+3.3
V>>
+12V
>>
GLOBALS
+3.3
VAUX
>>
BP_D
ET_N
PE_T
_N[7
..0]
PE_R
_P[7
.. 0]
PE_T
_P[7
..0]
PE_R
EFCL
K_N
PE_R
EFCL
K_P
PE_R
_N[7
..0]
PE_S
MCL
K
PE_R
ST_N
PE_S
MDA
T
PE_W
AKE_
N
PE_T
CKPE
_TM
SPE
_TDO
PE_T
RST_
NPE
_TDI
MSB
LSB
OUT
OUT
OUT
>>+3_3VGLOBAL
REV 1.0
SGPIO_HD_LED_MOD
SAS_ACT<7..0> SDATAIN
SCLOCK
SDATAOUTSLOAD
SAS_STAT<7..0>
IN
Host Bus Adapter Schematics for Intel® 8134x I/O Processors 9
1.2V RAILS MUST TURN ON BEFORE OR EVEN WITH 1.8V RAILS1.2V RAILS MUST TURN OFF AFTER OR EVEN WITH 1.8V RAILS
THE LINEAR REGULATORS HAVE BEEN DEPOPULATED.THESE RESISTORS ARE POPULATED BECAUSE
CAN BE REMOVED WHEN B0 8134xSILICON IS AVAILABLE.
EDGE OF POK_1P8 TO MINIMIZE INRUSH CURRENT.IT CLOSES THE FET QUICKLY WHEN POK_1P8 IS GONE,TO MINIMIZE CURRENT DRAIN FROM THE BACKUP BATTERY.
POWER REGULATORS TOP VIEW
+1_8V WHEN THE 1.8V ENABLE
AND THEDDR2 TERMINATORS
SIGNAL IS NOT ASSERTED
THIS NFET DRAINS
PLACEMENT NOT CRITICALTHIS IS THE BATTERY BACKED+1_8V RAIL FOR THE DIMM
+1.8V_Z IS FOR TERMINATIONS
+1.8V FOR 8431x
8431x
8431x
SPC CAPS, CAN BE RUN AT 90% RATING
BULK DECOUPLING
THIS FET ISOLATES THE BATTERY BACKED
SEQUENCING REQUIREMENT:
WHEN +12V IS BELOW 10.1V.
THIS IS THE +1_8V RAILFOR
RAIL FROM THE NON-BATTERY BACKED RAIL
WHEN THE 1.8V ENABLE SIGNAL IS ASSERTED
CKE LATCH CIRCUIT ONLY REQUIRED FOR BATTERY BACKED MEMORY IMPLEMENTATIONS.
DRIVING THE 1P8V ENABLE INPUTS WITHTHE 1.2V POK SIGNALS FORCES 1.8V RAILS
WHEN +3_3V IS BELOW 2.7V.
AND TERMINATIONS CAN BE THE SAME RAIL
+1.8V_B IS FOR DIMM
THIS VOLTAGE SUPERVISOR PULLS POK_1P2 LOW
THIS VOLTAGE SUPERVISOR PULLS POK_1P2 LOW
TO POWER-UP AFTER THE 1.2V RAILS.
THIS CIRCUIT OPENS THE FET SLOWLY ON THE RISING
AN INVERTED AND NON-INVERTED COPY
TO DRIVE THE FET GATEOF POK_1P8 AT A 12V LEVEL
THESE TWO FETS CREATE
DRAIN SLOWLY, BUT DISABLE IT QUICKLYTHIS CIRCUIT WILL ENABLE THE +1_8V
1% VALUE USED FOR BOM CONSOLIDATION
ECO: ENABLES 64-BIT PCI CYCLES.
0603
0603
0603
0 5%CHIP
0 5%CHIP
0 5%
+1_2VA
+1_8VA
1K 16V10UF
1206
X5R
10%
10%
25V
0402
0.01
UFX7
R
+12V
FAN HEADER
100KNCP303LSN27T1
NCP303LSN27T1
+3_3V
13K
5%
1K5%
12V_VOLT_DET
+12V
1%35
.7K
1%
P_SY
NC
H_1
P 8_1
P2
+12V
RST_12V_N
POK_
1P2
74LVC2G08
+1_8V_B
5%
+12V
1%
+1_8V_B
74LVC2G08
74LVC2G32
+12V
+1_8V
5%
+12V 05%
100K
100K
+1_8V_B
+1_8V_Z
+12V
+1_8V
+3_3V
+1_2V
74LVC2G32
EN_1P2_BUCK
LED_
12V_
ON
DD
R_C
KE0_
DI S
ABLE
DDR_CKE<0>
DDR_CKE0_AND_RSTDDR_CKE_AND_RST
POK_1P8_N
ENABLE_1P8V
+3_3V
5%0
EMPTY0.1UF
EMPTY0.1UF
5%00 5%0 5%
+1_2VB
DD
R_C
KE1_
DIS
ABLE
+1_8V_B
DDR_CKE<1>
+1_8V
10K
5%
+12V
LED_GRN
PNP_3906 PNP_3906
+12V
+1_2VA
0.1U
F
10K
5%
N_FET
RST_3P3_N
POK_1P8
0805
5%1/
10W39
5%1K
5%1K
2N7002
10K
2N7002
0.1U
F
+12V
+3_3V
+1_8V_B
+1_2VB
EN_1P2_LIN
+1_2V
EMPTY
220UF
20%25V
EMPTY20%
220UF25V
EMPTY20%25V220UF
EMPTY
4V20%
150UF
EMPTY
4V20%
150UF
EMPTY
4V150UF
20%EMPTY
0
5%0
EMPTY
+12V_FAN
RST_3P3_N
1D3 1D3
2A8 2A82D7
RST_3P3_N
1C1
2N7002
2N7002
+1_8VA
5%
1C3
5%
+1_8V_B
1A41A7
PNP_3906
EMPTY
PCI_REQ64_N
PE_RST_B_N
2D7
+3_3V
+1_2VA
R4A1
Q6B3 5 6 7 8
4
123
R9A1
12
DS9A1
21
C2D11
2
C8C41
2
C1C101
2
C3D121
2
C8A91
2
C4A41
2
U7B11
2
48
7
U7B21
2
48
7R6
B21
2
R6B1
12
R8B101 2
Q6B1
3
1
2
Q6B2
3
1
2
R3D1
R6P3
C1C6
1
2
C1C7
1
2U7B25
6
48
3U7B15
6
48
3
Q7B1
1
3
2
Q7B2
1
3
2
R1C9
12
R1C1
01
2
R1C71 2
R6B31 2
D7B1
13
C6B1
1
2
R6B71 2
D6B1
13
C6B2
1
2
Q6B4
3
1
2
R1C81 2
R8N51 2
R6B5
12
R3D31 2
R6B4
12
R6B8
12
R6B6
12
Q6B5
3
1
2
U1C2
53
12C1C9 1 2
C1C8 1 2
U1C1
53
12
R4A21 2
R4A31 2
R4A41 2
L1C11 2
J1C2
12
Q2B1
1
3
2
R1B6
12
-700 5.00Tue Aug 15 09:39:15 2006
22
4
4
2A6 2A8
68
2
A
B
C
D
2 1345
D
C
B
A
8 6 5 3
MODIFIEDSHEET
4 1
DRAWING REVBOARD REV
7
7
A
B
VCC
GND Y
IN
REV 0.51VRG_1P2V_MOD
+1P2V_BUCK
POK_1P2SYNCOUT_1P2FSYNCIN_1P2
+VIN
EN_1P2_BUCK
VRG_1P8_MOD REV 0.52
+VINFSYNCIN_1P8
+1P8V_BUCKSYNCOUT_1P8
POK_1P8EN_1P8_BUCK
VRG_1P8LIMOD_NPREV 0.51EN_1P8_LIN
+VIN +1P8V_LIN
S1S2S3
G
D4D3D2D1
IN
IN B
E
C
PWR
GND
OUT
FB
VIN
GNDCD
NC
RST_N
VIN
GNDCD
NC
RST_N
G
S
D
G
S
D
B
E
C
B
E
C
IN
A
B
VCC
GND Y
A
GND YVC
C
B
G
S
D
G
S
D
A
GND YVC
C
B
VRG_1P2LIMOD_NPREV 0.5
EN_1P2_LIN+1P2V_LIN+VIN
Host Bus Adapter Schematics for Intel® 8134x I/O Processors 10
DIP SWITCHES
SWITCH #1 2 3
OFFON
ANYANYOFF
OFFONON
ANYONOFF
ANY PCI 33 MHZ MODEPCI 66MHZ MODEPCI-X 66MHZ MODEPCI-X 100/133MHZ MODEPCI MODE SWITCH IS FOR SYSTEM TEST PURPOSES ONLY.
PCI MODE SWITCH CAN FORCE THE PCI SLOT TO OPERATEAT A LOWER FREQUENCY OR IN PCI MODE.
MAXIMUM PCI BUS SPEED
3 POSITION SWITCH - PCI MODE
MADE PCIXM1_100_N A RESISTOR OPTION
ALL OTHER DEVICE FUNCTION SELECT CONFIGS RESERVED6 OFF, 7 OFF, 8 OFF = ATU: 0 PORTS, TPMI: 8 PORTS6 OFF, 7 ON, 8 ON = ATU: 4 PORTS, TPMI: 4 PORTS
PCI CONFIGURATION DISABLED (RETRY)
FIRMWARE TIMER ENABLED
16 BIT FLASH INTERFACE
X0 CPU ACTIVE AFTER RESET
400 MHZ DDRII SDRAM INTERFACEX1 CPU ACTIVE AFTER RESET
OFF
6 ON, 7 ON, 8 ON = ATU: 8 PORTS, TPMI: 0 PORTS6 ON, 7 ON, 8 OFF = ATU: 7 PORTS, TPMI: 1 PORT6 ON, 7 OFF, 8 ON = ATU: 6 PORTS, TPMI: 2 PORTS
PCI CONFIGURATION ENABLED
533 MHZ DDRII SDRAM INTERFACEHOLD CPU X1 IN RESET
8 BIT FLASH INTERFACE
HOLD CPU X0 IN RESET
ON10 POSITION SWITCH
SWITCH SETTINGS
7
5
34
21
6
SWITCH #
8
JUMPER
109
RAID DISABLEDINSTALLED EMPTY
RAID ENABLED
FIRMWARE TIMER DISABLEDRESERVED DEFAULT
ECO ADDED DEV_FUNC_SEL2 TO SWITCH AND
COMPLEX MODE WHEN PLUGGED INTO INTELBACKPLANE.
BACKPLANE DETECT PUTS PCIE CARD IN ROOTECO: ADDED BACKPLANE DETECT RESISTOR.
BOOT_WIDTH_8_NCONFIG_CYCLE_EN_N
DEV_FUNC_SEL1DEV_FUNC_SEL2
789
19
5%
5%4.7K
EMPTY
SW_DIP_3
SETTING=000
PCI_XCAP
PCI_M66EN
17EMPTYEMPTYEMPTY
SETTING=EMPTYHDR_1X2_TH
PNP_
3906
MEM_FREQ_400_533_NHOLD_X1_IN_RST_NHOLD_X0_IN_RST_N
PCI_XCAP_66
PBI_PWE_N
PBI_POE_N
CONTROLLER_ONLY_N
PBI_PCE_N<1..0>
4.7K 5%
01
23
1110
161514 SW_DIP_1013
5%EMPTY 4.7K4.7K 5%EMPTY
4.7K 5%
EMPTY 4.7K 5%5%4.7KEMPTY5%4.7K5%4.7K
4.7K 5%
EMPTY 4.7K 5%EMPTY 4.7K 5%
22
43
10K
5%
21
0
5%4.7K4.7K
5%4.7K5%4.7K
5%4.7K5%4.7K
5%4.7K
4.7K 5%
4.7K 5%
5%4.7K
10K 5%
1B7
+3_3V
SETTING=0000111110 (LSB-MSB)
FW_TIMER_OFF_NDEV_FUNC_SEL0
5%4.7K4.7K 5%
12
12
PBI_A<24..0>
1C8
1A4
1D8 1C6
BP_DET_N
1C6
1C6
1C6
1B3
1C2
R5P7
12
SW5D1
10 11
1 202 193 184 175 166 157 148 139 12
J7C1
1 2
Q5D1
1
32
SW5A1
1 62 53 4
R5L11 2
R5D31 2
R2N11 2
R5P61 2
R5P31 2
R5P51 2
R5P41 2
R5P11 2
R5P21 2
R4P31 2
R4P21 2
R2N71 2
R2N51 2
R2N31 2
R2N21 2
R2N121 2
R2N101 2
R2N91 2
R2N41 2
R3N51 2
R2P11 2
R2N181 2
R1P11 2
R4P41 2
R3D51 2
-700 5.00Tue Aug 15 09:39:16 2006
68
2
A
B
C
D
2 1345
D
C
B
A
8 6 5 3
MODIFIEDSHEET
4 1
DRAWING REVBOARD REV
7
7
B
E C
IN
IN
IN
IN
IN
IN
IN
N O
2A1A
7A
5A6A
4A3A
1B2B3B
7B8B9B
10B10A9A8A
4B5B6B
N O
1B2B3B
2A3A
1A
OUT
Host Bus Adapter Schematics for Intel® 8134x I/O Processors 11
8 - GROUND/NO CONNECTS
0.5 - SEP 29:
0.56 OCT 28:0.57 OCT 29:0.58 NOV 1:
0.60 DEC 9:0.59 NOV 10:
4 - PCI-X BUS5 - PERIPHERAL BUS/MISC6 - POWER/FILTERS
0.52- OCT 05:0.51- OCT 01:
0.3 - SEP 18:
REVISIONS
0.54 OCT 12:0.53- OCT 12:
3 - STORAGE/PCI-EXPRESS
0.55 OCT 19:
8134x MODULE CONTENTS
DDR_VREF RESISTORS
RBIAS RESISTORS
PCI-X CAL RESISTORS
PERIPHERAL BUS
I2C/MISC BUSSES
DDR BUS
PCI-E BUS
PCI-E CAL RESISTOR
PCI-X BUS
STORAGE (SAS) BUS
125MHZ SAS OSC
THERMAL SENSOR
I2C PULL-UPS
8134x
+1_2VB+1_2VA+1_2V+1_8VA+1_8V+3_3V
2 - SDRAM
7 - POWER
8134x MODULE
8134x
DIAGRAM OF MODULE CONTENTS
0.70 DEC 14:
PLL FILTERS
0.4 - SEP 29:
0.75 OCT 14:
0.74 APR 11:
0.73 MAR 08:0.72 FEB 28:
0.76 DEC 23:
0.80 FEB 10:
0.71 JAN 7:
-600 5.00Fri Feb 10 08:54:38 2006
68
2
A
B
C
D
2 1345
D
C
B
A
8 6 5 3
MODIFIEDSHEET
4 1
DRAWING REVBOARD REV
7
7
PINOUT CHANGES INCORPORATED
RELEASE FOR CHECKPCI_REQ64 -> PCI_REQ64_NMOST OF THE BLOCK REVIEW FEEDBACK INC.FIX REQ0 AND GNT0 DIRECTIONSRESIZED MODULE SYMBOL
CHANGED DDR_MCAL1 SIZE TO 0402ADDED PULLUPS ON SMB SIGNALS AND WARM_RST_N
ADDED SL_TEST <31..0>
UPGRADED IOP TO A1 IPN
MODIFIED SL PART FOR 800MHZ B0 VERSION
ECO8: RENAMED VECTORED NETS TO HAVE VECTOR LASTRENAMED PLL_VCC13P3_L_X NET TO PLL_VCC3P3_L_XCHANGED 14 DECOUPLING CAPS TO EMPTY (NOT POPULATED)
DEPOPULATED P_CLKIN CAPADDED PULL-DOWN RESISTOR OPTION TO PUR1 PIN
RENAMED S_CLK_N/P TO S_CLK0_N/P, SWAPPED ASSIGNMENTS OF PINSH15 WITH H20 (S_CLK0_N WITH VSS) AND H16 WITH H21 (S_CLK0_P WITH VSS)
CHANGED 4.7NH IND TO -024ADDED PCI_CLKOUT_R AND PCI_CLKINMOVED P_RST_N PIN, FIXED TABLE OF CONTENTSADDED 5PF CAP TO PCI_CLKINGROUNDED VSSPLLS0 AND VSSPLLS1CHANGED PIN AN8 TO PUR1CHANGED I2C PULLUPS TO 3.3K
ADJUSTED DECOUPLING TO NEW RECOMMENDATIONS
REMOVED SOME DECOUPLING, CHANGED SOME TO 0603
PORT NAME CHANGES, CORRECT DDR CLOCK SWAPPING
Host Bus Adapter Schematics for Intel® 8134x I/O Processors 12
NOTE: MA[15:14] INCLUDED FOR BUS WIDTH MATCHING TO DIMMTHIS IS A CONCEPT HEIRARCHICAL ISSUE ONLY
KEEP DDR_VREF AS SHORT AS POSSIBLE
04021%
1/16W24.9
0.1U
F
0.1UF
0.1UF
100 1%
DDR_CB<7..0>
1%0402
0
3
12
456789
10
0
21
01
0 11
1312
161514
171819
2120
2322
2526
24
2827
293031
343332
3536
393837
4140
444342
4645
47
4948
5150
52
01
0
1
2
3
2
3
5453
5657
55
5958
626160
63
4
5
4
5
66
7
8
7
8
0
1
2
0
1
2
1
0
23456
012345678
01
01234567
910111213
DDR_CKE<1..0>
DDR_CK_P<2..0>DDR_CK_N<2..0>
1%
7
1
DDR_MA<15..0>
DDR_CS_N<1..0>
301
8
1/16W
+1_8V
DDR_BA<2..0>
DDR_DQ<63..0>
DDR_DQS_P<8..0>
DDR_DQS_N<8..0>
+1_8V
DDR_ODT<1..0>
DDR_DM<8..0>
100
8134x
2 of 13
DDR_MCAL0DDR_MCAL1
DDR_VREF_SLDDR_RESET_N
DDR_CAS_N
DDR_WE_N
DDR_RAS_N
-600 5.00-600-600 5.005.00Fri Feb 10 08:52:07 2006Fri Feb 10 08:52:07 2006Fri Feb 10 08:52:07 2006Fri Feb 10 08:52:07 2006
1 2C6N13
1 2C6N14
1 2R6N3
1 2R6P2
1
2
C6P
1
1C5
1C5
1C5
1C5
1C5
1C5
1C5
1C5
1C4
1C5
1C4
1C4
1C5
1C4
1C4
U34U35
T33AJ33AK33
H33
AT35AT34
W34V34
AA35AA34
AH33
AG33AF33
AE33AC33
AB33
Y34AA33
Y33
F33J33
AT33AR33
V33
W35G36
P36G35
AF36P35
AF35
AN35AP37
V36V37
K33
AP33AN33
L33N33G33
P33
Y36AA36
U36
Y37U37
AA37
AM33
R33U33
W37W36
H36E36D37
AL35AM35AL37AM37AD35AE35AD37AE37M35N35M37N37E35F35E37F37
P37L36K37T37R36M36L37H34G34D35C35J35H35E34D34H37G37D36C36J37
R37
AG35AD34AC34AG37AF37AC36AB37AH37AG36AD36AC37R34P34L35K35T35R35M34L34
AH35
AN36AN37
AK34
AP35AL34
AJ35AR35
AK35
AP34AN34
AK36AJ37AR36AP36AL36AK37AG34AF34AC35AB35
U4B1
1 2R6N11 2R6N2
1C5
68
2
A
B
C
D
2 1345
D
C
B
A
8 6 5 3
MODIFIEDSHEET
4 1
DRAWING REVBOARD REV
7
7
IO
SDRAM
DQ19DQ18DQ17DQ16DQ15DQ14DQ13DQ12DQ11DQ10
DQ1DQ0
DQ2
DQ4DQ3
DQ6DQ5
DQ7
DQ9DQ8
DQ20
DQ39DQ38DQ37DQ36DQ35DQ34DQ33DQ32DQ31DQ30DQ29DQ28DQ27DQ26DQ25DQ24DQ23DQ22DQ21
DQ40
DQ60DQ59DQ58DQ57DQ56DQ55DQ54DQ53DQ52DQ51DQ50DQ49DQ48DQ47DQ46DQ45DQ44DQ43DQ42DQ41
DQS7_NDQS7
DQS6_NDQS6
DQS5_NDQS5
DQS4_NDQS4
DQS3_NDQS3
DQS2_NDQS2
DQS1_NDQS1
DQS0_NDQS0
DQ63DQ62DQ61
DQS8DQS8_N
BA1BA0
BA2
CB0
CB2CB1
CB3CB4CB5
RAS_N
CS1_NC 0_NWE_N
CKE0CKE1
CAS_N
CB6CB7
DM1DM0
DM2
DM4DM3
DM6DM5
DM7DM8
MA0
M_RST_NM_VREF
ODT0ODT1
MA1
MA3MA2
MA4
MA6MA5
MA8MA7
MA9
M_CK_N1M_CK1M_CK_N0M_CK0
M_CAL1M_CAL0
MA13MA12MA11MA10
M_CK_N2M_CK2
OUTOUT
OUT
OUT
OUT
OUT
OUT
OUTOUT
OUTOUT
OUT
OUT
OUT
IO
8134x SDRAM
Host Bus Adapter Schematics for Intel® 8134x I/O Processors 13
NOTE PIN CHANGE REV 0.74
CONNECT SAS_RBIAS<N> RESISTOR GND PINS AND SAS_RBIAS_SENSE GND SIGNALS USING A SINGLE VIAISOLATE SAS_RBIAS_SENSE<N> (GND) SIGNALS FROM THE GND PLANE AT 8134x
KEEP SHORT AND CLOSE TO 8134x
OUTPUTS
BIDIRECTIONALS
1
SAS_ACT<7..0>
2
32
SAS_RX_N<7..0>
44
1PE_T_N<7..0>PE_T_P<7..0>
67
SAS_RX_P<7..0>
SAS_TX_N<7..0>
0
4
55
SAS_RBIAS_SENSE<1..0>
4
SAS_RBIAS<1..0> 01%
6.49K 1%
6
0
7
5
1
33
6
SAS_TX_P<7..0>
1
PE_R_P<7..0>
54
10
6
2
7
4
01
0
0
10
1
1
22
6
3
1
4
01
5
3
5
1
67
0
0
1
2
3
4
5
0
2
3
6
7
5
7
6
1
0
2
3
6
7
0
2
3
4
5
6
7
77
4
5
PE_R_N<7..0>
1%1.4K
6.49K
SAS_STAT<7..0>
32
7 of 13
8134x
SAS_CLK_PSAS_CLK_N
6 of 13
PE_CAL_NPE_CAL_P
PE_REFCLK_NPE_REFCLK_P
-700 5.00Fri Feb 10 08:52:08 2006
1A4
1A4
1A5
1A5
1 2R4D1
1A5
1A5
1C4
H21
D26E26
F27B26E25
F26C27
A25
B17A17B13A13B16A16B14A14B23A23B19A19B22A22B20A20
E16E21
E15E20
D25F25A26E27C25B25A27C26
D17C17D13C13D16C16D14C14D23C23D19C19D22C22D20C20
H20
U4B1
AT24AU24AT23AU23AT21AU21AT20AU20AT18AU18AT17AU17AT15AU15AT14AU14
AN19AN20
AK19AK20
AP24AR24AP23AR23AP21AR21AP20AR20AP18AR18AP17AR17AP15AR15AP14AR14
U4B1
1C4
1C4
1C4
1C4
1C4
1 2R4A71 2R4A8
68
2
A
B
C
D
2 1345
D
C
B
A
8 6 5 3
MODIFIEDSHEET
4 1
DRAWING REVBOARD REV
7
7
OUT
OUT
OUT
IN
IN
OSC_125M_MODGLOBAL
REV 0.9>>+3_3V
CLK_PCLK_N
PCI-EXPRESS
PETP0PETN0PETP1PETN1PETP2PETN2PETP3PETN3PETP4PETN4PETP5PETN5PETP6PETN6PETP7PETN7
REFCLKPREFCLKN
PE_CALPPE_CALN
PERP0PERN0PERP1PERN1PERP2PERN2PERP3PERN3PERP4PERN4PERP5PERN5PERP6PERN6PERP7PERN7
STORAGE
S_CLK0_N
S_TXP0S_TXN0S_TXP1S_TXN1S_TXP2S_TXN2S_TXP3S_TXN3S_TXP4S_TXN4S_TXP5S_TXN5S_TXP6S_TXN6S_TXP7S_TXN7
S_ACT0S_ACT1S_ACT2S_ACT3S_ACT4S_ACT5S_ACT6S_ACT7
RBIAS0RBIAS1
RBIAS_SENSE0RBIAS_SENSE1
S_RXP0S_RXN0S_RXP1S_RXN1S_RXP2S_RXN2S_RXP3S_RXN3S_RXP4S_RXN4S_RXP5S_RXN5S_RXP6S_RXN6S_RXP7S_RXN7
S_STAT0
S_STAT5S_STAT4
S_STAT1S_STAT2S_STAT3
S_STAT6S_STAT7
S_CLK0_P
IO
OUTOUT
ININ
ININ
8134x
8134x STORAGE / PCI-EXPRESS
Host Bus Adapter Schematics for Intel® 8134x I/O Processors 14
MATCH PCI_CLK<3..0> AND PCI_CLKOUT
THESE RESISTORS NOT NEEDED FOR PCI-X HBA'S
INPUTS
PCI_CLK_R<3..0> ARE NOT ACTIVE FOR PCI-X BASED SYSTEMSCONNECT PCI_CLKIN TO EDGE CONNECTOR FOR PCI-X BASED SYSTEMSTIE PCI_CLKOUT_R TO PCI_CLKIN FOR PCIE BASED SYSTEMS.PCI_CLK_R NETS TO SLOT MUST BE 2.5 INCH SHORTERMATCH PCI_CLK_R<3..0> AND PCI_CLKIN
PLACE CLOSE TO BALL. REMOVE FOR B0 SILICON.
BIDIRECTIONALS
47
26
7
23
012
10
11
10
2
1
12345678910
1213141516171819202122232425
2728
3031323334353637383940414243444546
48
50515253545556575859
616263
49
60
0
3
2
23456
0
2
45
12
0
6
1
3
PCI_CAL<2..0> 012
29
22.1 1%121 1%22.1 1%
0
3
1
0
3
23
PCI_AD<63..0>
PCI_XINT_N<7..0>
PCI_CBE_N<7..0>
0 PCI_REQ_N<3..0>
PCI_GNT_N<3..0>
PCI_CLK_R<3..0>
PCI_CLKOUT_RPCI_CLKIN
1%
1%1%1%27.4
27.427.4
27.427.4
7
11%PCI_CLK<3..0>
5.6PFEMPTY
5 of 13
PCI_RSTOUT_N
PCI_DEVSEL_N
PCI_FRAME_N
PCI_XCAP
PCI_BMI
PCI_PAR
PCI_IRDY_NPCI_TRDY_N
PCI_PERR_NPCI_SERR_N
PCI_STOP_N
PCI_ACK64_NPCI_REQ64_NPCI_PAR64PCI_IDSELPCI_M66EN
PCI_CLKOUT
-600 5.00-600 5.00-600 5.00Fri Feb 10 08:52:08 2006Fri Feb 10 08:52:08 2006Fri Feb 10 08:52:08 2006Fri Feb 10 08:52:08 2006
1B4
1B4
1B4
1B4
1B4
1B4
1C4
1B4
1C4
1B4
1B4
1B4
1B4
1B4
1B4
1B4
1B4
1B4
1B4
1B4
1 2R3A81 2R3B1
1 2R7M2
1B4
F1
R3
R4
R2
F5F4
F3D3
U4
P1T5
R1T1
T3
AB1AB3AC5N5V1
AB5AC1AC4AC2L1P2U2W3
E9C8C9D9B9A8
G3
A9B8
G5H3J4J5
H4
C3
H1J1
D1D2B3
E1C2
AC3AD3AD1AD4AD2AE3AE1AE5AF1AF4AF2AF5AF3AG3AG1AG4AG2AH3AH1AH5AJ1AJ4AJ2AJ5AJ3AK3AK1AK4AK2AL3AL1AL5
K5L4K1L3K3M5L2M4M3N3M2P4M1P3N1R5U3U1V5V3V4V2W5Y1Y2Y4Y3Y5
AA1AA3AA2AA4 U4B1
1 2R7L9
1 2R7M91 2R7M101 2R7M51 2R7M4
1B4
1B4
1 2C7L3
68
2
A
B
C
D
2 1345
D
C
B
A
8 6 5 3
MODIFIEDSHEET
4 1
DRAWING REVBOARD REV
7
7
INOUT
PCI-X
P_AD0P_AD1P_AD2P_AD3P_AD4P_AD5P_AD6P_AD7P_AD8P_AD9P_AD10P_AD11P_AD12P_AD13P_AD14P_AD15P_AD16P_AD17P_AD18P_AD19P_AD20P_AD21P_AD22P_AD23P_AD24P_AD25P_AD26P_AD27P_AD28P_AD29P_AD30P_AD31P_AD32P_AD33P_AD34P_AD35P_AD36P_AD37P_AD38P_AD39P_AD40P_AD41P_AD42P_AD43P_AD44P_AD45P_AD46P_AD47P_AD48P_AD49P_AD50P_AD51P_AD52P_AD53P_AD54P_AD55P_AD56P_AD57P_AD58P_AD59P_AD60P_AD61P_AD62P_AD63
P_CLKO0P_CLKO1
P_CLKO3P_CLKOUT
P_CLKIN
P_REQ0_NP_REQ1_N
P_CLKO2
P_REQ3_N
P_GNT0_NP_GNT1_NP_GNT2_NP_GNT3_N
XINT0_NXINT1_N
P_REQ2_N
XINT2_NXINT3_NXINT4_NXINT5_NXINT6_NXINT7_N
P_CBE0_NP_CBE1_NP_CBE2_NP_CBE3_NP_CBE4_NP_CBE5_NP_CBE6_NP_CBE7_N
P_M66ENP_IDSELP_PAR64
P_REQ64_NP_ACK64_N
P_STOP_N
P_ ER R_NP_PERR_N
P_TRDY_NP_IRDY_N
P_PAR
P_CAL2P_CAL1
P_BMIP_CAL0
P_PCIXCAP
P_FRAME_N
P_DEVSEL_N
P_RSTOUT_N
IN
OUT
OUTIOIOIOIOIOIOIOIOIOIOIOININ
IO
IO
OUT
OUT
IN
IO
8134x
8134x PCI-X BUS
Host Bus Adapter Schematics for Intel® 8134x I/O Processors 15
THERMOSTAT_N CAN BE USED TO CONTROL A FAN OR THROTTLE A CPU CLOCK
THERM_ALERT CAN BE USED TO GENERATE AN INTERRUPT
AS WELL AS THERMAL DIODE ATTACHEMENT.PLACE FOR MONITORING AMBIANT BOARD AIR
KEEP THERMDA AND THERMDC < 6 INCHESROUTE THERMDA AND THERMDC TOGETHER WITH GROUND GUARD TRACES ON EACH SIDEKEEP SWITCHING SIGNALS AWAY FROM THERMDA AND THERMDC
THERM_ADM1032ARM HAS INTERNAL THERMOMETER
P8134x ERIPHERAL BUS / MISC
SCL<2..0>NMI_N<1..0>
HS_FREQ<1..0>
HPI_N
5%
6
1514
0
2
456789
111213141516
181920212223
01
6789
10111213
01
12345
7
234
PBI_D<15..0>
1
PBI_PCE_N<1..0>
0
3
1
10
5
24
0
0
012
012
00
1
2
1
00
00
U_CTS_N<1..0>U_RTS_N<1..0>
U_RXD<1..0>U_TXD<1..0>
110K
10K
1K
GPIO<7..0>
THERM_ADM1032ARM
THERM_ALERT_N
5%
0.1UF
THERMOSTAT_N
SDA<2..0>
+3_3V
+3_3V
+3_3V
+3_3V
PBI_A<24..0>
+3_3V
2
3.3K 3.3K5% 5%
+3_3V
5%
+3_3V
+3_3V
SMBDATSMBCLK
11
11
5%3.3K5%3.3K5%3.3K5%3.3K5%3.3K5%3.3K
WARM_RST_N
17
4.7K 5%5%4.7K
EMPTY
1 of 13
PBI_POE_NPBI_PWE_N
PBI_RSTOUT_N
3 of 13
SL_TCKSL_TDISL_TDOSL_TMSSL_TRST_N
PUR1P_RST_N
THERMDC
HS_ENUM_N
HS_LED_OUTHS_LSTAT
THERMDA
-700 5.00Fri Feb 10 08:52:09 2006
1B5
1B5
1B5
1A5
1B5
1B5
1B5
1B5
1B5
AM1
AR9AU10
AU9AR7AP6AR6
AT11AR11AN10AP11AU11
AR3
AN7
AR2
AU7AT6AT5AU5AU8AU6AT9AP9AP8
AT8
AP2
AR4AR5
AN2AN1AT4AP5AM5AP3AN3AP1AM2AN6
AN4
AM4AM3
AR10AN11
AR8
AT3AU4
U4B1
B5B6A6A5
B4C5C4A4
AT29AR28AN29AR29AN28AP29
AU29AU28
AR31AU30AR30AT30AU31
AN8F2E4
C7
V28
A10A11C10B11E10D11E11
A7E6D6E8C6
D8E7
V29
C11
U4B1
432
56
87
1
U4D1
1B5
1B5
1 2R5D1
1 2R4D4
1 2C5D1
21
R3A
7
1 2R3N4
1 2R3N1
1 2R7N4
1 2R7N5
R9C6R2N14
R2P2R9C5
R2N16R3P2
1C5
1B5
1B5
1B5
1B5
1B5
1A4
1B5
1C4
1B5
1B5
1B5
1C5
1C5
1A4
1A4
68
2
A
B
C
D
2 1345
D
C
B
A
8 6 5 3
MODIFIEDSHEET
4 1
DRAWING REVBOARD REV
7
7
IOIO
IOIO
IO
INININ
OUT
IOIO
ININ
IO
OUT
OUT
OUTOUT
OUT
OUT
OUT
VDDSDATASCLK
ALERT_NGND
D_PD_N
THERM_N
MISC
GPIO7
THERMDA
NMI1_NNMI0_N
HS_LSTATHS_LED_OUTHS_FREQ1HS_FREQ0HS_ENUM_N
GPIO6GPIO5GPIO4GPIO3GPIO2GPIO1GPIO0
THERMDC
HPI_N
WARM_RST_NP_RST_NPUR1
TRST_NTMSTDOTDITCK
SMBDATSMBCLK
SDA2SCL2SDA1SCL1SDA0SCL0
U1_CTS_NU1_RTS_N
U1_RXDU1_TXD
U0_CTS_NU0_RTS_N
U0_RXDU0_TXD
PERIPHERAL
D1D0
PB_RSTOUT_N
PCE1_NPCE0_N
PWE_NPOE_N
D2
D15D14D13D12D11D10
D9D8D7D6
D4D3
D5
A1
A10A9A8A7A6A5A4A3A2
A0
A11
A23A22A21A20A19A18A17A16A15A14A13A12
A24
OUT
OUT
IN
IN
OUT
ININ
ININ
8134x
8134x
Host Bus Adapter Schematics for Intel® 8134x I/O Processors 16
VCC3P3 REQUIRES >10UF, <150PH, <1MOHM
VCC1P8 REQUIRES >10UF, <150MH, <1MOHM
8134x POWER / FILTERS
VCC1P8HS REQUIRES >5UF, <150PH, <1MOHM
VCC1P2APR REQUIRES >20UF, <150MH, <1MOHM
VCC1P2HS REQUIRES >5UF, <150PH, <3MOHM
4.7UH
PLL_VCC1P2_L_P
20%22UF
X5R
X5R 6.3V
20%22UF
PLL_VCC1P2_L_1
PLL_VCC1P2_L_D
4.7UH
4.7UH
120NH PLL_VCC1P2_L_0
+1_2VA
+1_8VA
+1_8VA
+3_3V
+3_3V
+1_8V
+1_8V
+1_8VA
+1_8VA
+1_2VA
+1_2VA
+1_2VB
+1_8V
+3_3V
+3_3V
+1_2VB
+1_2VA
+3_3V
+1_2V
+1_2V
+1_2V
+1_2V
1/10W
1%1/10W
06030.51
1/10W
20%080522UF
6.3V
20%080522UF
6.3V
0805 6.3V
080522UF
120NH
6.3V
1/10W0.1 1%
06031%
06030.51 1%
1%
06030.51
1/10W0.1
0603
X5R
1UF
1UF
1UF
1UF
1UF
1UF
4.7U
F
4.7U
F
4.7U
F
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
4.7U
F
4.7U
F
4.7U
F
1UF
1UF
1UF
1UF
1UF
1UF
1UF
4.7U
F
1UF
1UF
1UF
1UF
1UF
4.7U
F1U
F
1UF
1UF
1UF
1UF
1UF
1UF
X5R
X5R
0805
20%
4.7U
F
+1_2VA
+1_2VB
1UF
1UF
4.7U
F
4.7U
F
PLL_VCC3P3_L_X
8 of 13
PLL_VSS3P3_XPLL_VCC3P3_X
PLL_VSS1P2_PPLL_VCC1P2_P
PLL_VSS1P2_DPLL_VCC1P2_D
PLL_VCC1P2_1
PLL_VCC1P2_0
11 of 13
-600 5.00-600 5.00-600 5.00Fri Feb 10 08:52:09 2006Fri Feb 10 08:52:09 2006Fri Feb 10 08:52:09 2006Fri Feb 10 08:52:09 2006
1
2
C3D
2
1
2
C3D
7
1
2
C4A
20
1
2
C4D
2
1
2
C4A
13
AU25AU22AU19AU16AU13AT25AT22AT19AT16AT13AR25AR22AR19AR16AR13AP25AP22AP19AP16AP13
G17G14F17F13E14E12
D24D21D18D15D12C24C21C18C15C12B24B21B18B15B12A24A21A18A15A12
AM24AM23AM22AM21AM18AM17AM16AM15
AU26AT26AR26AP26AN26AN25AN24AN23AN22AN21AN18AN17AM26AM25
AN16AN15AN14AN13AM14AM13
G13G12F14F12E17E13
G19G18F19F18E19E18
G24G23G22F24F23F22E24E23E22
U29Y29
N11P11
AC29AD29
J16J15
J21J20
U4B11 2R4A5
1 2R4A6
1 2R5C1
1 2R7L8
1 2R5B1
1
2
C4A
23
1
2
C4D
11
1
2
C4D
7
1
2
C4A
12
1
2
C3A
11
1
2
C3A
12
1
2
C4A
21
1
2
C4A
16
1
2
C4D
15
1
2
C4D
6
Y6U6U5P6P5M6L6L5H6H5AK6AK5AJ6AG6AG5AF6AD6AD5AC6AA6AA5
Y32W32V32U32T32R32P32N32M32L32K32J32H32AU32AT32AR32AP32AN32AM32AL32AK32AJ32AH32AG32AF32AE32AD32AC32AB32AA32
W6V6T6R6N6K6
G6
G31
G29
G26
F9
F6
F11
AM9AM8AM7AM6
AM31AM30AM29AM28AM11AM10
AL6AH6AE6AB6
J6
G32
G30
G28G27
G25
F8F7
F32
F10E5
AP30AN5
AN31AN30
U4B11 2L4A2
1 2L4A3
1 2L5C1
1 2L7L1
1 2L5B1
21C4A3
21C4A9
21C5C1
21C7M1
21C5B1
1
2
C5M
3
1
2
C5M
2
1
2
C4D
17
1
2
C4D
14
1
2
C5M
4
1
2
C6P
3
1
2
C4D
12
1
2
C4D
8
1
2
C4D
3
1
2
C5M
1
1
2
C6P
5
1
2
C4D
13
1
2
C4D
16
1
2
C4A
17
1
2
C3D
6
1
2
C4A
19
1
2
C4A
15
1
2
C4D
10
1
2
C4A
22
1
2
C4D
1
1
2
C6P
4
1
2
C4D
4
1
2
C4D
9
1
2
C6P
2
1
2
C6M
2
1
2
C6M
3
1
2
C4A
18
1
2
C3A
9
1
2
C4A
10
1
2
C4A
14
1
2
C4A
5
1
2
C3D
9
68
2
A
B
C
D
2 1345
D
C
B
A
8 6 5 3
MODIFIEDSHEET
4 1
DRAWING REVBOARD REV
7
7
POWER
VCC3P3_14VCC3P3_15VCC3P3_16VCC3P3_17VCC3P3_18VCC3P3_19
VCC3P3_21
VCC3P3_23VCC3P3_24
VCC3P3_26
VCC3P3_28VCC3P3_29
VCC3P3_31
VCC3P3_33
VCC3P3_35
VCC3P3_0VCC3P3_1VCC3P3_2VCC3P3_3VCC3P3_4VCC3P3_5VCC3P3_6VCC3P3_7VCC3P3_8VCC3P3_9VCC3P3_10VCC3P3_11VCC3P3_12VCC3P3_13
VCC3P3_20
VCC3P3_22
VCC3P3_25
VCC3P3_27
VCC3P3_30
VCC3P3_32
VCC3P3_34
VCC3P3_36VCC3P3_37VCC3P3_38VCC3P3_39VCC3P3_40VCC3P3_41
VCC1P8_0VCC1P8_1VCC1P8_2VCC1P8_3VCC1P8_4VCC1P8_5VCC1P8_6VCC1P8_7VCC1P8_8VCC1P8_9
VCC1P8_10VCC1P8_11VCC1P8_12VCC1P8_13VCC1P8_14VCC1P8_15VCC1P8_16VCC1P8_17VCC1P8_18VCC1P8_19VCC1P8_20VCC1P8_21VCC1P8_22VCC1P8_23VCC1P8_24VCC1P8_25VCC1P8_26VCC1P8_27VCC1P8_28VCC1P8_29
VCCVIO_0VCCVIO_1VCCVIO_2VCCVIO_3VCCVIO_4VCCVIO_5VCCVIO_6VCCVIO_7VCCVIO_8VCCVIO_9
VCCVIO_10VCCVIO_11VCCVIO_12VCCVIO_13VCCVIO_14VCCVIO_15VCCVIO_16VCCVIO_17VCCVIO_18VCCVIO_19VCCVIO_20
POWER_PLLS
VCC1P2PLLS0VSSPLLS0
VCC1P2PLLS1VSSPLLS1
VCC1P2PLLDVSSPLLD
VCC1P2PLLPVSSPLLP
VCC3P3PLLXVSSPLLX
VCC1P2AS0VCC1P2AS1VCC1P2AS2VCC1P2AS3VCC1P2AS4VCC1P2AS5VCC1P2AS6VCC1P2AS7VCC1P2AS8
VCC1P8S0VCC1P8S1VCC1P8S2VCC1P8S3VCC1P8S4VCC1P8S5
VCC1P2DS0VCC1P2DS1VCC1P2DS2VCC1P2DS3VCC1P2DS4VCC1P2DS5
VCC1P2E0VCC1P2E1VCC1P2E2VCC1P2E3VCC1P2E4VCC1P2E5
VCC1P8E0VCC1P8E1VCC1P8E2VCC1P8E3VCC1P8E4VCC1P8E5VCC1P8E6VCC1P8E7VCC1P8E8VCC1P8E9
VCC1P8E10VCC1P8E11VCC1P8E12VCC1P8E13
VCC1P2AE0VCC1P2AE1VCC1P2AE2VCC1P2AE3VCC1P2AE4VCC1P2AE5VCC1P2AE6VCC1P2AE7
VSSAS0VSSAS1VSSAS2VSSAS3VSSAS4VSSAS5VSSAS6VSSAS7VSSAS8VSSAS9VSSAS10VSSAS11VSSAS12VSSAS13VSSAS14VSSAS15VSSAS16VSSAS17VSSAS18VSSAS19
VSSDS0VSSDS1VSSDS2VSSDS3VSSDS4VSSDS5
VSSE0VSSE1VSSE2VSSE3VSSE4VSSE5VSSE6VSSE7VSSE8VSSE9VSSE10VSSE11VSSE12VSSE13VSSE14VSSE15VSSE16VSSE17VSSE18VSSE19
8134x
8134x
Host Bus Adapter Schematics for Intel® 8134x I/O Processors 17
VCC1P2X REQUIRES AT LEAST 40UF CAPCITANCE, < 150MH ESL, <1MOHM ESR.
CAN BE UNINSTALLED FOR FINAL DESIGN
8134x POWER
PLACE ON BOTTOM SIDE
0603
EMPT
Y
20%
4.7U
FEM
PTY
0603
20%
4VEM
PTY
20%
4V06
03EM
PTY
20%
4V4.7U
F06
03EM
PTY
4V4.7U
F06
03EM
PTY
4V4.7U
F06
03EM
PTY
4V06
03EM
PTY
20%
4.7U
F06
03EM
PTY
+1_2V +1_2V
+1_2V+1_2V
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
EMPT
Y20
%
20%
20%
4.7U
F4V
0603
4.7U
F4V4V4.
7UF
4.7U
F
4.7U
F
20%
20%
4V4.7U
F06
03EM
PTY
20%
4V06
03EM
PTY
20%
4V4.7U
F06
03
20%
0603
+1_2V+1_2V
+1_2V
4.7U
F
4.7U
F
4.7U
F
4.7U
F
4.7U
F
4.7U
F
EMPT
Y
EMPT
Y
20%
1UF
1UF
+1_2V
1UF
4.7U
F
4V4.7U
F
4V
0603
EMPT
Y20
%4V4.
7UF
0603
4.7U
F4V
EMPT
Y20
%06
03
20%
EMPT
Y4V4.
7UF
0603
+1_2V
+1_2V10 of 13
9 of 13
-700 5.00Fri Feb 10 08:52:10 2006
1
2
C7N
3
2
1
C6M
1
1
2
C6N
10
1
2
C3D
8
1
2
C6N
12
1
2
C3D
11
2
1
C6M
6
2
1
C6M
4
2
1
C6M
5
2
1
C4A
7
2
1
C3D
1
2
1
C6N
8
2
1
C6N
7
1
2
C3D
4
1
2
C6N
9
1
2
C3C
3
1
2
C7N
6
1
2
C7N
4
1
2
C3C
2
1
2
C3D
3
1
2
C4A
8
1
2
C3D
10
1
2
C3C
1
2
1
C7N
2
1
2
C6N
11
1
2
C4A
11
1
2
C3C
4
1
2
C3D
5
2
1
C7N
1
2
1
C4A
6
Y25Y23
AA30AA28AA26AA24AA22AB31AB29AB27AB25AB23AC30AC28AC26AC24AC22AD31AD27AD25AD23AE30AE28AE26AE24AE22AF31AF29AF27AF25AF23AG30AG28AG26AG24AG22AH31AH29AH27AH25AH23AJ30AJ28AJ27AJ26AK31AK29AK27AL30AL28AL27AL26AM27AN27AP27AR27AT27AU27AJ24AK25AL24
J26J28J30H25H27H29H31
K31K29K27K25K23L30L28L26L24L22M31M29M27M25M23N30N28N26N24N22P31P29P27P25P23R30R28R26R24R22T31T29T27T25T23U30U28U26U24U22V31
W24W26W28W30V23V25V27
W22Y31Y27U4B1
Y9Y7Y21Y19Y17Y15Y13Y11W8W20W18W16W14W12W10V9V7V21V19V17V15V13V11U8U20U18U16U14U12U10T9T7T21T19T17T15T13T11R8R20R18R16R14R12R10P9P7P21P19P17P15P13N8N20N18N16N14N12N10M9M7M21M19M17M15M13M11L8L20L18L16L14L12L10K9K7K21K19K17K15K13K11J8J24J22J18J14J12J10H9H7H23H19H17
AG8
H11H13
G8
AU12G10
AT12AR12AP12AN12AM12
AL8AL22AL18
AL14AL16
AL12AL10
AK9
AK23AK7
AK21AK17AK15AK13
AJ8AK11
AJ20AJ22
AJ18
AJ14AJ16
AJ10AJ12
AH9
AH21AH7
AH17AH19
AH15
AH11AH13
AG20AG18AG16AG14AG12AG10
AF9AF7
AF21AF19AF17AF15AF13AF11
AE8AE20AE18
AE14AE16
AE12AE10
AD9AD7
AD21AD19AD17AD15AD13
AC8AD11
AC18AC20
AC16
AC12AC14
AB9AC10
AB7
AB19AB21
AB15AB17
AB13AB11
AA8AA20AA18AA16AA14AA12AA10 U4B1
2
1
C6N
1
2
1
C6N
5
1
2
C7N
5
2
1C
6N4
2
1
C6N
32
1
C6N
2
2
1
C6N
6
68
2
A
B
C
D
2 1345
D
C
B
A
8 6 5 3
MODIFIEDSHEET
4 1
DRAWING REVBOARD REV
7
7
POWERVCC1P2_0VCC1P2_1VCC1P2_2VCC1P2_3VCC1P2_4VCC1P2_5VCC1P2_6VCC1P2_7VCC1P2_8
VCC1P2_10VCC1P2_9
VCC1P2_12VCC1P2_11
VCC1P2_13
VCC1P2_15VCC1P2_14
VCC1P2_17VCC1P2_16
VCC1P2_18
VCC1P2_20VCC1P2_19
VCC1P2_22VCC1P2_21
VCC1P2_23VCC1P2_24VCC1P2_25VCC1P2_26VCC1P2_27VCC1P2_28VCC1P2_29VCC1P2_30VCC1P2_31
VCC1P2_33VCC1P2_32
VCC1P2_34VCC1P2_35VCC1P2_36VCC1P2_37VCC1P2_38VCC1P2_39VCC1P2_40VCC1P2_41VCC1P2_42VCC1P2_43VCC1P2_44VCC1P2_45VCC1P2_46VCC1P2_47VCC1P2_48VCC1P2_49VCC1P2_50
VCC1P2_53VCC1P2_52
VCC1P2_54
VCC1P2_56VCC1P2_55
VCC1P2_58VCC1P2_57
VCC1P2_59
VCC1P2_61VCC1P2_60
VCC1P2_63VCC1P2_62
VCC1P2_64
VCC1P2_66VCC1P2_65
VCC1P2_68VCC1P2_67
VCC1P2_69VCC1P2_70VCC1P2_71VCC1P2_72
VCC1P2_74VCC1P2_73
VCC1P2_75VCC1P2_76VCC1P2_77
VCC1P2_79VCC1P2_78
VCC1P2_80VCC1P2_81VCC1P2_82VCC1P2_83VCC1P2_84VCC1P2_85VCC1P2_86VCC1P2_87
VCC1P2_89VCC1P2_88
VCC1P2_90
VCC1P2_92VCC1P2_91
VCC1P2_51
VCC1P2_93VCC1P2_94VCC1P2_95VCC1P2_96VCC1P2_97VCC1P2_98VCC1P2_99
VCC1P2_100VCC1P2_101VCC1P2_102VCC1P2_103VCC1P2_104VCC1P2_105VCC1P2_106VCC1P2_107VCC1P2_108VCC1P2_109VCC1P2_110VCC1P2_111VCC1P2_112VCC1P2_113VCC1P2_114VCC1P2_115VCC1P2_116VCC1P2_117VCC1P2_118VCC1P2_119VCC1P2_120VCC1P2_121VCC1P2_122VCC1P2_123VCC1P2_124VCC1P2_125VCC1P2_126VCC1P2_127VCC1P2_128VCC1P2_129VCC1P2_130VCC1P2_131VCC1P2_132VCC1P2_133VCC1P2_134VCC1P2_135VCC1P2_136VCC1P2_137VCC1P2_138VCC1P2_139VCC1P2_140VCC1P2_141VCC1P2_142VCC1P2_143VCC1P2_144VCC1P2_145VCC1P2_146VCC1P2_147VCC1P2_148VCC1P2_149VCC1P2_150VCC1P2_151VCC1P2_152VCC1P2_153VCC1P2_154VCC1P2_155VCC1P2_156VCC1P2_157VCC1P2_158VCC1P2_159VCC1P2_160VCC1P2_161VCC1P2_162VCC1P2_163VCC1P2_164VCC1P2_165VCC1P2_166VCC1P2_167VCC1P2_168VCC1P2_169VCC1P2_170VCC1P2_171VCC1P2_172VCC1P2_173VCC1P2_174VCC1P2_175VCC1P2_176VCC1P2_177VCC1P2_178VCC1P2_179VCC1P2_180VCC1P2_181VCC1P2_182VCC1P2_183VCC1P2_184VCC1P2_185VCC1P2_186
POWER
VCC1P2X118VCC1P2X117VCC1P2X116
VCC1P2X109VCC1P2X110VCC1P2X111VCC1P2X112VCC1P2X113VCC1P2X114VCC1P2X115
VCC1P2X108VCC1P2X107VCC1P2X106VCC1P2X105VCC1P2X104VCC1P2X103VCC1P2X102VCC1P2X101VCC1P2X100
VCC1P2X99VCC1P2X98VCC1P2X97VCC1P2X96VCC1P2X95VCC1P2X94VCC1P2X93VCC1P2X92VCC1P2X91VCC1P2X90VCC1P2X89VCC1P2X88VCC1P2X87VCC1P2X86VCC1P2X85VCC1P2X84VCC1P2X83VCC1P2X82VCC1P2X81VCC1P2X80VCC1P2X79VCC1P2X78VCC1P2X77VCC1P2X76VCC1P2X75VCC1P2X74VCC1P2X73VCC1P2X72VCC1P2X71VCC1P2X70VCC1P2X69VCC1P2X68
VCC1P2X61VCC1P2X62VCC1P2X63VCC1P2X64VCC1P2X65VCC1P2X66VCC1P2X67
VCC1P2X60VCC1P2X59VCC1P2X58VCC1P2X57VCC1P2X56VCC1P2X55VCC1P2X54VCC1P2X53VCC1P2X52VCC1P2X51VCC1P2X50VCC1P2X49VCC1P2X48VCC1P2X47VCC1P2X46VCC1P2X45VCC1P2X44VCC1P2X43VCC1P2X42VCC1P2X41VCC1P2X40VCC1P2X39VCC1P2X38VCC1P2X37VCC1P2X36VCC1P2X35VCC1P2X34VCC1P2X33VCC1P2X32VCC1P2X31VCC1P2X30VCC1P2X29VCC1P2X28VCC1P2X27VCC1P2X26VCC1P2X25VCC1P2X24VCC1P2X23VCC1P2X22VCC1P2X21VCC1P2X20VCC1P2X19VCC1P2X18VCC1P2X17VCC1P2X16VCC1P2X15VCC1P2X14VCC1P2X13VCC1P2X12VCC1P2X11VCC1P2X10VCC1P2X9VCC1P2X8VCC1P2X7VCC1P2X6VCC1P2X5VCC1P2X4VCC1P2X3VCC1P2X2VCC1P2X1VCC1P2X0
8134x
8134x
Host Bus Adapter Schematics for Intel® 8134x I/O Processors 18
8134x GROUND / NO CONNECTS
16
24
14
30
22
6
2719
11
3
SL_TEST<31..0>
1
0
9
17
25
8
412
20
28
2
10
18
26
715
2331
5
13
21
29
4 of 13
13 of 13
8134x
12 of 13
-600 5.00-600 5.00-600 5.00Fri Feb 10 08:52:10 2006Fri Feb 10 08:52:10 2006Fri Feb 10 08:52:10 2006Fri Feb 10 08:52:10 2006
AG29AG27AG25AG23AG21AG19AG17
AE34AE36
AE4AE7AE9
AF10AF12AF14AF16AF18AF20AF22AF24AF26AF28AF30
AF8AG11AG13AG15
AD20AD22
AD26AD24
AD28AD30AD33
AD8AE11AE13AE15AE17AE19
AE2AE21AE23AE25AE27AE29AE31
AD18
AB36AB4AB8
AC11AC13AC15
AC19AC17
AC21
AC25AC23
AC27AC31
AC7AC9
AD10
AD16AD14AD12
AB34
AA21AA23AA25AA27AA29AA31
AA7AA9
AB10AB12AB14AB16AB18
AB2
AB24AB22AB20
AB28AB26
AB30
AA19
AA15AA17
AA13AA11
A35A3
AG7AG31
AH10AG9
AH12AH14AH16
AJ23AJ25
AJ19AJ21
AJ17
AJ13AJ15
AH8AJ11
AH4
AH34AH36
AH26AH28AH30
AH22AH24
AH18AH2AH20
AL15AL13
AK8AL11
AK28AK30
AK26
AK22AK24
AK14
AK18AK16
AK10AK12
AJ36
AJ9AJ7
AJ31AJ34
AJ29
AL17
AR34AR1AP7AP4
AP28AP31
AM36AP10
AM34
AL7AL9
AL31AL33AL4
AL25AL29
AL2AL21AL23
AR37
Y22Y20
Y16Y18
Y12Y14
Y10
H16W2
AU34AU35H15
AU3AU33
AT31AT36AT7
AT2AT28
AT10
Y24
Y30Y28Y26
Y8Y35
U4B1
M8N13N15N17N19
M33M30M28M26M24M22M20M18M16M14M12M10
L9L7
L31L29L27L25L23L21L19L17L15L13L11
K8K4
K36K34K30K28K26K24K22K20
K2K18K16K14K12K10
J9J7
J36J34J31J29J27J25J23J19J17J13J11
H8H30H28H26H24H22H18H14H12H10
G9G7G4G2
G11F36F34E33
E2D7D4
D30D27D10C37C34
C1B7
B10B2
B27B30B36
N2N21N23N25N27N29
R13R11P8P30P28P26P24P22P20P18P16P14P12P10N9N7N4N36N34N31
T24T22T20T2T18T16T14T12T10R9R7R31R29R27R25R23R21R19R17R15
T26
V10U9U7U31U27U25U23U21U19U17U15U13U11T8T4T36T34T30T28
V12
W27W25W23W21
W15W13W11W1V8V35V30V26V24V22V20V18V16V14
W17W19
W31W33W4W7W9
U4B1
1C4
B31B32
E32
F21F28
AL19A34
A28A29
A32A33
AL20AM19AM20
AN9B28B29
B33B34B35C28C29C30C31C32C33D28D29 D31
D32D33D5E28E29E3E30E31
F15F16F20
F29F30F31G1G15G16G20
J2J3W29
G21H2
A30A31
U4B1
68
2
A
B
C
D
2 1345
D
C
B
A
8 6 5 3
MODIFIEDSHEET
4 1
DRAWING REVBOARD REV
7
7
NO CONNECTS
NC3NC2
NC50NC49
NC53NC52NC51
NC48NC47NC46NC45NC44NC43NC42
NC39NC38NC37
NC35NC34NC33NC32NC31NC30NC29NC28NC27NC26
NC25NC24NC23NC22NC21NC20NC19NC18NC17NC16
NC13NC12NC11NC10NC9NC8
NC5NC4
NC1NC0
NC6NC7
NC41NC40
NC36
NC15NC14
OUT
GROUND 1 VSS359VSS358VSS357VSS356VSS355
VSS349VSS348
VSS334VSS335VSS336VSS337VSS338VSS339VSS340VSS341VSS342VSS343VSS344VSS345VSS346VSS347
VSS351VSS352VSS353VSS354
VSS333
VSS314VSS315VSS316VSS317VSS318VSS319VSS320VSS321VSS322VSS323VSS324VSS325VSS326VSS327VSS328VSS329VSS330VSS331VSS332
VSS313
VSS293VSS294VSS295VSS296VSS297VSS298VSS299VSS300VSS301VSS302VSS303VSS304VSS305VSS306VSS307VSS308VSS309VSS310VSS311VSS312
VSS273VSS274VSS275VSS276VSS277VSS278VSS279VSS280VSS281VSS282VSS283VSS284VSS285VSS286VSS287VSS288VSS289VSS290VSS291VSS292
VSS272VSS271VSS270VSS269VSS268VSS267
VSS177VSS176VSS175VSS174VSS173
VSS178VSS179VSS180VSS181VSS182VSS183VSS184VSS185VSS186VSS187VSS188VSS189VSS190VSS191VSS192VSS193VSS194VSS195VSS196VSS197VSS198VSS199VSS202VSS203VSS204VSS205VSS206VSS207VSS208VSS209VSS210VSS211VSS212VSS213VSS214VSS215VSS216VSS217VSS218VSS219VSS220VSS221VSS222VSS223VSS224VSS225VSS226VSS227VSS228VSS229VSS230VSS231VSS232VSS233VSS234VSS235VSS236VSS237VSS238VSS239VSS240VSS241VSS242VSS243VSS244VSS245VSS246VSS247VSS248VSS249VSS250VSS251VSS252VSS253VSS254VSS255VSS256VSS257VSS258VSS259VSS260VSS261
VSS266VSS265VSS264VSS263VSS262
GROUND 2
VSS371VSS372
VSS368VSS369VSS370
VSS367
VSS163
VSS165VSS164
VSS168VSS167VSS166
VSS170VSS169
VSS200VSS172VSS171
VSS350VSS201
VSS360
VSS362VSS361
VSS364VSS363
VSS365VSS366
VSS162
VSS145VSS144VSS143
VSS147VSS146
VSS150VSS149VSS148
VSS152VSS151
VSS153
VSS155VSS154
VSS157VSS156
VSS158VSS159VSS160VSS161
VSS142
VSS122
VSS124VSS123
VSS126VSS127
VSS125
VSS129VSS128
VSS131VSS132
VSS130
VSS134VSS133
VSS135
VSS137VSS136
VSS139VSS138
VSS140VSS141
VSS104VSS103VSS102
VSS106VSS105
VSS109VSS108VSS107
VSS111VSS110
VSS112
VSS114VSS113
VSS116VSS115
VSS117
VSS119VSS118
VSS121VSS120
VSS101VSS100
VSS99
VSS97VSS98
VSS95VSS96
VSS0VSS1VSS2VSS3
VSS5VSS4
VSS6
VSS26
VSS24VSS25
VSS21VSS22VSS23
VSS20VSS19VSS18VSS17VSS16VSS15VSS14VSS13VSS12VSS11VSS10VSS9VSS8VSS7
VSS27
VSS44VSS45VSS46
VSS43VSS42VSS41VSS40VSS39
VSS37VSS38
VSS36
VSS34VSS35
VSS33VSS32VSS31VSS30VSS29VSS28
VSS47
VSS67VSS66VSS65VSS64VSS63VSS62VSS61VSS60VSS59VSS58VSS57VSS56VSS55VSS54VSS53VSS52
VSS50VSS51
VSS49VSS48
VSS87VSS86VSS85VSS84VSS83VSS82VSS81VSS80VSS79VSS78VSS77VSS76VSS75VSS74VSS73VSS72VSS71VSS70VSS69VSS68
VSS88VSS89VSS90VSS91VSS92VSS93VSS94
8134x
8134x
Host Bus Adapter Schematics for Intel® 8134x I/O Processors 19
:SETONTUOYAL
SNOISIVER
DIFFERENTIAL OSCILLATOR 125 MHZ
.ELBISSOPSA120348OTESOLCSASTNENOPMOCECALP
.SRIAPLAITNEREFFIDSAN_RKLC,P_RKLC,N_CKLC,P_CKLC,N_KLC,P_KLCETUOR
.ETONTUOYALRIAPFFIDDEDDA.TFOSOTSEDFERDEGNAHC:9.0.2040OTROTSISERMHO01DEGNAHC:8.0
DRAHSEDFEREDAM,STRAPNOMMOCOTSPACSEIRESDEGNAHC:7.0.STNENOPMOCELBALIAVAEROMOTROTICAPACDAOLDNALATXDEGNAHC:6.0
ESAELERLAITINI:5.0
AD120348EES TNENOPMOCROFTEEHSAT NEMECALP .ELPMAXET
FU1.0
%1
P_CKLC
N_CKLC
33PF
0.1U
F
N_RKLC
281
N_KLC
P_KLC2LATX
0.01
UF
9.94
%1
33PF
V3_3+
1LATX
%1
9.94 FU1.0
%1281
P_RKLC
10U
F
ZHM000.52_S94CH
V3_3+
%101 KLC_AV3_3+
120348SCI
dom_m521_cso
hcs_keerc_alohohs00.5007-500201:33:7101rpAnuS
6C8
1 25A3R
1
2
C3A
3
1
2
C3A
4
1
2
C3A
5
1
2
C3A
8
6C8
1
2
C3A
10 2
12A3R
1234
8765
1A3U
1 2
1A3Y
2
16A3R
1 24A3R
1 23A3R
1 2
7A3C
1 2
6A3C
LLEC
68
2
A
B
C
D
2 1345
D
C
B
A
8 56 3
DEIFIDOMTEEHS
4 1
VERGNIWARDVERDRAOB
7
TCEJORPRETSAM
7
CNOQNOQCCV
1LATX2LATX
EEVACCV
TUO
TUO
Host Bus Adapter Schematics for Intel® 8134x I/O Processors 20
0.55: ADDED BACKPLANE DETECT SIGNAL ON PIN A32.0.54: CHANGED PE_TDO TO IN, PE_TDI TO OUT0.53: MOVED TEXT ON MOD SYMBOL, MOVED C NET LABELS TO CONNECTOR SIDE
ALL SIGNALS HAVE PE PREFIX
0.52: CHANGE SIGNAL NAMES FOR VECTORS, ADD CONSTRAINTS
PCI-EXPRESS EDGE CONNECTOR
0.51: SWAPPED PE_T AND PE_R CONNECTIONS
ADDED BUBBLES FOR ACTIVE LOW SIGNALS
0.1: DESIGN REVIEWMODULE REVISIONS:
PE_TCK
PE_SMDAT
PE_WAKE_N
PE_RST_N
PE_REFCLK_N
PE_SMCLK
PE_TRST_N
PE_TMSPE_TDOPE_TDI
PE_R_P[7..0]PE_R_N[7..0]
PE_TC_N[7..0]PE_TC_P[7..0]
PE_T_N[7..0]PE_T_P[7..0]
33
55
6
7
6
7
+3_3VAUX
+3_3V
01234567
0123456
01234567
01234567
+12V
7
PCI_EXP_X8_EDGE
0 0.1UF0.1UF
1
2
3
5
7
0
1
3
4
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF0.1UF
0.1UF
0.1UF5
7
0.1UF
0.1UF
1
2
1
22
66
4
0.1UF
00
44
0.1UF
0.1UF
0.1UF
PE_REFCLK_P
PE_PRSNT
BP_DET_N
-700 5.00Fri Dec 23 15:07:25 2005
1 2
C3D25
1 2
C3D23
1 2
C3D24
1 2
C3D22
1 2
C3D20
1 2
C3D21
1 2
C3D17
1 2
C3D191 2
C3D18
1 2
C3D16
1 2
C3D15
1 2
C2D5
1 2
C3D14
1 2
C2D4
1 2
C2D2
1 2
C2D3
1A5
1A5
1A5
1A5
1A4
1A4
1A4
A1
B48B31B17
B3
A14A13
A11
A32A33
A19B30B12
B11B6B5
A22A17
A30
A40A36
A26
A44A48
A25A21A16
A29A35
A47A43A39
B15
B34B28B24B20
B38
B19B14B46B42
B23B27B33B37B41B45
A49A46A45A42A41
A31A28
A34A37A38
A27A24A23A20A18
B49B47
A4A12A15
B44B43B40B39B36B35
B26B29
B25
B32
B22B21B18
B13B16
B7
B9
B4
A5A6A7A8
A10B10
A9B8A3A2B2B1
J2D2
1A4
68
2
A
B
C
D
2 1345
D
C
B
A
8 6 5 3
MODIFIEDSHEET
4 1
DRAWING REVBOARD REV
7
7
IO
OUT
OUTIN
+12V1+12V2+12V3+12V4
+3.3V1+3.3V2
3.3VAUX+3.3V3
TMSTDOTDITCK
GND1
TRST_N
GND2
GND4GND3
GND5GND6GND7
GND11
GND8
GND10GND9
GND12GND13GND14GND15GND16GND17
GND22GND21GND20
GND18GND19
GND23GND24GND25GND26GND27
GND32GND31GND30
GND28GND29
GND33GND34GND35GND36GND37
PETP7PETP6PETP5PETP4PETP3PETP2
PETN6PETN7PETP0PETP1
PETN5
PETN1PETN2PETN3PETN4
PETN0
PERP5PERP6PERP7
PERP4PERP3
PERP0PERP1PERP2
PERN7PERN6
PERN2
PERN4PERN5
PERN3
PERN0PERN1
SMCLKSMDATWAKE_N
RSVD2RSVD3RSVD4
RSVD6RSVD5
PERST_N
REFCLK_PREFCLK_N
RSVD1
PRSNT2_N1PRSNT2_N2PRSNT2_N3
PRSNT1_N
OUT
OUTOUT
OUT
OUT
OUTOUT
OUTOUT
ININ
IO
Host Bus Adapter Schematics for Intel® 8134x I/O Processors 21
DDR2 DIMM SOCKET
ECO: CHANGED POWER RAILECO: CHANGED POWER RAIL
TO 1K OHM TO REDUCE POWERCONSUMPTION IN BBU MODE.
ECO: CHANGED VREF RESISTORS
DDR_MISC<3..0>DDR_RESET_NDDR_MA<15..0>
01
0.1UF
DDR_DQS_N<8..0>
DDR_RAS_N
21
0
1
67
DIMM_DDR2_RA
1 of 2
DDR_DQS_P<8..0>
2
2
2
6
0
1
0
4
DDR_CS_N<1..0>
11
1
8
5
10
1
0
14
5049
7
3
0
29
44
59
1
56
210
0
14
345
8910
1213
15
12
5
26
7
8
6
5
4
3
2
1
0
5
7
6
3
2
1
4
6160
63
565554535251
48474645
41
3837
353433323130
21
18
16
13
98
6
32
0
4
62
12
43
24
2
0
34
1
2
0
42
23
2728
2019
17
25
15
58
11
7
57
36
3940
10
DDR_DQ<63..0>
DDR_BA<2..0>
1
DDR_CAS_N
8
7
+3_3V
DDR_VREF
DDR_SCLDDR_SDA
DDR_SA<2..0>
0.1UF
0
DDR_CK_P<2..0>
DDR_CK_N<2..0>
GPIO<7>GPIO<6>
+1_8V_B
22DDR_CB<7..0>
DDR_WE_N
DDR_DM<8..0>
DDR_ODT<1..0>
DDR_CKE<1..0>
0.1U
F
+1_8V_B
1%1K
1%1K
-700 5.00Thu Jan 12 14:20:55 2006
1D5
1D5
1 2
C9B5
1 2
C9B6
1D4
1D4
1D5
1D4
1D4
1D5
1D4
1D5
1D5
1D5
1D5
1D5
1D5
1D5
18
73193
76
74
224212203156147135126
165233
221
138
186
45
113
92
36
83
104
27
15
6
71
6160
70
220
239
119120
240101
137
185
177
173174
57176196
179
18058
182
18363
188
164
223
202155
134
55
1
19577
238
167
232
211
146
168
125
162
4849
190
43
161
46
105
114
93
84
37
236235230
7
16
28
229
111
227226
117116
110
107
217108
218
96208209
215214
9899
9095
89206
199200205
87
80159158
8681
153
33
3934
40152
14331
14124
13
2221
131132140
2530
109
122123
12912
128
171
42
150149144
52
54
34
192
J9C1
1D5
1D5
1 2R9B3
1 2R9B4
1
2
C9B
4
1D417D8
1D4
1D4
68
2
A
B
C
D
2 1345
D
C
B
A
8 6 5 3
MODIFIEDSHEET
4 1
DRAWING REVBOARD REV
7
7
IOIO
BI
IO
IO
IO
RAS_N
DQ1DQ0
A16_BA2
CKE0
DQ21DQ22DQ23
CB0
CKE1
DQ6
DQ8DQ7
DQ5DQ4
DQ2DQ3
DQ18DQ17
DQ14DQ13DQ12
DQ10DQ11
DQ9
DQ16DQ15
DQ19DQ20
DQ28DQ27
DQ25DQ26
DQ24
DQ29
DQ33DQ34
DQ30DQ31DQ32
DQ35
DQ38DQ37DQ36
DQ39DQ40
DQ42DQ41
DQ49DQ48
DQ46DQ47
DQ45DQ44DQ43
DQ53
DQ51DQ52
DQ50
DQ56
DQ58DQ59
DQ54DQ55
DQ57
DQ60
DQS2
DQS1
DQS0
DQ61DQ62DQ63
DQS3
DQS4
DQS5
DQS7
DQS6
DQS8
CB4
CB1
BA1
CB3CB2
CB5
DM0_DQS9
CB7
DM2_DQS11
DM5_DQS14
DM7_DQS16
CB6
VDDSPD
ODT1ODT0
VREF
RC0
DM1_DQS10
DM3_DQS12DM4_DQS13
DM6_DQS15
DM8_DQS17
A0
A2A1
A3
A7A6
A8
A13A12A11
A14A15
A9
CK0
CK1_RFU
SA2SA1
SCLSDA
SA0
CK2_RFU
A10_AP
A5A4
BA0
DQS0_N
DQS1_N
DQS2_N
DQS6_N
DQS4_N
DQS3_N
DQS5_N
DQS7_N
DQS8_N
CK0_N
CK1_RFU_N
CK2_RFU_N
NC_DQS16_NNC_DQS17_N
NC_DQS9_NNC_DQS10_NNC_DQS11_NNC_DQS12_NNC_DQS13_NNC_DQS14_NNC_DQS15_N
CAS_N
S1_NS0_NWE_N
RESET_N
INIOIO
IN
ININ
ININ
IN
IN
IN
ININ
IN
IN
IO
IO
Host Bus Adapter Schematics for Intel® 8134x I/O Processors 22
1.1: 4/25/05 - FIXED VREF TO BE GENERATED FROM SAME RAIL AS DIMM POWER1.0: 2/4/05 - ADDED BBU BUS, REMOVED BBU CIRCUIT
MODULE REVISIONS:
0.5: INITIAL RELEASE
TIE +1.8V_Z TO +1.8V_B AT TOP LEVEL
VTT ISOLATED FROM
PLACE CAPACITORS ACROSS FILLS AS NEARPLACE TERMINATIONS ACROSS FILLS
TERMINATIONS AS POSSIBLE
CREATE FILL FOR +1.8V_Z AND GND
DDR POWER FOR BATTERY BACK UP
VTT GENERATION & DIMM POWER
FOR NON-BBU APPLICATIONS
+1_8V_Z
+1_8V_B
+1_8V_B
+1_8V_Z
+1_8V_Z
0.1U
F
DDR_MA<15..0>
DDR_ODT<1..0>
100 1%
0
1
2
100
100
100
1%
10
1
1% 1% 1% 1% 1% 1%
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1%1%10
01%
100
1% 1%1%
1%10
010
01%1%1%1%1%
100
100
100
1%10
010
01%
100
1% 1%10
0
1%1%1%1%10
010
0
100
1%1%10
010
010
010
0
100
100
100
100
1%1%10
010
01%1%
100
100
1%1%10
010
01%1%
100
100
1%1%10
010
01%1%
100
1%
100
1% 1%
15 12 11 109
98
87
7 66 5
54
43
3 22 1
10
1UF
1UF
100
1%
100
100
01011121314
1%
1%
100
14 131%1%
1%
01
15
1%
1%10
010
0
100
100
100
1%
1%10
0
1%
100
100
0
2 of 2
DIMM_DDR2_RA
100
100
100
100
100
100
0.1U
F
0.1U
F
0.1U
F
0.1U
F
0.1U
F
0.1U
F
0.1U
F
0.1U
F
0.1U
F
0.1U
F
0.1U
F
0.1U
F
0.1U
F
0.1U
F
0.1U
F
DDR_BA<2..0>
DDR_RAS_NDDR_CAS_NDDR_WE_NDDR_CS_N<1..0>
DDR_CKE<1..0>
+3_3V
3
DDR_MISC<3..0>
-700 5.00Fri May 20 15:20:12 2005
1
2
C8B
15
1
2
C7C
6
1
2
C7C
5
21
R8B
132
1R
7B25
21
R7B
3
21
R7B
23
21
R7B
212
1R
7B10
21
R7B
222
1R
7B19
21
R7B
20
21
R7B
18
21
R7B
172
1R
7B16
21
R7B
15
21
R8C
22
1R
7C25
21
R7C
3
21
R7C
23
21
R7C
212
1R
7C10
21
R7C
222
1R
7C19
21
R7C
20
21
R7C
18
21
R7C
172
1R
7C16
21
R7C
152
1R
7B13
21
R7B
14
21
R7B
12
21
R7C
132
1R
7C14
21
R7C
12
21
R7C
92
1R
7C11
21
R7B
92
1R
7B11
1
2
C7B
14
21
R7B
242
1R
7B8
21
R7B
52
1R
7B6
21
R7B
72
1R
7B2
21
R8B
122
1R
8B14
21
R7B
42
1R
7B1
21
R7C
42
1R
7C1
21
R8C
3
21
R7C
2
21
R8C
1
21
R7C
72
1R
7C6
21
R7C
52
1R
7C8
21
R7C
24
16D8
16D8
16D8
16D8
16D8
16C8
16C8
16B8
16B8
1
2
C7B
3
1
2
C7B
4
1
2
C7B
5
1
2
C7B
6
1
2
C7B
10
1
2
C7B
11
1
2
C7B
12
1
2
C7B
7
1
2
C7B
8
1
2
C7B
9
1
2
C7B
13
1
2
C7B
1
1
2
C7C
2
1
2
C7C
3
1
2
C7C
4
1
2
C8C
3
1
2
C8C
2
1
2
C8C
1
1
2
C7C
1
1
2
C6C
1
231
194
82
216219
169198
204
148151
112115118
187189197
237234
228225222
213
201
207210
166163160157
145142
154
139136133130127
121124
109106103100
9794918885
666550
3532
38
292623
1411
82
191181175170787572625651
1841781726967645953
1026819
205
17
474441
79
J9C1
1
2
C7B
2
1
2
C8B
14
68
2
A
B
C
D
2 1345
D
C
B
A
8 6 5 3
MODIFIEDSHEET
4 1
DRAWING REVBOARD REV
7
7
VSS19
VSS13VSS14VSS15
VSS5VSS1VSS6
NC0NC1NC2
VDD0VDD1VDD2VDD3VDD4VDD5VDD6VDD7
VDDQ1VDDQ2VDDQ3VDDQ4VDDQ5VDDQ6VDDQ7VDDQ8VDDQ9
VDDQ10
VSS0VSS2VSS3VSS4
VSS7VSS8VSS9
VSS12
VSS10VSS11
VSS16VSS17VSS18
VSS21VSS22VSS23VSS24VSS25VSS26VSS27VSS28VSS29
VSS34VSS33
VSS35VSS36VSS37VSS38VSS39
VSS44
VSS40VSS41
VSS45VSS46VSS47VSS48
VSS54VSS53
VSS51
VSS55
VSS58VSS59VSS60
VSS62VSS63
VDD10VDD9VDD8
VSS32VSS31VSS30
VSS43VSS42
VSS52
VSS50VSS49
VSS57VSS56
VSS20
VDDQ0
VSS61
BI
IN
IN
IN
ININININ
IN
Host Bus Adapter Schematics for Intel® 8134x I/O Processors 23
0.5: INITIAL RELEASE
LAYOUT NOTES:PLACE AC COUPLING CAPS CLOSE TO
REVISIONS
EITHER SOURCE OR DESTINATION.
SAS CONNECTORS 4 X1 INTERNAL (DUAL STACKED)
SAS_RC_P3SAS_RC_N3
SAS_TC_N3SAS_TC_P3
SAS_RC_P2SAS_RC_N2
SAS_TC_N2SAS_TC_P2
SAS_RC_P1SAS_RC_N1
SAS_TC_N1SAS_TC_P1
SAS_RC_P0
SAS_TC_N0SAS_TC_P0
SAS_RX_N<3..0>
SAS_RX_P<3..0>
SAS_TX_N<3..0>
SAS_TX_P<3..0>
2
3
33
0.01UF
0.01UF0.01UF
0.01UF
11
11
0.01UF
0.01UF0.01UF
2
22
00
00
0.01UF
0.01UF
0.01UF
0.01UF
0.01UF
0.01UF
0.01UF
3
SAS_CONN_DUAL
SAS_CONN_DUAL
SAS_RC_N0
0.01UF
0.01UF
C5A2 12
C5A1 12
C6A4 12
C6A3 12
C5A3 12
C6A1 12
C5A4 12
C6A2 12
C6A6 12
C7A9 12
C6A5 12
C6A11 12
C6A7 12
C6A9 12
C6A8 12
C6A10 12
J6A1
1
4
7
8
11
14
65
1312
23
910
J6A2
1
4
7
8
11
14
65
1312
23
910
-700 5.00Tue Aug 15 09:39:19 2006
1C2
1C2
1C2
1C2
68
2
A
B
C
D
2 1345
D
C
B
A
8 6 5 3
MODIFIEDSHEET
4 1
DRAWING REVBOARD REV
7
7
GND1TX0+
GND6RX1+RX1-GND5TX1-TX1+GND4
GND3RX0+RX0-GND2TX0-
GND1TX0+
GND6RX1+RX1-GND5TX1-TX1+GND4
GND3RX0+RX0-GND2TX0-
IN
OUT
IN
OUT
Host Bus Adapter Schematics for Intel® 8134x I/O Processors 24
SAS SIGNALS FROM IO PROCESSOR TO X4
SOURCE OR DESTINATIONPLACE AC COUPLING CAPS NEAR EITHER
0.6: SWAPPED SAS LANES TO IMPROVE ROUTING.0.5: INITIAL RELEASE
LANE 0
LANE 1
LANE 2
LANE 3
SAS LANE CONNECTIONS
LANE 2
LANE 0
LANE 3
LANE 1
X4 INTERNAL SAS CONNECTOR
ORDER TO MATCH LANE SWAPS ON BOARD.B0 WILL ENABLE REORDERING SGPIO TRANSMIT
INTERNAL SAS CONNECTOR SWAPPED TO MINIMIZE VIAS.
LAYOUT NOTE:
REVISIONS
SAS CONNECTOR X4 INTERNAL
0.01UF
0.01UF
SAS_RC_N1SAS_RC_P1
SLOADSCLOCK
SAS_RC_P3SAS_RC_N3
SAS_TC_N3SAS_TC_P3
SAS_TC_N1SAS_TC_P1
SDATAOUTSDATAIN
SAS_RC_P0
SAS_TC_N0SAS_TC_P0
SAS_RC_N0
SAS_RC_P2SAS_RC_N2
SAS_TC_P2SAS_TC_N2
SAS_TX_N<3..0>
SAS_RX_N<3..0>
SAS_RX_P<3..0>
SAS_TX_P<3..0>
0.01UF
SAS_CONN_X4_INT_RA
+3_3V
3
1
0
2
3
1
0
2
3
1
0
2
3
1
0
0.01UF2
5%2K
5%2K
5%2K
0.01UF
0.01UF
0.01UF
0.01UF
5%2K
0.01UF
0.01UF
0.01UF
0.01UF
0.01UF
0.01UF0.01UF
0.01UF
-700 5.00Tue Jan 31 16:56:12 2006
12C7A5
12C7A7
12C7A6
12C7A8
12C7A1
12C8A1
12C8A3
12C8A2
12C8A4
12
R8A3
12C8A5
12C8A7
12C8A6
12C8A8
12
R8A2
12
R8A1
12
R7A1
1D1
1D1
1C1
1C1
1D1
1D1
12C7A2
12C7A3
1D1
1D1
32313029282726
2322
2524
212019181716
131211
9
76
1
5432
1415
10
8
J8A1
12C7A4
68
2
A
B
C
D
2 1345
D
C
B
A
8 6 5 3
MODIFIEDSHEET
4 1
DRAWING REVBOARD REV
7
7
CO
NTR
OLL
ERPI
NO
UT
RX1+
GND4
SIDEBAND1SIDEBAND0
RX0+RX0-GND2TX0-
GND1
TX0+GND3
RX1-
TX1-TX1+GND5
SIDEBAND2SIDEBAND3SIDEBAND4SIDEBAND5GND6RX2+
TX2-TX2+
RX2-GND7
GND8RX3+RX3-GND9TX3-TX3+GND10
IN
OUT
IN
OUT
OUTIN
ININ
8134x
8134x
8134x
Host Bus Adapter Schematics for Intel® 8134x I/O Processors 25
J1 OPEN
SGPIO / HD LED MUX
NOTE:
REVISIONS
SGPIO ROUTED TO SAS CONN
PRODUCTION DESIGNS WILL TYPICALLY CHOOSE EITHER HD LED OR SGPIO OPTION.HD LED / SGPIO MUX CIRCUIT IS FOR DEBUG AND TESING ONLY.
0.5 INITIAL RELEASE
ECO460829
1.0 ECO460829 REVERSED SCLOCK AND SLOAD SIGNAL CONNECTIONS
J1 SHORTED SGPIO ROUTED TO HD LEDS (DEFAULT)
SGPIO MUX
+3_3V
+3_3V
+3_3V
+3_3V
+3_3V +3_3V
S_ACT0_MUX
HDR_1X2_TH
QS125
LED_BLU
7
01
LED_BLU
6
LED_BLU
LED_BLU
LED_BLU
LED_BLU
345
7
234
67
5
4
5
4
3
1 1
02 S_ACT2_MUX0
3
LED_BLU
LED_BLU
6
7 510
510
510
510
510
510
510
510
510
510
510
510
510
510
510
LED_BLU
LED_BLU
LED_BLU
LED_BLU
LED_BLU
S_STAT0_MUXS_STAT2_MUX
10K
10K
HD
_LE
D_E
NR
_N
1K
LED_BLU
LED_BLU
5
HDR_2X10_2MM_SMEMPTY
1
SGPIO_EN_N
0.1U
F
+3_3V
LED_BLU
QS125
0.1U
F
510
SAS_STAT<7..0>
SAS_ACT<7..0>
HD_LED_EN_N
20 SCLOCK
0
2
6
2
20
SDATAINSLOADSDATAOUT
-700 5.00Fri Mar 31 11:24:33 2006
1 2R9A9
1
2
C9B
2
21
R9B
1
1C2
1C2
12
3
Q9B1
21
R9B
2
36
1114
25
1215
168
19
471013
U9A1
1 2
DS9A3
1 2
DS9A4
1 2
DS9A5
1 2
DS9A6
1 2
J9A1
1 2
DS9A7
1 2
DS9A8
1 2
DS9A9
21
R9A
17
1
2
C9A
1
42
86
101214161820
1
79
11131517
53
19
J9A2
1 2R9A8
1 2R9A7
1 2R9A6
1 2R9A5
1 2R9A4
1 2R9A3
1 2R9A2 1 2R8A41 2
DS8A1
1 2R9A10
1 2R9A11
1 2
DS9A10
1 2
DS9A11
1 2R9A12
1 2R9A13
1 2
DS9A12
1 2
DS9A13
1 2R9A14
1 2R9A15
1 2
DS9A14
1 2
DS9A15
1 2R9A161 2
DS9A16
1C2
1C2
1C2
36
1114
25
1215
168
19
471013
U9B1
1 2
DS9A2
1C2
68
2
A
B
C
D
2 1345
D
C
B
A
8 6 5 3
MODIFIEDSHEET
4 1
DRAWING REVBOARD REV
7
7
IN4Y3Y2Y1Y
NC2NC1
GNDVCC
4OE_N3OE_N2OE_N1OE_N
4A3A2A1A
OUT
OUTOUT
4Y3Y2Y1Y
NC2NC1
GNDVCC
4OE_N3OE_N2OE_N1OE_N
4A3A2A1A
C
E
B
IO
IO
Host Bus Adapter Schematics for Intel® 8134x I/O Processors 26
PLACE NEAR SLOT
AND GATE OUTPUTHIGH = NO CARD
CARD IS DETECTEDWILL TURN ON WHEN
LOW = CARD
3) SMBCLK & SMBDAT SEE SEC 4.3.3
WHEN NOT BEING USED
THESE SIGNALS REQUIRE INDIVIDUAL DECOUPLING
ALL REFERENCES TO PCI SPEC REV 2.3
NOT USED, BUT CONTROL SIGS NEEDPULL-UP TO ENSURE STABILITY
2) LOCK# SEE SECT 4.3.3 PCIX SPEC
PCI-X STRADDLE MOUNT (SM) SLOT
SEE 4.3.4.1
0 V IS ON 5VPCI
NO CONNECT
ON SLOT
NOTES:
PLACE NEAR SLOTS
NO
CO
NN
EC
T
NO CONNECT
FROM M66EN
SEE 4.3.3
INDIVIDUAL PULL-UPS REQUIRED
SEE 4.3.3
NO CONNECT
!) PRSNT1# & PRSNT2#
MUST BE <0.25
SEE SEC 4.3.7
ECO CHANGE
0.1 INITIAL RELEASEREVISION HISTORY
0.11 CHANGES PER DAN/REX
OF OTHER COMPONENTS ON THE BUSSYSTEM, AND NOT THE AUX POWER FOR PROPER FUNCTION
HARD CODED REFDES ON MODULE
0.2 REMOVED HARD, ROTATED FIRST Q, FIXED TEXT0.12 SINGLE AND GATE PINOUT CHANGED
WHEN PCI CARD IS DETECTEDRED LED WILL ILLUMINATE
9) PCIXCAP SEE SECTION 7.7.7 OF SPECDECOUPLED ON A SYSTEM LEVELPOWER PLANES ARE EXPECTED TO BE PROPERLY
8) DECOUPLING - SEE 4.3.4.3
7) 3.3VAUX TREATED AS RESERVED IF NOT USED.6) TDO MUST BE OPEN, IF NOT USED5) TRST# & TCK PULLED DOWN, IF NOT USED.
PULLED UP TO VCC, WHEN NOT USED..4) TMS & TDI IF NOT USED SHOULD BE
AND NO AUX POWER IS APPLIED
0.3 VOLTAGE ON PCIXCAP NEEDED TO BE SUPPLIED BY THE
0.31 UPDATED VRG_3P3V_MOD AND NO_BACKANNOTATE PROPERTY.
WILL TURN ON WHEN
NO CONNECT
0.1U
F
4.7K
BSS84
BSS84
RED_LED_ON
+3V_PCI
13
+3_3V
+5V_PCI
+12V_PCI
5% 4.7K5% PU_SMDAT
0.01UF
45
4.7K 5%
PCIX64_CONN_SM
PD_TCK
+3_3V +3_3V
+3_3V
10U
F
PCI_M66EN
PCI_ACK64_NPCI_REQ64_N
PCI_XINTD_NPCI_XINTC_N
PCI_XINTA_N
PCI_REQ_NPCI_CLK
5%
PD_TRST_N
PCI_TRDY_N
67
5%
4.7K
4.7K 5%5%
22U
F
0.1U
F
0.1U
F
0.1U
F
0.1U
F
123
56
89101112
14151617
202122232425262728293031323334353637383940414243
4647
4950515253545556575859
6263
2345
IDSEL
PU_LOCK_N
PCI_PERR_NPCI_SERR_NPCI_DEVSEL_N
1
SLOT_IDSEL
PCI_CBE_N<7..0>0
PCI_XINTB_N
7
18
10U
F
5%PU_TMS
PCI_PARPCI_FRAME_NPCI_IRDY_N
PCI_STOP_N
4.7K
5%
PCI_RSTOUT_N
4.7K
19
5%
6061
0.01
UF
4.7K
PCI_GNT_N
10U
F
PU_SMBCLK
0.1U
F
5%4.
7K NO_5V_AND_CARD
CARD_DETECTION
100
5%
RED_LED_ON_1
48
44
PCI_AD<63..0>
4
PCI_PAR64200
0.01
UF
PD_PRSNT2_N
0.01
UF
PD_PRSNT1_N
0.1U
F
0
4.7K
PCI_XCAP
+3_3V
5%3.3K
PU_TDI
B1
4P PWR CONN
74LVC1G08
PD_PRSNT2_N
PD_PRSNT1_N
0.1U
F
-700 5.00Mon Aug 21 17:01:22 2006
A58B58A57B56A55B55A54B53B52A49B48A47B47A46B45A44A32B32A31B30A29B29A28B27A25B24A23B23A22B21A20B20A91B90A89B89A88B87A86B86A85B84A83B83A82B81A80B80A79B78A77B77A76B75A74B74A73B72A71B71A70B69A68B68A40
A2
B25B31B36B41B43B54A21A27A33A39A45A53A14B19B59A10A16A59B70B79B88A66A75A84
B16
B49A26A67
A43
B38
B2A4B4A3
B10B14A9A11B63B92B93A92A94B5B6B61B62A5A8A61A62B3B15B17B22B28B34B46B50B51B57B64B67B73B76B82B85B91B94A18A24A30A35A37A42A48A50A51A56A63A69A72A78A81A87A90A93
A41
B18A17A6B7A7B8A52B44B33B26B66
B65A64
A60B60
A34B35A36A38B37B42B40A15
A19B39B9B11
A1
A65
J1A1
R8L21C2
1B2
1B2
12
R1A
3
1B2
1B2
1B2
1B2
1B2
1B2
1B2
1 2R7L2
C1A
1
C2A
1
1B2
1B2
1 2R7L3
1 2R7L1
1B2
1
2
C7L
1
12 R1A5
1 2 R1A412 R1A6
1
2
C4A
2
1
2
C8L
3
1
2
C7L
2
1
2
C4A
1
1
2
C6L
1
1
2
C8L
2
1
2
C6L
2
1
2
C1A
2
1
2
C3A
2
1
2
C1A
4
1
2
C1A
6
1
2
C1A
5
12
R9L
1
12
R9L
2
1B2
12
DS1
A1
4321
J1A2
3 2
1 Q1A2
32
1 Q1A1
12
R1A
2
12
R1A
1
12
R8L
1
12C8L1
1B2
1B2
1B2
1B2
1
5
24
3
U1A1
1B2
1B2
1B2
1C2
1B2
1B2
68
2
A
B
C
D
2 1345
D
C
B
A
8 6 5 3
MODIFIEDSHEET
4 1
DRAWING REVBOARD REV
7
7
OUTIN
IO
IO
IO
IN
GND
YB
VCCA
IO
IOIO
IO
G
S
D
G
SD
+12VGND0GND1
+5V
VRG_3P3V_MOD REV 0.52
EN_3P3_BUCKFSYNCIN_3P3+VIN +3P3V_BUCK
SYNCOUT_3P3POK_3P3
IO
IN
INOUT
IOIOIOIOIOIOIOIOIO
OUT
CBE5_N
TRST_N
PRSNT2_NPRSNT1_N
LOCK_NPME_N
RST_NPERR_NSERR_N
DEVSEL_NSTOP_NTRDY_NIRDY_N
FRAME_N
ACK64_NREQ64_N
CBE7_NCBE6_N
CBE4_NCBE3_NCBE2_NCBE1_NCBE0_NINTD_NINTC_NINTB_NINTA_N
GNT_NREQ_N
SMBDAT
GND36GND35GND34GND33GND32GND31GND30GND29GND28GND27GND26GND25GND24GND23GND22GND21GND20GND19GND18GND17GND16GND15GND14GND13GND12GND11GND10
GND9GND8GND7GND6GND5GND4GND3GND2GND1+5V8+5V7+5V6+5V5+5V4+5V3+5V2+5V1
RSVD11RSVD10
RSVD9RSVD8RSVD7RSVD4RSVD3RSVD2RSVD1
TMSTDOTDITCK
PCIXCAP
PAR
PAR64IDSELM66EN
CLK
+3.3VIO11+3.3VIO10+3.3VIO9+3.3VIO8+3.3VIO7+3.3VIO6+3.3VIO5+3.3VIO4+3.3VIO3+3.3VIO2+3.3VIO1+3.3VAUX+3.3V12+3.3V11+3.3V10+3.3V9+3.3V8+3.3V7+3.3V6+3.3V5+3.3V4+3.3V3+3.3V2+3.3V1-12V+12V
SMBCLKAD63AD62AD61AD60AD59AD58AD57AD56AD55AD54AD53AD52AD51AD50AD49AD48AD47AD46AD45AD44AD43AD42AD41AD40AD39AD38AD37AD36AD35AD34AD33AD32AD31AD30AD29AD28AD27AD26AD25AD24AD23AD22AD21AD20AD19AD18AD17AD16AD15AD14AD13AD12AD11AD10AD09AD08AD07AD06AD05AD04AD03AD02AD01AD00
Host Bus Adapter Schematics for Intel® 8134x I/O Processors 27
LOCATION 1
SEE LAYOUT GUIDE
BETWEEN PGND AND GND
SEE LAYOUTGUIDE
VRG 3P3V_BUCK
9A MAX OUTPUT
PLACE THE DECOUPLING CAPACITOR (LOCATION 3) CLOSE TO CS_P AND CS_N PINS.
CAPACITOR (LOCATION 1) NEAR CS_N. RUN TWO CLOSELY PARALLEL
6) PLACE THE FEEDBACK AND COMPENSATION COMPONENTS AS CLOSE TO THE IC PINS AS
2) CONNECT INPUT, OUTPUT, AND VL CAPACITORS TO THE POWER GROUND PLANE;
PC BOARD TRACE RESISTANCE. PLACE THE INPUT BIAS BALANCE RESISTOR AND BYPASS
CONNECT ALL OTHER CAPACITORS TO THE SIGNAL GROUND PLANE.
INDUCTOR AS POSSIBLE. MAKE A KELVIN CONNECTION TO MINIMIZE THE EFFECT OF
5) CONNECT THE DRAIN LEADS OF THE POWER MOSFETS TO A LARGE COPPER AREA TO HELP
POSSIBLE. CONNECT THE FEEDBACK-DIVIDER RESISTOR FROM FB TO THE OUTPUT AS CLOSE
POWER
COOL THE DEVICE.
4) PLACE THE MOSFETS AS CLOSE AS POSSIBLE TO THE IC TO MINIMIZE TRACE INDUCTANCE
3) PLACE THE INDUCTOR CURRENT-SENSE RESISTOR AND CAPACITOR AS CLOSE TO THE
MAX8544 SWITCHING FREQUENCY
LOCATION 3
AS POSSIBLE TO THE FARTHEST OUTPUT CAPACITOR.
INPUT 10.8V-13.2V
GROUND
ONLY CONNECTION
GROUND
TRACES FROM ACROSS THE CAPACITOR (LOCATION 2) TO CS_P AND CS_N.
SIGNAL
OF THE GATE-DRIVE LOOP.
LOCATION 2
LAYOUT GUIDE
BE BETWEEN 470KHZ-870KHZ.IF FSYNCIN_3P3 IS DRIVEN,IT MUSTSET TO 670KHZ DEFAULT.
FSYNCIN_3P3 INPUT OPTIONAL
REVISION LISTREVISION 0.5 INITIAL RELEASE.REVISION 0.51 COMPENSATION CIRCUIT RC NETWORK VALUES CHANGED.REVISION 0.52 REMOVED HARD REFDES ATTRIBUTES.
THE POWER GROUND PLANE AND THE SIGNAL GROUND PLANE. PLACE THE INPUT CERAMIC
THE HIGH SWITCHING CURRENT WITHIN THIS SMALL LOOP.MOSFET’S DRAIN AND THE LOW-SIDE MOSFET’S SOURCE. THIS IS TO HELP CONTAINDECOUPLING CAPACITOR DIRECTLY ACROSS AND AS CLOSE AS POSSIBLE TO THE HIGH-SIDE
1) PLACE IC DECOUPLING CAPACITORS AS CLOSE TO IC PINS AS POSSIBLE. KEEP SEPARATE
SEE LAYOUT GUIDE
+VIN
VRG_3P3V_LX
3P3F
B
3P3ILIM1
+3P3V_BUCK
0.1UF3P3SS
35.7K
VRG_3P3V_DH
24.9
K
EN_3P3_BUCK
1%+5VL3P3
270PF3P3CMP
100K
1%3P3ILIM2
200K
100U
F
100P
F
N_FET
VRG_3P3V_CS_P
1%
POK_3P3
10U
F
10U
F
10U
F
0.1U
F
MAX8544EEP 1%
N_FET
SYNCOUT_3P3
1%
1UF
0.82UH
VRG_3P3V_CS_N
3P3CMP4VRG_3P3V_DL
5%390K
8.06K 1%
10U
F
FSYNCFSYNCIN_3P3
VRG_3P3V_BST
100U
F
100U
F
100U
F
0.47
UF
0.47UF
5%51
0
5%
1%13.3K
510
100K
1%18
2K
-700 5.00Sun Aug 07 10:17:44 2005
14
18
17
16
510
11
122
1
4
3
19
6
15
20
8
13
9
7
U2A2 C2B
2
C2A
8
C2A
10R
8L6
1 2
R2A6R8L7
R2A
4
21D7
21D8
21D8
1
2
C1B
2
1
2
C2B
6
1
2
C1B
1
C2A
3
C2A
6
C2A
4
1
2
C2B
1
C1A
3
5 6 7 8
4
3 2 1
Q1B4
5 6 7 8
4
3 2 1
Q1A3
C8L5
1 2L1A1
1 2R2A7
1 2R2A10
R2A13
R2A8
C2A11
C2A7
R2A11
R8L
4
R2A
5
1 2C2B3
31
2
D8L
1
1
2
3
D8M1
68
2
A
B
C
D
2 1345
D
C
B
A
8 6 5 3
MODIFIEDSHEET
4 1
DRAWING REVBOARD REV
7
7
OUT
IN
S1S2S3
G
D4D3D2D1
S1S2S3
G
D4D3D2D1
OUT
IN
IN
OUT
CS_N
ILIM1
DL
CS_P
SYNCO
IN
EN
FSYNC
SS
COMP
ILIM2
GNDPGND
POK
MODE FB
LX
DH
BST
VL
Host Bus Adapter Schematics for Intel® 8134x I/O Processors 28
CLK_VIEW IS A LAN CLOCK
REVISION 0.5 INITIAL RELEASEREVISION 0.51 POP OPTION ON LAN PWR GOOD REMOVED.
GBE_82545GM_MODULE
TEST OUTPUT FOR IEEE PHYCONFORMANCE TESTING. THETWO PIN HEADER MAKES ITEASY TO CONNECT A PROBE
REPLACED GROUND_EARTH SYMBOL WITH GNDF.
REVISION HISTORY
NOTES
1. KEEP XTAL1 AND XTAL2 TRACES AS SHORT AS POSSIBLE.
REVISION 0.7 RENAMED MOST NON-PCI NETS AND A FEW PCI NETS.
ADDED LAYOUT NOTE.
MODIFICATION.REVISION 0.8 CORRECTED EEPROM NET CONNECTIONS DUE TO EEPROM SYMBOL
REVISION 0.9 CHANGED REFDES TO SOFT.
25M
HZ,
20PF
93C46
49.9
PCI_AD<44>
2.49
K
PCI_AD<8>
PCI_AD<11>
EMPTYHDR_1X2_TH
0
PCI_TRDY_NPCI_IRDY_NPCI_FRAME_N
PCI_CBE_N<7..0>
IDSELPCI_IDSEL 200 5%PCI_STOP_N
GBE_SMBDAT
PCI_GNT_NPCI_REQ_N
PCI_AD<3>
GBE_LINK1000_N
PCI_PERR_NPCI_SERR_NPCI_RST_N
PCI_CLKPCI_INTA_N
GBE_JTAG_TMSGBE_JTAG_TDOGBE_JTAG_TDIGBE_JTAG_TCKGBE_JTAG_RST_N
GBE_XTAL2GBE_XTAL1
GBE_SMBCLKGBE_SMBALRT_NGBE_SDP7GBE_SDP6GBE_SDP1GBE_SDP0GBE_SIG_DETECT 1K 1%
GBE_MDI3_NGBE_MDI2_PGBE_MDI2_NGBE_MDI1_PGBE_MDI1_NGBE_MDI0_PGBE_MDI0_N
GBE_LINK100_N
GBE_ACT_N
PCI_AD<28>PCI_AD<27>PCI_AD<26>
PCI_AD<12>
LINK_NACT_N
5%
0.1UF
300
5%
1M+3
_3V
5%
1%22
.6
100K
DS1
SMT
1M
22PF
49.9 1%
1%
0.01
UF
1
3
1%
300
1%
62
42434445464748
25
13
4
1
3
65
2
0
6160595857
5554
5150
41403938373635343332313029
24
21
19
63
1514
1211
87
23
6
181716
2827
22
20
26
5253
56
5
7
1%1K
1%2.
49K
1%
1%
4
22PF
0.01UF
10UF
5%
49.9 1%
LINK_1000_N
MAGJACK
0.1UF
1%
0.01
UF
5%
0.01UF
1%
0.01UF
+2_5V
1%49.9
8.2K
0.01
UF
0.1UF
1%
5%
300
109
PCI_AD<50>
PCI_AD<52>
PCI_AD<54>
PCI_AD<57>
PCI_CBE_N<4>PCI_CBE_N<3>PCI_CBE_N<2>
PCI_CBE_N<0>PCI_AD<63>PCI_AD<62>PCI_AD<61>PCI_AD<60>
PCI_AD<55>PCI_AD<56>
PCI_AD<20>PCI_AD<21>PCI_AD<22>
PCI_AD<31>
PCI_AD<35>
PCI_AD<29>
PCI_AD<25>PCI_AD<24>PCI_AD<23>
PCI_AD<18>
PCI_LOCK_N
PCI_DEVSEL_N
PCI_PAR64
PCI_AD<2>
PCI_AD<10>PCI_AD<9>
PCI_AD<7>PCI_AD<6>PCI_AD<5>PCI_AD<4>
PCI_AD<13>PCI_AD<14>PCI_AD<15>PCI_AD<16>PCI_AD<17>
PCI_AD<19>
PCI_AD<30>
PCI_AD<34>
PCI_AD<36>PCI_AD<37>PCI_AD<38>PCI_AD<39>PCI_AD<40>PCI_AD<41>PCI_AD<42>PCI_AD<43>
PCI_AD<45>PCI_AD<46>PCI_AD<47>PCI_AD<48>PCI_AD<49>
PCI_AD<51>
PCI_AD<53>
PCI_AD<59>
PCI_CBE_N<5>PCI_CBE_N<6>PCI_CBE_N<7>
PCI_AD<1>PCI_AD<0>
82545GM
5%
1.3M
5%
+3_3
V
+3_3
V
+3_3
V +3_3V
300
0.01UF
49.9
49.9
49.9
49.9
+3_3
V
+3_3
V
EMPTY
EMPTY
300 5%
5%30
0PCI_CBE_N<1>
PCI_AD<58>
49
PCI_AD<63..0>
PCI_PAR
+3_3V
2
GBE_REF
PCI_PME_N
GBE_ZN_COMP
35.7
GBE_AUX_PWR
GBE_LAN_PWR_GOODGBE_ZP_COMP
PCI_AD<33>PCI_AD<32>
GBE_EE_CS
GBE_EE_SK
GBE_EE_DIGBE_EE_DO
GBE_MDI3_P
PCI_M66EN
GBE_LINK_N
GBE_CLK_VIEW
MGJKT1AC
MGJKT4AC
PCI_ACK64_N
MGJKT2AC
PCI_REQ64_N
GBE_VIOGBE_VIO
MGJKT3AC
0.1UF
U2A1
5.00-700Sun Aug 07 10:41:31 2005
1B11A1
1A1
1A1
1A1
1A1
R2B
5
1
2
C3A
1
1
2
C2B
13R
3B2
R3A
1
R7M
7
R2B
7
1
2
C8L
4R8M
1
C2B8
C2B7
1 2C2B9
1 2C1C1
1 2C1C2
1 2C1C5
1 2R2B9
1 2R2B8
1 2R1C1
1 2R1C2
1 2R1C3
1 2R1C4
1 2R1C5
1 2R1C6
C1C4
C1C3
C1B4
C1L1
R9N1
1 2C9N3
R1B
1
P2P5P3
R18
V20
W20
U18
T16Y19W18V17
V19T17
A4A3A15A14
E11
T7W6Y5
V1
M20
M16
U4
V4W4V5U6V6
Y6
K16
F19
E12G5G4E20G19
K17
R5A17
F16E18E16E15E14E13D15B16F17F18G17G16B15D19D18C15D16C18D17H16G18J16H18J17J18
E3R3
Y20
E2C20C19B20D20
B2
C2
D2
U2Y16
U10V15
T6
Y15W14
W12T12V12U12Y14V13T13
Y12V11T11Y11W10
U8Y7
V7
Y3
V3
L16
M19
M18M17N20N16P20N18P19P16R20P18P17T20R16U20
T19
T18
V18U16
P1P4
T2
Y1
V14T14
V16Y4T8
V10Y13
A16
Y10T10
V9Y8
H20K18C17F20
G20
A8
T4
E1
N4N3B1
C1
D1
Y9Y2
T5
N1M1
T9W2T3U14W16
V8W8
Y18Y17T15
N5
U2B1
21
R7M
8
1B1
1B1
21
R2B
6
1B1
1A1
1A1
1A1
1A1
1A1
1A1
1A1
1A1
1A1
1A1
1A1
1A1
1A1
1A1
1A1
1A1
1A1
1 2
J2C1
R2C1
4 321
Y2B1
R2B1
11
12
10
4
6
5
3
1
2
8
7
9
17
18
15
16
14
13
J1C1
12
DS2
B1
R1B4
21R1B5
21R1B3
R1B2
R2B
3
1 2R8L3
432
56781
68
2
A
B
C
D
2 1345
D
C
B
A
8 6 5 3
MODIFIEDSHEET
4 1
DRAWING REVBOARD REV
7
7
CS VCCDC
ORGGND
SKDIDO
O
O
O
O
O
O
OOO
O O O
O
O
O
O
O
OO
RJ45-8
1000 PF
RJ45-1
2KV
75
RJ45-7
RJ45-5
RJ45-4
RJ45-6
75
75
75
RJ45-3
RJ45-2
O
LED1C
LED1A
LED2B
LED2A
SH2
SH1
T4C
T4B
T4A
T3C
T3B
T3A
T2C
T2B
T2A
T1C
T1B
T1A
XTL1
NC1
NC
2
XTL2
INIOIOIOIOIOIO
IOIO
IOIO
IOINININ
IN
IOIO
INIO
IOIOIOIO
IOIO
JTAG_RST_NCBE7_NCBE6_NCBE5_N
IRDY_NFRAME_N
ACK64_NREQ64_N
GNT_NREQ_N
DEVSEL_N
LINK_NACT_N
RST_N
INTA_NLOCK_N
MDI2_N
MDI1_N
MDI0_NLINK1000_N
LINK100_N
MDI3_N
PME_N
TEST_N
RX_N
TX_NFL_WE_NFL_OE_NFL_CS_N
TRDY_NSTOP_N
SERR_NPERR_N
SMBALRT_N
CBE0_NCBE1_NCBE2_NCBE3_NCBE4_N
PCI_AD0PCI_AD1
VIO0
ZN_COMP
JTAG_TDIJTAG_TCK
PCI_AD59PCI_AD58
PCI_AD53
PCI_AD51
PCI_AD49PCI_AD48PCI_AD47PCI_AD46PCI_AD45PCI_AD44PCI_AD43PCI_AD42PCI_AD41PCI_AD40PCI_AD39PCI_AD38PCI_AD37PCI_AD36
PCI_AD34
PCI_AD32
PCI_AD30
PCI_AD28
PCI_AD19
PCI_AD17PCI_AD16PCI_AD15PCI_AD14PCI_AD13PCI_AD12PCI_AD11
PCI_AD4PCI_AD5PCI_AD6PCI_AD7PCI_AD8PCI_AD9PCI_AD10
PCI_AD3PCI_AD2
IDSEL
PAR64PAR
M66ENCLK
MDI2_P
MDI1_P
MDI0_P
EE_SKEE_DOEE_DIEE_CS
MDI3_P
VIO1
AUX_PWRREF
FL_DATA5FL_DATA4FL_DATA3FL_DATA2FL_DATA1FL_DATA0
FL_ADDR18FL_ADDR17FL_ADDR16FL_ADDR15FL_ADDR14FL_ADDR13FL_ADDR12FL_ADDR11FL_ADDR10
FL_ADDR9FL_ADDR8FL_ADDR7FL_ADDR6FL_ADDR5FL_ADDR4FL_ADDR3FL_ADDR2FL_ADDR1FL_ADDR0
LAN_PWR_GOODZP_COMP
FL_DATA6
RX_PSIG_DETECT
SDP0SDP1SDP6
TX_P
FL_DATA7
PCI_AD18
PCI_AD23PCI_AD24PCI_AD25PCI_AD26PCI_AD27
PCI_AD29
PCI_AD35
PCI_AD33
PCI_AD31
PCI_AD22PCI_AD21PCI_AD20
SDP7
SMBCLKSMBDATA
XTAL1XTAL2
PCI_AD56PCI_AD55
PCI_AD60PCI_AD61PCI_AD62PCI_AD63
PCI_AD57
PCI_AD54
PCI_AD52
PCI_AD50
CLK_VIEWJTAG_TMSJTAG_TDO
IO
IO
OUTIN
INININ OUT
Host Bus Adapter Schematics for Intel® 8134x I/O Processors 29
CHANGED REFDES TO SOFT.REVISION 0.9 REMOVED EXTERNAL +2.5V AND +1.5V INPUT OPTION.
REVISION 0.7 REPLACED 1.5 POWER TRANSISTOR WITH BCP69-16.REVISION 0.5 INITIAL RELEASE
REVISION HISTORY
RENAMED POWER PLANE NETS.
GBE_82545GM_MODULE
NOTES:
1W
EMPTY
+1_5V
4.7U
F
0.01
UF
1 1%
+3_3V
+3_3V
5.1K
0.01
UF
0.01
UF
4.7U
F
10U
F
10U
F
10U
F
10U
F
10U
F
10U
F
10U
F
0.01
UF
0.01
UF
0.01
UF
10U
F
+3_3V
4.7U
F
0.01
UF
82545GM
BCP69T1
0.01
UF
4.7U
F
0.01
UF
0.01
UF
0.01
UF
10U
F
0.01
UF
10U
F
+2_5V
0.01
UF
GBE_CNTRL_2P5GBE_CNTRL_1P5
10U
F
5%5%
5.1K
EMPTY
BCP69-16
PNP2_E_1P5
-700 5.00Sun Aug 07 10:41:32 2005
G7G8G9G12
P7N14
P8
P12P9
P13
F2A18
P14
N13N8
M14N7
M7
H7
G13G14
H8
J14J7H14H13
U15U11
U19W1W5
W13W9
W17
B4F1
A19G1G2
L2G3
L5L18
U7
B14
C10B19
C16
D11D6
E17
L17M2
R17R4
N19
U3U1
B8
H19H4
U2B1
1
2
C8M
10
1
2
C2C
5
1
2
C8L
7
1
2
C2C
4
1
2
C8L
9
1
2
C2C
3
1
2
C8L
6
1
2
C8M
5
1
2
C8M
9
1
2
C2C
2
1
2
C8L
8
1
2
C2C
1
1
2
C8M
4
1
2
C8M
6
1
2
C2C
6
1
2
C2B
10
1
2
C8L
10
1
2
C8M
2
1
2
C8M
8
1
2
C8M
7
1
2
C2A
2R2A
2R
2C3
C2B
14
1
2
C2A
13
C8M
3
C2A
5
C2C
7
1
2
C8N
1 1
342
Q2A1
1
342
Q2C1
R2A1
1
2
C8N
2
68
2
A
B
C
D
2 1345
D
C
B
A
8 6 5 3
MODIFIEDSHEET
4 1
DRAWING REVBOARD REV
7
7
VDDO_3.3V8VDDO_3.3V9
VDDO_3.3V0
VDDO_3.3V15VDDO_3.3V16
VDDO_3.3V12VDDO_3.3V13VDDO_3.3V14
VDDO_3.3V11VDDO_3.3V10
VDDO_3.3V7
VDDO_3.3V5VDDO_3.3V6
VDDO_3.3V4
VDDO_3.3V2VDDO_3.3V3
VDDO_3.3V1
VDDO_3.3V17
AVDDL_2.5V6AVDDL_2.5V5
AVDDL_2.5V3AVDDL_2.5V4
AVDDL_2.5V2AVDDL_2.5V1AVDDL_2.5V0
AVDDH_3.3V1AVDDH_3.3V0
VDDO_3.3V25
VDDO_3.3V23VDDO_3.3V24
VDDO_3.3V22VDDO_3.3V21VDDO_3.3V20
VDDO_3.3V18VDDO_3.3V19
DVDD_1.5V8DVDD_1.5V9
DVDD_1.5V10DVDD_1.5V11
DVDD_1.5V7
DVDD_1.5V5DVDD_1.5V4
DVDD_1.5V6
DVDD_1.5V12
DVDD_1.5V14DVDD_1.5V13
DVDD_1.5V15DVDD_1.5V16
DVDD_1.5V23
CTRL_15CTRL_25
DVDD_1.5V22
DVDD_1.5V20DVDD_1.5V21
DVDD_1.5V19
DVDD_1.5V17DVDD_1.5V18
DVDD_1.5V3DVDD_1.5V2DVDD_1.5V1DVDD_1.5V0
Host Bus Adapter Schematics for Intel® 8134x I/O Processors 30
REVISION HISTORY
REVISION 0.9 CHANGED REFDES TO SOFT.REVISION 0.5 INITIAL RELEASE.
CONNECT CAPACITORS BETWEEN CHASSIS GROUND AND SIGNAL GROUND ON BOTHSIDES OF MAGNETICS MODULE.
CHIP AS POSSIBLE.
GBE_82545GM_MODULE
THEM EVENLY AROUND THE 82545 GM CONTROLLER.AT A MINIMUM, USE 1 BULK CAP AND 1 HIGH FREQUENCYCAP PER SIDE OF THE CHIP. PLACE CAPS AS CLOSE TO THE
USE DECOUPLING CAPACITORS GENEROUSLY, PLACING
RESRVD_2930
RESRVD_2728
0.01
UF
4.7U
F
1000
PF
0.01
UF
10U
F
1%1K
1%1K
0.01
UF
0.01
UF
0.01
UF
0.01
UF
0.01
UF
1000
PF
1000
PF
10U
F
1000
PF
4.7U
F
RESRVD_2930
RESRVD_2728
82545GM
+3_3V
+3_3V
0.01
UF
-700 5.00Sun Aug 07 10:41:33 2005
1
2
C2A
12
1
2
C2B
4
1
2
C2B
12
1
2
C3B
2
1
2
C2B
5
1
2
C8M
1
1
2
C2B
11
1
2
C3B
1C
9M5
C9M
4
C9M
6
C9M
3
C9M
2
R2B
4
C9N
1
C9M
1
C9N
2
R2B
2
A1
B3B6
B11B17
C3D3D8
D14E19
F3G10G11
H2H9
H10H11H12H17
J8J9
J10J11J12J13
K2K4K5K7K8K9
K10K11K12K13K14
L7L8L9
L10L11L12L13L14L19
M4M8M9
M10M11M12M13
N9N10
U9U13U17
N11N12N17P10P11
R2R19
U5
V2W3W7
W11W15W19
A12C13C14D12D13F4
A11C12B13B12A13
F5
J5J4J3J2J1H5H3H1
J19J20K1K3K19K20L1L3L4M3N2T1D4D5C4E4C5E5B5E6D7C7E10B7A7C8E8E9D9C9B9D10A9C11B10C6A20
L20R1A6E7M5B18
A10A5A2
U2B1
68
2
A
B
C
D
2 1345
D
C
B
A
8 6 5 3
MODIFIEDSHEET
4 1
DRAWING REVBOARD REV
7
7
GND1GND2GND3
RESERVED25RESERVED26RESERVED27RESERVED28RESERVED29RESERVED30
RESERVED24RESERVED23RESERVED22RESERVED21RESERVED20RESERVED19RESERVED18RESERVED17RESERVED16RESERVED15RESERVED14RESERVED13RESERVED12RESERVED11RESERVED10
RESERVED9RESERVED8RESERVED7RESERVED6RESERVED5RESERVED4RESERVED3RESERVED2RESERVED1RESERVED0
NC31NC30NC29NC28NC27NC26NC25NC24NC23NC22NC21NC20
NC12NC13NC14NC15NC16NC17NC18NC19
NC11
NC0NC1NC2NC3NC4
NC10NC9NC8NC7NC6NC5
GND73GND72GND71GND70GND69GND68
GND64GND63GND62GND61GND60GND59GND58GND57
GND67GND66GND65
GND56GND55GND54GND53GND52GND51GND50GND49GND48GND47GND46GND45GND44GND43GND42GND41GND40GND39GND38GND37GND36GND35GND34GND33GND32GND31GND30GND29GND28GND27GND26GND25GND24GND23GND22GND21GND20GND19GND18GND17GND16GND15GND14GND13GND12GND11GND10GND9GND8GND7GND6GND5GND4
GND0
Host Bus Adapter Schematics for Intel® 8134x I/O Processors 31
NO
CO
NN
EC
T TO DEVICE CONNECTIONS
DECOUPLING CAPACITORS
NOTES
FLASH - 8M
0.051 NAMED UNNAMED STS NET
0.01 INIAL DRAFTREVISION LIST
SEE 8.2 OF FLASH DATASHEET
PLACE AS CLOSE AS POSSIBLE
0.052 CHANGED FLASH PART VERSION0.053 CHANGED C1 & C2 PART VERSION
0.05 INITIAL RELEASE
3/11 CHANGED DOT SIZE0.055 CHANGED VCC & ADDED TITLE0.054 CHANGED FLASH NAME PER DAN
PU_STS
2
PBI_POE_NPBI_RSTOUT_N
PBI_PWE_N
PBI_A<24..0>
6
21
12
14 +3_3V
+3_3V
PBI_PCE0_N
16
0.1U
F
0.1U
F
17
109
23
20
22
4
1110
BYTE_WIDTH_N
5
3
2K
0
14131211
1
987654321
0
87
+3_3V
15
1918
15
5%
PBI_D<15..0>
13
28F640J3C120
24
5.00-700Fri Apr 21 08:59:19 2006
F1B8H1B4F8D4
G8
A1G2
C3
H8G1
A4
A8C8C7B7A7D8D7C5B5A5C4D3
B3A3C2A2D2D1
B1
B6C6D5D6E6
H6H4
F6F7H2
B2G4H3A6
E8E7G7H5F5F4
E3E1H7
F3
G6G5E5E4G3E2F2
C1
U7D1
1C7 1C7
1C7
1C7
1C7
1C7
12
R3P
1
1C81
2C3P
2 1
2
C3P
1
68
2
A
B
C
D
2 1345
D
C
B
A
8 6 5 3
MODIFIEDSHEET
4 1
DRAWING REVBOARD REV
7
7
IN
IN
INININ
IOIN
A3
D0D1D2D3D4D5D6
D10
D7D8D9
D11D12D13D14D15STS
VCC1VCC2VCCQVSS1
RFU1RFU2RFU3
VSS2VSS3
RFU4RFU5RFU6RFU7RFU8
A2
A4A5A6A7A8A9
A11A12A13A14A15A16A17A18A19A20A21A22
VPEN
A23_NCA24_NC
A10
A0A1
WE_N
RP_NOE_NCE0_NCE2_NCE1_NBYTE_N
Host Bus Adapter Schematics for Intel® 8134x I/O Processors 32
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Host Bus Adapter Schematics for Intel® 8134x I/O Processors 33
DISTRIBUTE CAPACITORS ALONG CONNECTORS
REVISIONS
PBI AUXILARY CONNECTOR
0.1: RELEASE FOR DESIGN REVIEW0.2: ADDED BATTERY CONTROL SIGNALS
RENAMED VBATT, PBI_SMBCLK & PBI_SMBDAT SIGNALS0.3: RENUMBERED 2X25 HEADER PINS
CHANGED POLARITY OF PBI_AUX_CE AND PBI_NVSRAM_CE1.0: ADDED BBU BUS1.1: ECO5: RENAMED PBI_XINT<7..6> TO PBI_XINT_N<7..6>1.2: CHANGED POLARITY OF BATT_PRSNT TO LOW ACTIVE BATT_PRSNT_N.
BATT_ENABLE
PBI_GPIO<7..0>PBI_NCBATT_DISCHRG
BATT_PRSNT_N
DDR_MISC<3..0>
+3_3V
+3_3V
+3_3V
+3_3V
+1_8V
HDR_2X25_TH
PBI_A<24..0>
PBI_I2C_SDA<2..0>PBI_I2C_SCL<2..0>
PBI_XINT_N<7..6>FLASH_16B_8BPBI_PWE_NPBI_POE_NPBI_AUX_CE_NPBI_NVSRAM_CE_N
PBI_PCE_N<1..0>
PBI_CKE<1..0>
PBI_CLK<1..0>WARM_RST_N
12
7
0
PBI_RSTOUT_N
16
0
6
HDR_2X25_TH
3
10
10
14
14
VBATT_1P8V
0.1U
F
+3_3V
0.1U
F
0.1U
F
0.1U
F
0.1U
F
0.1U
F
0.1U
F
0.1U
F
2
1
0
1
0
1
1
2
012
43
56789
111213
15
17
192021222324
0
01
2345
67
+12V
1
23
45
67
89
1011
13
15
PBI_D<15..0>
BATT_CHRG
1
SMBCLKSMBDAT
18
0
2
PE_RST_N
-700 5.00Fri Aug 05 14:05:34 2005
1B8
1B8
1B8
1C8
1B8
1B8
246
2422
8101214161820
26
464442
28303234363840
4850
31
579
23211917151311
25
454341393735
4947
33312927
J1P2
246
2422
8101214161820
26
464442
28303234363840
4850
31
579
23211917151311
25
454341393735
4947
33312927
J1P1
1B8
1B8
1B8
1
2
C3P
3
1
2
C2N
1
1
2
C2P
2
1
2
C1N
2
1
2
C2N
3
1
2
C2P
1
1
2
C2N
2
1
2
C1P
1
1B8
1B8
1B8
1B8
1B8
1B8
1B8
1B8
1B8
1B8
1B8
1B8
1B8
1B8
68
2
A
B
C
D
2 1345
D
C
B
A
8 6 5 3
MODIFIEDSHEET
4 1
DRAWING REVBOARD REV
7
7
OUT
IN
INININ
IN
IN
IN
INININ
IOOUT
OUTOUTIN
IO
OUT
IO
IO27293133
4749
353739414345
25
11131517192123
975
13
5048
40383634323028
424446
26
201816141210
8
2224
642
27293133
4749
353739414345
25
11131517192123
975
13
5048
40383634323028
424446
26
201816141210
8
2224
642
IOIO
IN
IN
IOIO
Host Bus Adapter Schematics for Intel® 8134x I/O Processors 34
REVISION HISTORY:
CPLD VERSION A MODULE
LAYOUT NOTE:PLACE THE DEBUG LEDS IN LINE <7..0>DEBUG LED ARRAY
0.50 - PRELIM VERSION0.51 - REVIEW F/B IMPLEMENTED
0.53 - HARD REFDES - DAN0.54 - ALL LOCATION REFDES FIXED0.55 - CPLD SIGNAL ASSIGNMENT MODIFIED.0.56 - CPLD SIGNAL ASSIGNMENT MODIFIED.
0.58 - CHANGED BATT_PRSNT POLARITY TO LOW ACTIVE.0.57 - CHANGE RES TO 0603, COSMETICS.
0.52 - ADDED 0OHM TO SL_GPIOS
0.59 - CHANGED 7 SEGEMT LED TO LTS-3367C-T FOR LEAD FREE PROCESS CAPABLE.0.60 - CHANGED 3 TRANSISTORS TO 2N7002 (FET) INSTEAD OF 3906 (BJT)
CPLD_TCK
5%
CC_DISP_LOW
CC_DISP_HIHEX_DSP_SEG_FHEX_DSP_SEG_EHEX_DSP_SEG_DHEX_DSP_SEG_C
HEX_DSP_SEG_G
HEX_DSP_SEG_BHEX_DSP_SEG_A
470
LED
_YLW
BATT_PRSNT_NROT_SW1
NVRAM_CS_N
ROT_SW1ROT_SW2ROT_SW3
PBI_A<19..16>
ROT_SW3
BUZZER_CRTL
PBI_RST_N
CPLD_TMSCPLD_TDOCPLD_TDI
PBI_A<17>
PBI_A<18>
CPLD_GPIO1
PBI_AUX_CE_N
PBI_D<4>PBI_PCE_N1
PBI_PWE_NPBI_D<7>PBI_D<3>
CPLD_GPIO2CPLD_GPIO4CPLD_GPIO0BATT_DISCHRGBATT_CHRGCPLD_GPIO3BATT_ENABLELED_ARRAY_CRTLPBI_D<6>
PBI_D<5>HEX_DSP_SEG_BPBI_D<0>PBI_D<1>
HEX_DSP_SEG_DP
NVRAM_CS_NDISP_HI_CRTLHEX_DSP_SEG_ADISP_LO_CRTLHEX_DSP_SEG_GHEX_DSP_SEG_EHEX_DSP_SEG_FHEX_DSP_SEG_D
ROT_SW2PBI_A<19>
ROT_SW0PCI_CLKPBI_A<16>
HEX_DSP_SEG_C
LC4064Z_M56C
5%00 5%
0 5%0 5%0 5%
470
5%5%47
05% 5%
470
5%47
047
0
5%
8.2K
5%
8.2K
5%8.
2K
5%8.
2K
PBI_RST_N
BATT_CHRG
BATT_ENABLE
BATT_DISCHRG
PCI_CLK
PBI_POE_N
PBI_PCE_N1
PBI_AUX_CE_N
PBI_D<7..0>
PBI_PWE_N
CPLD_TCK
CPLD_TDI
CPLD_TMS
CPLD_TDO
+3_3V
3
LED
_YLW
0.1U
F
0.1U
F
+3_3V
LED
_YLW
LED
_YLW
LED
_YLW
LED
_YLW
LED
_YLW
LED
_YLW
+3_3V
+1_8V
0421
94HAB16W
BATT_PRSNT_N
PBI_POE_N
5%
470
5%
+3_3V
PBI_D<2>
SL_GPIO<4..0>
BUZZER_CRTL
470
LTS_3367C_T
LTS_3367C_T
ROT_SW0
2N7002DISP_HI_CRTL
2N7002DISP_LO_CRTL
2N7002
CC_DBG_LED
LED_ARRAY_CRTL
-700 5.00Tue Jul 18 15:26:15 2006Tue Jul 18 15:26:15 2006
12
DS1
A6
12
DS1
A7
12
DS1
A8
1436
52
SW2D1
1C8
C1
C5K6H6A5
B10
F8F10
K3
F1G3G1H1K4H4H5K5
D1
A4A3A2A1C3
C4
K2A9F3E8
E10D8D10C10A7C7C6A6
H7K7K8K9K10H8H10G10
H3C8G8D3
J1E1E3A8
J10A10B1K1
U9C2
Q1B1
Q1B3
Q1B2
1
2
C1N
1
1
2
C9C
2
12
DS1
A9
1D8
1 2R9C71 2R9C8
1 2R9C31 2R9C2
1 2R9C4
3
42
5
108
1
9
76
DS36
3
42
5
108
1
9
76
DS37
12
R9L
41
2R
9L5
12
R9L
61
2R
9L7
12
R9L
81
2R
9L9
12
R9L
10
12
R9L
11
12
R3D
21
2R
2D5
12
R3D
41
2R
2D1
1C8
1C8
1C8
1C8
1D8
1C8
1C8
1C8
1D8
1D8
1C8
1D8
1C8
1C8
1C8
1C8
1C8
12
DS1
A2
12
DS1
A3
12
DS1
A4
12
DS1
A5
68
2
A
B
C
D
2 1345
D
C
B
A
8 6 5 3
MODIFIEDSHEET
4 1
DRAWING REVBOARD REV
7
7
IN
IN
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IO
IN
IN
IN
7-SEG DISPLAY
DP_CDP_A
CC
A
CB
D
FE
G
7-SEG DISPLAY
DP_CDP_A
CC
A
CB
D
FE
G
OUT
G
S
D
G
S
D
G
S
D
LC40
64Z_
M56
C
TCKTDITDOTMS
IN_4IN_5IN_6IN_7
GND3GND2GND1GND0
C11C10
C8C6C4C2C1C0
D0/GOE1D2D4D6D8
D10D12D15
VCC_B1VCC_B0VCC1VCC0
A0/GOE0
A8A6A4A2A1
A11
B0B2B4B6B8B10B12B15
IN_0
IN_2IN_1
IN_3
CLK0/ICLK1/ICLK2/ICLK3/I
A10
OUT
ROTARY SWITCH
C0C1
B8B4B2B1
Host Bus Adapter Schematics for Intel® 8134x I/O Processors 35
AUDIO ALARM LOUD
REVISION LIST
0.01 INITIAL DRAFT 10/11/04
BUZZER
2 & 3
SETTINGS
NC AUDIO ALARM OFF
PINS
AUDIO ALARM QUIET
1 & 2
BUZ_QUIET
PWR
5%
121
ON_OFF5%
10K
HDR_1X3_TH
BUZZER_SO_DMT1233SMT
1K
BUZZER_CTRL
5%
1%
1%22
.1
BUZ_LOUD
BU
Z_P
WR
0
+3_3V
-700 5.00Mon Mar 20 09:38:25 2006
1D8 1 2R2D3
21
R2D
7
21
R2D
4
12
3
Q2D1
21
R2D
2
31
2
J2D5
2
1LS2D1
21
R2D
6
68
2
A
B
C
D
2 1345
D
C
B
A
8 6 5 3
MODIFIEDSHEET
4 1
DRAWING REVBOARD REV
7
7
VCC
GND
C
E
BIN
Host Bus Adapter Schematics for Intel® 8134x I/O Processors 36
0.6 CHANGED NET NAMES 8/04/050.5 MADE ALL REFDES SOFT 3/21/05
REVISION LIST0.01 INITAL DRAFT 10/7/040.2 GROUNDED PIN 2 3/2/05
RS232_DUAL_MOD
U_RXD<1..0>U_CTS_N<1..0>
1UF 0.
1UF
+3_3V
EN_N
RJ11_SINGLE
1UF
10K
1UF
1UF
U_RTS_N<1..0>
1
U_TXD<1..0>
RJ11_SINGLE
10K
0
U_VN
NC
5%
1
0
1
U_C1P
U_C1N
U_C2N
NC
NC
NC
U_VP
0
RS232BUFF_561
U_C2P
5%
1
0
SHDN
UART0_TXD_NUART0_RXD_NUART0_RTSUART0_CTS
UART1_TXD_NUART1_RXD_NUART1_RTSUART1_CTS
-700 5.00Sat Dec 24 14:42:48 2005
10251823274928132
171311
192226
58
2120
67
16151412
24
U1D1
2
43
1
65
J1C3
1B6
1B6
1
2
C9P
2
2
43
1
65
J1D1
21
R1D
2
21
R1D
1
1B6
1B6
1
2
C1D
3
1
2
C1D
2 1
2
C1D
1
1 2C9P1
68
2
A
B
C
D
2 1345
D
C
B
A
8 6 5 3
MODIFIEDSHEET
4 1
DRAWING REVBOARD REV
7
7
ININ
RTSCTS
NC0
TXDRXD
NC1
OUTOUT
IN
RTSCTS
NC0
TXDRXD
NC1
IN
EN_N
C1+C1-C2+C2-T1inT2inT3inT4inR1outR2outR3outR4outR5out
VCCV+V-
T1outT2outT3outT4out
R1inR2inR3inR4inR5inSHDN
GND
Host Bus Adapter Schematics for Intel® 8134x I/O Processors 37
0.56: MORE RESISTORS CHANGED TO 0402
0.61: MOVED TRST_N PULL-DOWN RESISTOR TO MR_N RESET INPUT.0.62: CHANGED MR_N RESET RESISTOR TO EMPTY.
0.80: ADDED DECOUPLING CAP FOR 74LVC1G58 DEVICES. CHANGED TRST_GBE_N TO GBE_TRST_N.0.81: MINOR TEXT UPDATES.
0.70: CHANGED CHAIN ORDER TO SL-->GBE-->CPLD. ADDED IOP ONLY OPTION.
0.60: ADDED PULL-DOWN OPTION TO TRST_N.
0.55: MORE RESISTORS CHANGED TO 04020.54: JTAG_CONN UPDATED0.53: CHANGED 0 OHM RESISTORS TO 0402.0.52: HARD REFDES. FUSE_SMT UPDATED.
CHAIN ORDER CHANGED TO CPLD-->GBE-->SL0.51: COVERTED TO SINGLE JTAG CONNECTOR0.50: FIRST RELEASE
INSTALL MR_N PULL-DOWN RESISTOR
AND LOW. REMOVE THIS RESISTOR FOR
OPEN COLLECTOR OUTPUTS.
8134x
AR
JTAG_CONN_MODULE
GIG-ETHERNET
USE WITH JTAG DEBUGGERS WITH
THAT DRIVE THE JTAG SIGNALS HIGHFOR USE WITH JTAG DEBUGGERS
CPLD
REVISION HISTORY
0.90: 8/9/06 (DSH): ECO# 505468: ADDED VOLTAGE DIVIDER ON VCC PIN TO ACCEPT 1.8V LEVELS FROM CPLD.
STUFF RESISTOR "RA" TO COMPLETE THE JTAG CHAIN DURING PRE-SILICON TESTING.
PLACE DECOUPLING CAP NEAR VCC PINS FOR ALL THREE 74LVC1G58 DEVICES.
ECO# 505468: ADDED VOLTAGE DIVIDER ON VCC PIN TO ACCEPT 1.8V LEVELS FROM CPLD.JUMPER OPEN FOR IOP ONLY IN JTAG CHAIN (DEFAULT).JUMPER SHORTED FOR IOP, GBE AND CPLD IN JTAG CHAIN.
EMPTY
5%
IOP_TDO_N
CPLD_TDO
TMS
0
HDR_2X5_SMT
5%
FUS
E_7
50M
A
TCK
CPLD_TDI
5% 10K
+3_3V
EMPTY
0 5%
5%
GBE_TDI
IOP_TDO
+3_3V
+3_3V
IOP_TDI
5% 10K
IOP_TDO_N
5%
+3_3V
5%
10K
TRST_N
JTAG_SELCPLD_TDO
5%4.7KMR_N
+3_3V
VREF
10K
0
74LVC1G58
MAX811EUS
JTAG_TDOSRST_N
HDR_1X2_TH
+3_3V
RST_OUT_N
4.7K
GBE_TDO
JTAG_TDO
74LVC1G58
+3_3V
GBE_TRST_N
74LVC1G58
+3_3V
TRST_N
VCC_2P720.1UF5%1K
5%4.7K
-700 5.00Fri Aug 11 15:24:09 2006
12
F2C
11A6
1A62468
10
13579
J3C1
12
R7N
3
12
R8N
2
12
R6P
1
12
R3C
1
3
21
4U3C1
1 2R3C3
3
52
41
6
U7N2
1 2
J3C2
12
R3C
2
3
52
41
6
U8N1
3
52
41
6
U7N1
1 2C8N3R7N2
R7N6
1A6
1A6
1A6
12
R8N
31
2R
8N1
1 2R7N1
68
2
A
B
C
D
2 1345
D
C
B
A
8 6 5 3
MODIFIEDSHEET
4 1
DRAWING REVBOARD REV
7
7
IN
OUT
IN
OUTOUT
IN
OUT
OUT
OUT
SHORT PIN 6 TO GNDFOR BUFFER B->YSHORT PIN 6 TO VCCFOR INVERTER A->Y
SEL
AY
GND
VCC
B
SHORT PIN 6 TO GNDFOR BUFFER B->YSHORT PIN 6 TO VCCFOR INVERTER A->Y
SEL
AY
GND
VCC
B
SHORT PIN 6 TO GNDFOR BUFFER B->YSHORT PIN 6 TO VCCFOR INVERTER A->Y
SEL
AY
GND
VCC
B
VCC
GND RST_N
MR_N
TDITDO
SRST_NTRST_N
TCK
VREFGND2GND1TMSGND0
OUTOUT
Host Bus Adapter Schematics for Intel® 8134x I/O Processors 38
THE GROUND-PLANE LAYER.
GROUND AND CHANNELING HEAT AWAY. CONNECT THE
THE PACKAGE BY PROVIDING A DIRECT HEAT CONDUCTIONUNDERSIDE. THIS PAD LOWERS THE THERMAL RESISTANCE OF
PATH FROM THE DIE TO THE PC BOARD.
1.31A
+VIN
3.3V
1.5V
2.5V
REVISION 0.51.
REVISION
1 THE PACKAGE FEATURES AN EXPOSED THERMAL PAD ON ITS
LAYOUT GUIDE
2.0A
USING A LARGE PAD OR GROUND PLANE, OR MULTIPLE VIAS TOEXPOSED BACKSIDE PAD AND GND TO THE SYSTEM GROUND
FUNCTION OF PROVIDING AN ELECTRICAL CONNECTION TO SYSTEMADDITIONALLY, THE GROUND PIN (GND) PERFORM THE DUAL
(GUARANTEED LIMIT)
MAX OUTPUT CURRENT
0.81A
VIN RANGE ( 1.425V TO 3.6V)
VREG +1P2V_LINEAR (NOT POPULATED)
EMPT
Y
EMPT
YEM
PTYEMPTY
EMPT
Y
10U
F
1%4.
99K
1%6.
98K
2.2U
F
MAX8526EUDEN_1P2_LIN
+VIN +1P2V_LIN
1P2LI_FB
-700 5.00Fri Dec 23 18:13:58 2005
101112
81
7
432
9
6
5 13
14
15
U4D2
R4D
2R
4D3
C4D
5
2D7
1
2
C3D
26
68
2
A
B
C
D
2 1345
D
C
B
A
8 6 5 3
MODIFIEDSHEET
4 1
DRAWING REVBOARD REV
7
7
OUT
IN
IN
EDP_GND
NC3
OUT4IN4
NC1
FB
IN1IN2IN3
NC2
EN GND
OUT3OUT2OUT1
Host Bus Adapter Schematics for Intel® 8134x I/O Processors 39
+VIN
EXPOSED BACKSIDE PAD AND GND TO THE SYSTEM GROUND
FUNCTION OF PROVIDING AN ELECTRICAL CONNECTION TO SYSTEMVIN RANGE 2V TO 3.6V)
MAX OUTPUT CURRENT
2.0A (GUARANTEED LIMIT)
1.13A
1.
LAYOUT GUIDE
3.3V
2.5V
USING A LARGE PAD OR GROUND PLANE, OR MULTIPLE VIAS TO
ADDITIONALLY, THE GROUND PIN (GND) PERFORM THE DUALPATH FROM THE DIE TO THE PC BOARD.
UNDERSIDE. THIS PAD LOWERS THE THERMAL RESISTANCE OFTHE PACKAGE FEATURES AN EXPOSED THERMAL PAD ON ITS
THE PACKAGE BY PROVIDING A DIRECT HEAT CONDUCTION
GROUND AND CHANNELING HEAT AWAY. CONNECT THE
THE GROUND-PLANE LAYER.
REVISION 0.51 ADDED NO_BACKANNOTATE ATTRIBUTE.REVISION 0.5 INITIAL RELEASE.
REVISION HISTORY
VREG 1P8V LINEAR (NOT POPULATED)
+VIN
EN_1P8_LIN
+1P8V_LIN
1P8LI_FB
MAX8526EUD
2.2U
F 1%13
K1%
4.99
K
10U
F
EMPT
YEM
PTY
EMPT
Y
EMPTY
EMPT
Y
-700 5.00Fri Dec 23 18:31:11 2005
101112
81
7
432
9
6
5 13
14
15
U4D3
R6P
4R
6P5
C4D
192D6
C4D
18
68
2
A
B
C
D
2 1345
D
C
B
A
8 6 5 3
MODIFIEDSHEET
4 1
DRAWING REVBOARD REV
7
7
OUT
IN
IN
EDP_GND
NC3
OUT4IN4
NC1
FB
IN1IN2IN3
NC2
EN GND
OUT3OUT2OUT1
Host Bus Adapter Schematics for Intel® 8134x I/O Processors 40
SEE LAYOUT GUIDE
7.2A MAX OUTPUT
SEE LAYOUT GUIDELOCATION 3
1) PLACE IC DECOUPLING CAPACITORS AS CLOSE TO IC PINS AS POSSIBLE. KEEP SEPARATE
3) PLACE THE INDUCTOR CURRENT-SENSE RESISTOR AND CAPACITOR AS CLOSE TO THEINDUCTOR AS POSSIBLE. MAKE A KELVIN CONNECTION TO MINIMIZE THE EFFECT OFPC BOARD TRACE RESISTANCE. PLACE THE INPUT BIAS BALANCE RESISTOR AND BYPASSCAPACITOR (LOCATION 1) NEAR CS_N. RUN TWO CLOSELY PARALLELTRACES FROM ACROSS THE CAPACITOR (LOCATION 2) TO CS_P AND CS_N.PLACE THE DECOUPLING CAPACITOR (LOCATION 3) CLOSE TO CS_P AND CS_N PINS.
4) PLACE THE MOSFETS AS CLOSE AS POSSIBLE TO THE IC TO MINIMIZE TRACE INDUCTANCE
5) CONNECT THE DRAIN LEADS OF THE POWER MOSFETS TO A LARGE COPPER AREA TO HELP
6) PLACE THE FEEDBACK AND COMPENSATION COMPONENTS AS CLOSE TO THE IC PINS ASPOSSIBLE. CONNECT THE FEEDBACK-DIVIDER RESISTOR FROM FB TO THE OUTPUT AS CLOSE
DECOUPLING CAPACITOR DIRECTLY ACROSS AND AS CLOSE AS POSSIBLE TO THE HIGH-SIDE
AS POSSIBLE TO THE FARTHEST OUTPUT CAPACITOR.
VRG 1P8V_BUCK
GUIDELOCATION 2
BE BETWEEN 350KHZ-650KHZ.
SIGNALGROUND
INPUT 10.8V-13.2V
GROUNDPOWER
BETWEEN PGND AND GNDONLY CONNECTION
LOCATION 1
SEE LAYOUT
OF THE GATE-DRIVE LOOP.
COOL THE DEVICE.
FSYNCIN_1P8 INPUT OPTIONAL
SET TO 500 KHZ DEFAULT.IF FSYNCIN_1P8 IS DRIVEN,IT MUST
MAX8544 SWITCHING FREQUENCY
REVISION 0.51 COMPENSATION VALUES CHANGED TO 0.47UF AND 510 OHM.REVISION 0.52 CHANGED REFDES TO SOFT.
REVISION 0.5 INITIAL RELEASE.REVISION HISTORY
LAYOUT GUIDE
THE POWER GROUND PLANE AND THE SIGNAL GROUND PLANE. PLACE THE INPUT CERAMIC
CONNECT ALL OTHER CAPACITORS TO THE SIGNAL GROUND PLANE.2) CONNECT INPUT, OUTPUT, AND VL CAPACITORS TO THE POWER GROUND PLANE;
THE HIGH SWITCHING CURRENT WITHIN THIS SMALL LOOP.MOSFET’S DRAIN AND THE LOW-SIDE MOSFET’S SOURCE. THIS IS TO HELP CONTAIN
N_FET 0.47
UF
5%
10.2
K
1%
1%
5%51
0
100U
F
N_FET
100U
F
100U
F
1%
POK_1P8
10U
F
VRG_1P8V_CS_N
100U
F
100P
F
100K
1%FSYNCIN_1P8
0.1U
F
200K
110K
VRG_1P8V_DL
10U
F
VRG_1P8V_CS_P
0.82UH
510
0.47UF
1%
MAX8544EEP
+5VL
1P8ILIM21%
VRG_1P8V_DH
VRG_1P8V_BST
8.06K
SYNCOUT_1P8
10U
F
EN_1P8_BUCK
1P8CMP4
1%
1UF
1P8SS
5%
10U
F
+1P8V_BUCKVRG_1P8V_LX
+VIN
1P8FB
1P8ILIM1
560PF
53.6K
0.1UF
1P8CMP
1%
100K
10.2K
8.2K
FSYNC
-700 5.00Sun Aug 07 10:56:19 2005
14
18
17
16
510
11
122
1
4
3
19
6
15
20
8
13
9
7
U8B1 C8B
7
C8B
6
C8B
8
1 2R8B8
R8B7
1 2R8B2
R8B
11
1 2
R8B3R8B9
R8B
6
2C6
2C5
1
2
C8B
4
1
2
C9B
3
1
2
C9B
1
C8B
12
C8B
13
C8B
10
R8B4
R8B1
21
R8A
5
21
R8B
5
1
2
C8B
3
C8B
11
5 6 7 8
4
3 2 1
Q8B2
5 6 7 8
4
3 2 1
Q8B1
C8B9
2C6 1
2
3
D8A1
1 2L8B1
1 2C8B5
C8B2
31
2
D8B
1
C8B1
68
2
A
B
C
D
2 1345
D
C
B
A
8 6 5 3
MODIFIEDSHEET
4 1
DRAWING REVBOARD REV
7
7
OUT
IN
S1S2S3
G
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S1S2S3
G
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OUT
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IN
OUT
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DL
CS_P
SYNCO
IN
EN
FSYNC
SS
COMP
ILIM2
GNDPGND
POK
MODE FB
LX
DH
BST
VL
Host Bus Adapter Schematics for Intel® 8134x I/O Processors 41
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Host Bus Adapter Schematics for Intel® 8134x I/O Processors 42