Homework
description
Transcript of Homework
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Homework
• Reading– None (Finish all previous reading assignments)
• Machine Projects– Continue with MP5
• Labs– Finish lab reports by deadline posted in lab
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Hierarchy for 80286 Memory and I/O
• IBM PC-AT (“Advanced Technology” in 1984)
• DOS 3.0 Operating System
• PC-AT bus evolved into Industry Standard Bus
• Many manufacturers built ISA-based PCs/cards
• ISA Bus– Slow 6 MHz evolved to 8 MHz or 125 nsecs/cycle– Address Bus 20 bits– Data Bus 16 bits
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IBM PC-AT
Reference: http://www.vintage-computer.com/ibmpcat.shtml
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Big Picture (80286)
RTC Keyboard SerialPort
ParallelPort
FloppyDisk
80286
RAMMemory
ROMMemory
ISA Bus: 20/16 bits, 8 MHz (125 nsecs/cycle)
HardDisk
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Hierarchy for 80486 Memory and I/O
• CPU Clock: 66 MHz
• Local Bus or CPU Bus– “Fast” 33MHz / 32 bits wide
• Expansion Bus Controller (CPU-ISA Bridge)
• ISA Bus (Legacy)– “Slow” 8 MHz or 125 nsecs/cycle– Address Bus 20 bits– Data Bus 16 bits
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Big Picture (80486)
CPU
Local bus or CPU bus: fast (33 MHz, 32 bits) [30 nsec./cycle]
Memory CacheVideo
AdapterDisk
ExpansionBus
Controller
RTC
ISA bus: slow (8 MHz, 8/16 bits) [125 nsec./cycle]
KeyboardSerialPort
ParallelPort
FloppyDisk
SystemROM
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Competition for ISA replacement
• Many vendors proposed busses to replace ISA as the technology improved– IBM: Micro Channel Architecture (MCA)– Extended Industry Standard Architecture (EISA)– VESA Local Bus– Intel: Peripheral Component Interconnect (PCI)
• PCI had won commercial battle by mid-90’s– “Medium Speed”: 33 or 66 MHz / 32 or 64 bits wide
• For a while PCs had a mix of ISA and PCI slots
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Subsequent Evolution
• More and more of the “random logic” and VLSI chips surrounding the processor were included in Ultra-VLSI chips (“Motherboard chips”)
• The “North Bridge” allows highest speed access to program/data memory and high speed graphics processors (faster access than the PCI bus!)
• The “South Bridge” interfaces to PCI bus and incorporates devices for Ethernet, USB, etc.
• The Super I/O chip incorporates legacy interfaces– Floppy Disk, Keyboard, Parallel Port, Serial Ports, etc.
Hierarchy for Pentium Memory and I/O
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Mother Board chip or chip set
Hierarchy for Pentium Memory and I/O
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Motherboard Chipsets
• The motherboard chip set provides the core logic and manages the motherboard's functions– CPU: CPU– NB: Northbridge– GPU: Graphics– SB: Southbridge
Source: Wikipedia
Multi-core CPU Chips
• To increase processing power, multiple CPU’s are included in high performance CPU chips
• Example Dual core:
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Enhancing Performance• “Pipelining is an implementation technique in which
multiple instructions are overlapped in execution”, (Patterson and Hennessey, “Computer Organization and Design”, p. 436)
Sequential Execution:
Pipelined Execution:
RegRead
ALUOperation
InstructionFetch
DataMemory
RegWriteLoad Word
8 nsRegRead
ALUOperation
InstructionFetch
DataMemory
RegWrite
8 nsRegRead
InstructionFetch
Load Word
Load Word
RegRead
ALUOperation
InstructionFetch
DataAccess
RegWriteLoad Word
2 nsRegRead
ALUOperation
InstructionFetch
DataMemory
RegWrite
RegRead
InstructionFetch
Load Word
Load Word ALUOperation
DataMemory
RegWrite
2 ns
2 ns
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Enhancing Performance• Pipelining improves the overall performance by
increasing instruction throughput per unit time not decreasing execution time of an individual instruction
• Ideal speedup is number of stages in the pipeline
• Do we achieve this? Sometimes / Not always– Notice the idle time in the pipe at certain times– Flushing pipeline during conditional jumps– Data being calculated by previous instruction may be
needed too early during the next instruction cycle
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Superscalar Processors
IF OF EX OS
IF OF EX OS
IF OF EX OS
IF OF EX OS
IF OF EX OS
IF OF EX OS
IF OF EX OS
IF OF EX OS
IF OF EX OS
IF OF EX OS
0 1 2 3 4 5 6 7 8 9 Time in Base Cycles
• More than one execution pipeline executing in parallel
• Note: Possible coordination problems must be resolved
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Custom Digital Signal Processor
• Early example of a super scalar processor with pipelining of arithmetic operations
• Embedded application is hard real time system – processing analog modem waveforms
• Computations are based on complex arithmetic• Rotation of a vector (e.g. carrier frequency)
– Complex multiply
• Filtering of a sequence of signal samples– Loop doing complex multiplication and addition
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Digital Signal Processor ArchitectureSignal Processing Controller (SPC)
Fetch and Execute Instructions
Multiplier-Accumulator-Ram(Real)
Multiplier-Accumulator-Ram(Imaginary)
Data Bus
Real MAR Chip Select Imaginary MAR Chip Select
Address/Modulo Registers
ALU ALUMemoryMemory
SPCProgramMemoryR0
R1N0N1
ControllingHost
Processor(68000)
Analog/DigitalConverter
FromPhone Line
Digital/AnalogConverter
ToPhone Line
Address Bus
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Addresses and Complex Data
• Addresses stored in SPC Registers– Pointers to complex data in MAR memories– Register post increment modes:
Increment by oneDecrement by oneIncrement by one modulo specified N registerDecrement by one modulo specified N register
• Complex numbers stored in MAR memories:– Real part in one MAR (Real MAR)– Imaginary part in other MAR (Imaginary MAR)
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Multiplier-Accumulator-RAM
X-Register Y-RegisterMultiplier
Adder
256 Words of RAM Memory
Accumulator
MPY MAC
To Other MARFrom Other MAR
Address from SPC
Selector
Chip SelectFrom SPC
Selector
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SPC/MAR Assembly Programming
• Complex Multiply(RR0 * RR1 – IR0 * IR1) + i (RR0 * IR1 + RR1 * IR0)
YPP.P MP.R1 Load both Y from own memory at R1 address
MPY.P MR.R0 Multiply both with real memory at R0 address
YMM.R MI.R1 Load minus real Y from imag memory at R1 address
YPP.I MR.R1 Load imag Y from real memory at R1 address
MAC.P MI.R0 Multiply/add both with imag memory at R0 address
NOP Result not ready yet: NOP or housekeeping
NOP Result not ready yet: NOP or housekeeping
STA.P MP.R0 Store each acc. in own memory at R0 address
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Moore’s Law
• Gordon Moore made a famous observation in 1965, just four years after the first planar integrated circuit was discovered
• Moore observed an exponential growth in the number of transistors per chip and predicted that this trend would continue
• Moore's Law, the doubling of transistors every couple of years, has been maintained, and still holds true today
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Moore’s Law
Moore’s Law
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