HOMELLC TESTANALYZE REPORT SLIDE SETUP SOLUTIONS LINK LAYER CMD/CNTRLRUN HOME Quantum Data...

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SETUPSOLUTIONS LINK LAYER CMD/CNTRLRUN

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Quantum Data DisplayPort Link Layer Test Solutionsusing the 882EA Test Instrument

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HOME

QUANTUM DATA OVERVIEW

Mission StatementQuantum Data invents test instruments that help manufacturers bring next-generation audio, video, and control products to market – faster and without interoperability problems.

HistoryHeadquartered in Elgin, IL, Quantum Data has been at the leading edge of programmable video test generator technology for nearly 30 years. Quantum Data was founded in 1979 by Allen and Ann Jorgensen and has been at the leading edge of programmable video test generator technology since its inception. Over the years, the company has expanded the scope of its products to include other types of video test equipment.

Global PresenceQuantum Data has distributorships and service centers throughout the world including: European Union, China, Taiwan, Japan, Korea, Singapore, Malaysia, Latin America, etc.

You’ll find Quantum Data instruments in the Authorized Test Centers and design laboratories and production facilities of major consumer electronics and information technology manufacturer’s throughout the world.

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SOLUTIONS

QUANTUM DATA DISPLAYPORT LINK LAYER TEST SOLUTIONS

SOLUTIONS


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SOLUTIONS

882EA TEST INSTRUMENT

Aux channel port (connects to source)

DisplayPort transmit port.

DisplayPort receive port

Aux channel port (connects to sink)

Activation keys

882EA front panel

882EA - Front

882EA - Rear

SOLUTIONS

Activation keys


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SOLUTIONS

882EA TEST SOFTWARE

• 882EA Link layer compliance test (VESA APPROVED!)– Applications

• Tests link layer compliance on source devices under test.• Tests link layer compliance on sink devices under test.

– Operation• Can be run link layer compliance test through front panel• Can be run link layer compliance test through GUI application.• Can be run link layer compliance test through command line.

• 882EA Auxiliary Channel Analyzer– Applications – monitors aux channel transactions including link

transactions.• Monitor link training during link layer compliance testing.• Monitors link training or link maintenance transactions during normal

operation.

– Configurations• Monitors link transactions between 882EA and source devices under test.• Monitors link transactions between 882EA and sink devices under test.

SOLUTIONS


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LINK LAYER

LINK LAYER OPERATION

LINK LAYER


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LINK LAYER

TESTING APPROACH

• What approach can developers of DisplayPort products take to ensure robust link layer solutions?

– Ensure products are compliant.

– Ensure product are interoperable.

• Compliance first – then interoperability.– Compliant products may not interoperate together.

– Noncompliant products may still interoperate.

• What tools are available for developers of DisplayPort products?– Link layer compliance test tools.

– Link layer monitoring tools.

LINK LAYER


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INFORMATION

DISPLAYPORT LINK LAYER FUNCTIONS

• Link Initialization (“link training”)– Link training must be performed unless the Source Main Link transmitter

and the Sink Main Link receiver are already in synchronization. – Link training follows hot plug – Transmitter (source) device detects a

HPD low-going pulse that exceeds 2ms in width.

• Link Maintenance– Source must check Link Status when it detects possible main link

synchronization loss (IRQ HPD from sink with low pulse between 0.5ms – 1ms).

– Must link train upon synchronization loss.

LINK LAYER


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OVERVIEW

DISPLAYPORT LINK TRAINING

PROCESS

• Link training follows hot plug - source device detects a HPD low-going pulse that exceeds 2ms in width.

• Two phases in link training:– Clock Recovery - locks the receiver CR (clock recovery) PLL to the

repetition of D10.2 data symbols.– Channel Equalization – achieves symbol lock and inter-lane alignment:

• Symbol Lock - Receiver (Sink) has properly detected and aligned the ANSI8B/10B symbol boundaries.

• Inter-lane alignment – Sink has successfully aligned the symbol boundaries of all lanes with one another.

– Must complete in 10ms.

LINK LAYER


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LINK LAYER

LINK TRAINING

NORMAL OPERATION WITH SINK

READ SINK DPCD CAPABILITIES

LINK LAYER

Source reads sink DCPD link capability register 001h.

Physical connection for testing a DisplayPort sink device.

Sink supports link rate of 2.7Gb/s and 4 lanes.


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LINK LAYER

LINK TRAINING


WRITE LINK PARAMETERS TO

SINK DPCD

LINK LAYER

Source writes to sink DCPD link configuration register 100h to set link training parameters

Source writes link rate of 2.7Gb/s and 4 lanes


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LINK LAYER

LINK TRAINING


BEGIN CLOCK RECOVERY

Source writes to sink DCPD link configuration register 102h to set Training Pattern

Set main link to send Training Pattern 1 for Clock Recovery

LINK LAYER


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LINK LAYER

LINK TRAINING


SET DPCD LINK CONFIGURATION

Settings used for link training

Source writes to sink DCPD link configuration register 102h to set Training parameters

LINK LAYER


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LINK LAYER

LINK TRAINING


CHECK CLOCK RECOVERY DONE

Source reads sink DCPD link status register 202h to check on link status

Clock recovery is Done (Set)

LINK LAYER


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LINK LAYER

LINK TRAINING


BEGIN CHANNEL EQUALIZATION Source writes to sink

DCPD link configuration register 102h to begin Channel Equalization

Training pattern set to 2

LINK LAYER


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LINK LAYER

LINK TRAINING


CHECK CHANNEL EQUALIZATION

DONE Source reads sink DCPD link status register 202h to check on Channel Equalization

Channel Equalization and Symbol Lock Done (Set)

LINK LAYER


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LINK LAYER

LINK TRAINING


CHECK LINK TRAINING DONE

Training not in progress – Link training done

Source reads sink DCPD link status register 202h to check on Link Training completion

LINK LAYER


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LINK LAYERANALYSIS

LINK LAYER ANALYSIS

ANALYZE


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PHYSICAL SETUP

PASSIVE MONITORING FOR

ANALYSIS BETWEEN

SOURCE AND SINK DEVICES

DisplayPort Source device

DisplayPort Sink device

Connect the sink device to the ACA port labeled To Sink.

Connect the source device to the ACA port labeled To Source.

ANALYZE

Physical connections for passive monitoring.


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LINK LAYERANALYSIS

TEST CASE #1

SOURCE BEGINS LINK TRAINING WITH VOLTAGE

SWING OF 1

Source begins Link Training with voltage swing level of 1 rather than 0.

ANALYZE

Sample test case for passive monitoring.


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LINK LAYERANALYSIS

TEST CASE #2

LINK TRAINING SHIFTS TO

LOWER LANE RATE

ANALYZE

Source writes to sink DCPD link configuration register 102h to set Link Training pattern.

Link training pattern set to 1.

Second sample test case for passive monitoring.


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LINK LAYERANALYSIS

TEST CASE #2


LOWER LANE RATE

ANALYZE

Source reads sink DCPD link status register 202h to check Link Training progress.

Clock Recovery and Channel Equalization not set (not completed).


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LINK LAYERANALYSIS

TEST CASE #2


LOWER LANE RATE

ANALYZE

Sink requests pre-emphasis for link training.

Source reads sink DCPD link status register 202h to check for change request in Link Training parameters.


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LINK LAYERANALYSIS

TEST CASE #2


LOWER LANE RATE

ANALYZE

New link training parameters – Max drive current setting is reached.

Source writes to sink DCPD link configuration register 102h to set new Link Training parameters.


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LINK LAYERANALYSIS

TEST CASE #2


LOWER LANE RATE

ANALYZE

Lane rate reduced to 1.62Gb/s.

Source writes to sink DCPD link configuration register 100h to set new Link Training lane rate.


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LINK LAYERANALYSIS

TEST CASE #3

LINK TRAINING REQUIRES

LONGER THAN 10MS

Link Training begins

Link Training completes >10ms

ANALYZE

Third sample test case for passive monitoring.


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LINK LAYERCOMPLIANCE

TEST

RUNNING THE LINK LAYER COMPLIANCE TEST

LLC TEST


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LINK LAYER COMPLIANCE

TEST

PHYSICAL SETUP

OVERVIEW

SETUP

First: Make the physical connections.

Second: Configure the capabilities of the device under test through the LLC GUI, front panel or command line.

Third: Select the tests you want to run and then initiate them either through the GUI, front panel or command line.

Fourth: You can monitor the link transactions during the test.

Fifth: When the test is done, you get a summary and detailed report.


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DisplayPort Source

Loop the ACA port labeled To Sink to the 882EA Rx port.

Connect the source device to the ACA port labeled To Source.


TEST

PHYSICAL SETUP

SOURCE TESTING

SETUP

Physical test configuration for running a link layer compliance

test on a source device with monitoring by the ACA.


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DisplayPort Sink


TEST

PHYSICAL SETUP

SINK TESTING

SETUP

Connect the ACA port labeled To Source to the 882EA Tx port.

Connect the sink device to the ACA port labeled To Sink.

Physical test configuration for running a link layer compliance

test on a sink device with monitoring by the ACA.


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RUN LINK LAYER COMPLIANCE

TEST

RUN THE LINK LAYER COMPLIANCE TEST

RUN


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RUN LINK LAYERCOMPLIANCE

TEST

SINK CONFIGURATION Configures the test with

the number of lanes that the sink device under test supports.

Configures the test with the color and sampling rate supported by the sink device under test.

This tab enables you to configure the capabilities of the device under test.

Configures the test with the masimum lane rate that the sink device under test supports.

Configures the test with the formats that the sink device under test supports.

Configures whether the sink device under test supports test automation.

Provisions the test with the DPCD capabilities registers.

RUN

You can load and existing configuration from a file on the 882EA or you can load an existing configuration.


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TEST

SINK TEST

RUN

Here is a list of the tests. You can select which ever tests you want to run.

This tab allows you to select the tests you want to run and to initiate the test.

You initiate the test here. You can run the

selected tests multiple times.

Defines the amount of time between each test.

These spin boxes determine how many times each test is run.

The status of each test that is run.


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TEST

SOURCE CONFIGURATION

RUN

Configures the test with the number of lanes that the source device under test supports.Configures the test with

the color and sampling rate supported by the source device under test.

This tab enables you to configure the capabilities of the source device under test.

Configures the test with the masimum lane rate that the source device under test supports.

Configures the test with the formats that the source device under test supports.

Configures whether the source device under test supports test automation.

You can load and existing configuration from a file on the 882EA or you can load an existing configuration.


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TEST

SOURCE TEST

RUN

Here is a list of the tests. You can select which ever tests you want to run.

This tab allows you to select the tests you want to run and to initiate the test.

Defines the long hot plug pulse width supported by the source device under test.

These spin boxes determine how many times each test is run.

The status of each test that is run.

Defines the time delay between each test.


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LINK LAYERCOMPLIANCE

TEST

LINK LAYER COMPLIANCE REPORT

REPORT


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LINK LAYERCOMPLIANCE TEST REPORT

SOURCE TEST HEADER

REPORT

The Generator Information section provides information about the 882EA firmware/gateware and hardware.

The DUT Specific Information section provides information about the capabilities of the device under test.


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SOURCE TEST DEVICE

CONFIGURATION

REPORT

Continuation of the DUT Specific Information section provides information about the capabilities of the device under test.


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SOURCE TEST

REPORT

Test Summary section provides a Pass/Fail indication of the test.

Test Details section provides a details about each distinct event in the test.

The details section tells you if each distinct event in the test passed or failsd. This enabls you to pin piont the point of failure of the test.


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SOURCE TEST

REPORT

Typical example of the details section of a link layer compliance test.


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SOURCE TEST

REPORT

Another typical example of the details section of a link layer compliance test.


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SOURCE TEST

REPORT

Final status in the details section of a link layer compliance test.


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SINK TEST

REPORT

Test Summary section provides a Pass/Fail indication of the test.

Test Details section provides a details about each distinct event in the test.

The details section tells you if each distinct event in the test passed or failsd. This enabls you to pin piont the point of failure of the test.


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SOURCE TEST DEVICE

CONFIGURATION

REPORT

Typical example of the details section of a link layer compliance test.


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LINK LAYERCOMMANDS

CONTROL OF THE LINK LAYER THROUGH COMMANDS AND FRONT PANEL

CMD/CNTRL


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LINK LAYERCOMMANDS

CMD/CNTRL

• You can directly control the DisplayPort link layer either through the 882EA front panel or the command line.

• Front panel (or virtual front panel) control functions– Change number of lanes.

– Change lane rate.

– Change any format parameter, e.g. colorimetry, sampling, etc.

• Command line control.– Read and DPCD register from a DisplayPort sink.

– Write to any writable DPCD register from a DisplayPort sink.

– Change any format parameter, e.g. colorimetry, sampling, etc.


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LINK LAYERCONTROLS

FRONT PANEL

Sets the number of lanes.

Initiates link training.

Sets the lane rate.

Forces link training with the specified values.

Enable or disable scrambling.

CMD/CNTRL

Front Panel operates the same as the virtual front

panel shown below.


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LINK LAYERCONTROL

COMMANDS

SINK TESTING

CMD/CNTRL

These commands control the DPCD of the sink device connected to the 882EA.


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LINK LAYERCONTROL

COMMANDS

SINK TESTING

CMD/CNTRL


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LINK LAYERCONTROL

COMMANDS

SOURCE TESTING

CMD/CNTRL

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