Home Assignment 3 Logical Design Assigned. Deadline 2015 May 3 rd Sunday.
-
Upload
brandon-chapman -
Category
Documents
-
view
218 -
download
0
description
Transcript of Home Assignment 3 Logical Design Assigned. Deadline 2015 May 3 rd Sunday.
Home Assignment 3 Logical DesignAssigned.
Deadline 2015 May 3rd Sunday
Flip-Flops. Counters. Registers.
The D Latch The D Flip-Flop Flip-Flop Symbols A Basic Digital Counter (ripple counter) A Synchronous Binary Counter A Synchronous Decimal Counter Serial to Parallel Shift register Parallel to Serial Shift register
P&H Appendix-BWakerly Ch.7
The D Latch
Timing diagram of D latch.
CLK D Q Qn
0 D Q Q 1 D Q D
D Q
_ Q
QA
D CLK
Cannot experience a "race" condition caused by all inputs being at logic 1 simultaneously.
The D Flip-Flop
Slave RS latch Master D latch
q
CLK’
qA
D CLK
QA
CLK’
Flip-Flop Symbols
A Basic Digital Counter (ripple counter)
Timing Diagram of Ripple counter without delays.
BA
A
CLK
CA DA
A Basic Digital Counter (ripple counter)
Timing Diagram of Ripple counter with delays.
BA
A
CLK
CA DA
Ripple effect (delay)
A Synchronous Binary Counter
CLK
StatesCountD C B A
0 0 0 0 00 0 0 1 10 0 1 0 20 0 1 1 30 1 0 0 40 1 0 1 50 1 1 0 60 1 1 1 71 0 0 0 81 0 0 1 91 0 1 0 101 0 1 1 111 1 0 0 121 1 0 1 131 1 1 0 141 1 1 1 15
A Synchronous Decimal Counter States
CountD C B A
0 0 0 0 00 0 0 1 10 0 1 0 20 0 1 1 30 1 0 0 40 1 0 1 50 1 1 0 60 1 1 1 71 0 0 0 81 0 0 1 9
CLK
Serial to Parallel Shift register
Parallel to Serial Shift register