High Yield Device Delayering Techniques using Helios PFIBefug.imec.be/EFUG2015_02.pdf · provides...
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High Yield Device Delayering Techniques using Helios PFIB EFUG 2015 Toulouse
Transcript of High Yield Device Delayering Techniques using Helios PFIBefug.imec.be/EFUG2015_02.pdf · provides...
High Yield Device Delayering Techniques using Helios PFIB
EFUG 2015
Toulouse
Plasma FIB Applications & Use Cases: Electronics
FEI Confidential - Covered by CNDA 2
3D Device
<120mins
300 µm Solder Bump
55mins
100um Chunk
<60min
EFI Prep
EFI / nanoProbing
TSV
EBSD Prep
Helios PFIB : High Resolution Imaging & Failure Identification
FEI Confidential - Covered by NDA
Helios PFIB : High Resolution Imaging & Failure Identification
FEI Confidential - Covered by NDA
Fault Isolation
Introduction: Generic EFI/EFA-to-PFA Workflow
PFA Sample Prep Root Cause Analysis
• Generic FA workflow proceeds from 1) alignment to CAD, 2) iterate delayering and EFI, and finally 3) RCA by PFA • BEOL defects are isolated by nano-probing at metal layers while FEOL defects (and deviations) are nano-probed at contacts • A new workflow (e.g., PFIB+DX) must be compatible with BEOL and FEOL and produce the same results as conventional workflows • The scope of this project is to establish PFIB+DX as an alternative to conventional de-layering by comparing transistor parameters
obtained by nano-probing at the contact/local-interconnect level. • The compatibility of BEOL with this EFI workflow is implied by the validity of the IV-curves obtained by nano-probing at metal-0
De-Layering
Requirements for Delayering
In order to prepare a device for EFI/EFA a number of requirements from the delayering process must be met:
• Large Area (100 µm) Region of Interest (ROI) available
• Controlled layer removal with clear (live) endpointing
• Excellent flatness over ROI following delayering
• Damage free surface
6 FEI Confidential - Covered by CNDA
EFI – Current Delayering Methods(Mechanical)
7
SEM Image of Mechanically dimpled/polished sample
Not site specific Large keep-out zones
FEI Confidential - Covered by NDA
Optical Image of a dimpled
die
EFI - Current Delayering Methods(FIB)
8
Uncontrollable delayering of a 28 nm technology process when using traditional Ga+, XeF2/H2O methodology. Up to 4 different copper layers exposed
FEI Confidential - Covered by NDA
Unevenly exposed M1 lines on a 22nm technology process device with Xe FIB and no chemistries
Helios PFIB for Delayering
9 FEI Confidential - Covered by CNDA
1. Inductively Coupled Plasma (ICP) source technology with Xe ion beam provides >20X throughput compared to current Ga+ FIB techniques
2. Xe ion beam has ~35 less surface damage (amorphization) than Ga+ 3. Dx chemistry (US patent 9,064,811) + PFIB allows controlled delayering
from top-down to expose super-flat surfaces over large areas
Delayering on Advanced Process Technologies using FIB D M Donnet et al ISTFA 2014
14nm FinFET IC Sample
SEM Image from: http://www.intel.com/content/dam/www/public/us/en /documents/pdf/foundry/mark-bohr-2014-idf-presentation.pdf
M11
M9
M0
Conventional: Mechanical or Broad Ion Beam
PFIB + DX
Helios PFIB Delayering: Layer-by-Layer Control for EFI
M6 V5 M5 V4 M4 V3 M3 V2 M2
M4 M3 M2
~50nm “pitch” between layers in this range of metal levels
End-pointing per layer or multiple layers
FEI Confidential - FEI Seminar Series
M4 M3 M2 M1 M0
Helios PFIB Delayering: End-pointing on M0 for FEOL nano-probing
350V SEM inspection of the exposed contacts reveals the expected layout…
Helios PFIB Delayering: Uniformity of Layer Removal
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SEM cross sectional images of a device following delayering PFIB + Dx gas chemistry
FEI Confidential - Covered by NDA
Helios PFIB EFI: EBAC / EBIC
15 FEI Confidential - Covered by CNDA
SEM EBAC Mix
High Gain EBAC/EBIC Amplifier
• Line lights up when touched by probe
FEI Confidential - FEI Seminar Series
Helios PFIB EFI: Voltage contrast
FEI Confidential - Covered by CNDA
With Landing confirmation Fast Transistor Characterization setup
Helios PFIB EFI: Transistor Measurements
Summary
Delayering with the Helios PFIB delivers
• Site specific, damage free large area delayering with clear endpointing for
controlled removal of individual layers
• Single operator, high throughput EFI solution
• Enables insitu nanoprobing
2014-0910 FEI Confidential
