High temperature operation of SiC transistors
77
High temperature operation of SiC transistors ATW on Thermal Management, Los Gatos Cyril BUTTAY 1 , Marwan ALI 2 , Oriol AVINO 1,2 , Hervé MOREL 1 , Bruno ALLARD 1 1 Laboratoire Ampère, Lyon, France 2 Labinal Power Systems, SAFRAN Group, France 23/9/15 1 / 32
Transcript of High temperature operation of SiC transistors
High temperature operation of SiC transistorsATW on Thermal Management, Los Gatos
Cyril BUTTAY1, Marwan ALI2, Oriol AVINO1,2,Hervé MOREL1, Bruno ALLARD1
1 Laboratoire Ampère, Lyon, France2 Labinal Power Systems, SAFRAN Group, France
23/9/15
1 / 32
Outline
Introduction
High-Temperature behaviour of SiC Devices
Packaging for high-temperature converters
Conclusion
2 / 32
Outline
Introduction
High-Temperature behaviour of SiC Devices
Packaging for high-temperature converters
Conclusion
3 / 32
Automotive
Vehicle Location Max Temp (°C)Drive train high temp location 177Floor 85Near radiator support structure 100Back of alternator 160Cooling circuit 120Exhaust manifold 649
Most data: Kassakian, J. G. et al. “The Future of Electronics in Automobiles”, ISPSD, 2001, p 15-19
I Low-cost, high-volume applications;I Moving to higher voltages (12V->300V for hybrids)I Little cooling headroom with silicon devices (TJ=150 to
175°C)
ß dedicated cooling circuit for power electronic systems
4 / 32
Automotive
Vehicle Location Max Temp (°C)Drive train high temp location 177Floor 85Near radiator support structure 100Back of alternator 160Cooling circuit 120Exhaust manifold 649
Most data: Kassakian, J. G. et al. “The Future of Electronics in Automobiles”, ISPSD, 2001, p 15-19
I Low-cost, high-volume applications;I Moving to higher voltages (12V->300V for hybrids)I Little cooling headroom with silicon devices (TJ=150 to
175°C)
ß dedicated cooling circuit for power electronic systems
4 / 32
Automotive
Vehicle Location Max Temp (°C)Drive train high temp location 177Floor 85Near radiator support structure 100Back of alternator 160Cooling circuit 120Exhaust manifold 649
Most data: Kassakian, J. G. et al. “The Future of Electronics in Automobiles”, ISPSD, 2001, p 15-19
I Low-cost, high-volume applications;I Moving to higher voltages (12V->300V for hybrids)I Little cooling headroom with silicon devices (TJ=150 to
175°C)
ß dedicated cooling circuit for power electronic systems
4 / 32
Aircraft
The trend:I Hydraulic, Pneumatic and Electric
networks co-exist in current systemsI More-electric aircraft should reduce
complexityI objective: 1 MW on-board electrical power
The environment:
I From mild to very harsh:I Some system are located in the cabinI Jet engine actuator will face -55°C to 225°C cyclingI Many systems are located in non-pressurised areas
I Long system life: around 30 yearsI Reliability is the main concern
5 / 32
Aircraft
The trend:I Hydraulic, Pneumatic and Electric
networks co-exist in current systemsI More-electric aircraft should reduce
complexityI objective: 1 MW on-board electrical power
The environment:I From mild to very harsh:
I Some system are located in the cabinI Jet engine actuator will face -55°C to 225°C cyclingI Many systems are located in non-pressurised areas
I Long system life: around 30 yearsI Reliability is the main concern
5 / 32
Aircraft
The trend:I Hydraulic, Pneumatic and Electric
networks co-exist in current systemsI More-electric aircraft should reduce
complexityI objective: 1 MW on-board electrical power
The environment:I From mild to very harsh:
I Some system are located in the cabinI Jet engine actuator will face -55°C to 225°C cyclingI Many systems are located in non-pressurised areas
I Long system life: around 30 yearsI Reliability is the main concern
5 / 32
Aircraft
The trend:I Hydraulic, Pneumatic and Electric
networks co-exist in current systemsI More-electric aircraft should reduce
complexityI objective: 1 MW on-board electrical power
The environment:I From mild to very harsh:
I Some system are located in the cabinI Jet engine actuator will face -55°C to 225°C cyclingI Many systems are located in non-pressurised areas
I Long system life: around 30 yearsI Reliability is the main concern
5 / 32
Aircraft
The trend:I Hydraulic, Pneumatic and Electric
networks co-exist in current systemsI More-electric aircraft should reduce
complexityI objective: 1 MW on-board electrical power
The environment:I From mild to very harsh:
I Some system are located in the cabinI Jet engine actuator will face -55°C to 225°C cyclingI Many systems are located in non-pressurised areas
I Long system life: around 30 yearsI Reliability is the main concern
5 / 32
Space Exploration
I NASA missions to Venus and JupiterI Venus surface temperature : up to 480°CI Pressure a few kilometres inside Jupiter: 100
bars, at 400°CI Strong thermal cycling, as temperature can drop
to 140K at night;I Other awful conditions: winds, corrosive
gases. . .
6 / 32
Deep oil/gas extraction
I Continuous operation, relatively lowcycling
I Deep drilling: high ambient temperature(up to 225°C)
I Expected lifetime: 5 yearsI Main requirement: sensors and
dataloggingI Example of new applications: downhole
gas compressor
7 / 32
Maximum operating temperature
0°C
500°C
1000°C
1500°C
2000°C
2500°C
3000°C
10 V 100 V 1 kV 10 kV 100 kV 1 MV
Junc
tion
tem
pera
ture
Breakdown voltage
Silicon3C−SiC6H−SiC4H−SiC
2H−GaNDiamond
Silicon operating temp is intrisically limited at high voltages.I 1200 V devices rated at <200 °C junction temperature
8 / 32
Outline
Introduction
High-Temperature behaviour of SiC Devices
Packaging for high-temperature converters
Conclusion
9 / 32
Test configuration
I High temperature test systemI Silver-sintered interconnectsI Ceramic substrate (DBC)I Copper-kapton leadframe
I DUT: 490 mΩ SiC JFET from SiCEDI characterization:
I Tektronix 371A curve tracerI Thermonics T2500-E conditionner
Source: Thermonics T-2500E Datasheet
10 / 32
Test configuration
I High temperature test systemI Silver-sintered interconnectsI Ceramic substrate (DBC)I Copper-kapton leadframe
I DUT: 490 mΩ SiC JFET from SiCEDI characterization:
I Tektronix 371A curve tracerI Thermonics T2500-E conditionner
Source: Thermonics T-2500E Datasheet
10 / 32
Test configuration
I High temperature test systemI Silver-sintered interconnectsI Ceramic substrate (DBC)I Copper-kapton leadframe
I DUT: 490 mΩ SiC JFET from SiCEDI characterization:
I Tektronix 371A curve tracerI Thermonics T2500-E conditionner
Source: Thermonics T-2500E Datasheet
10 / 32
Static Characterization of 490 mΩ JFET
Buttay et Al. “Thermal Stability of Silicon Carbide Power JFETs” IEEE transactions on Electron Devices, 2013, 60, 4191-4198
0 2 4 6 8 10 12Forward voltage [V]
0
2
4
6
8
10
12Fo
rwar
d cu
rren
t [A]
-50 C-10 C30 C70 C
110 C
150 C190 C230 C270 C300 C
VGS = 0 V , i.e. device fully-on11 / 32
Power dissipation as a function of the junction temp.
50 0 50 100 150 200 250 300
Junction temperature [C]
0
20
40
60
80
100
120
140D
issi
pate
d p
ow
er
[W]
2.0 A4.0 A6.0 A8.0 A10.0 A
12 / 32
Thermal Run-away mechanism – Principle
I The device characteristicI Its associated cooling systemI In region A, the device
dissipates more than thecooling system can extract
I In region B, the devicedissipates less than thecooling system can extract
I Two equilibrium points: onestable and one unstable
I Above the unstable point,run-away occurs
13 / 32
Thermal Run-away mechanism – Principle
I The device characteristicI Its associated cooling systemI In region A, the device
dissipates more than thecooling system can extract
I In region B, the devicedissipates less than thecooling system can extract
I Two equilibrium points: onestable and one unstable
I Above the unstable point,run-away occurs
13 / 32
Thermal Run-away mechanism – Principle
I The device characteristicI Its associated cooling systemI In region A, the device
dissipates more than thecooling system can extract
I In region B, the devicedissipates less than thecooling system can extract
I Two equilibrium points: onestable and one unstable
I Above the unstable point,run-away occurs
13 / 32
Thermal Run-away mechanism – Principle
I The device characteristicI Its associated cooling systemI In region A, the device
dissipates more than thecooling system can extract
I In region B, the devicedissipates less than thecooling system can extract
I Two equilibrium points: onestable and one unstable
I Above the unstable point,run-away occurs
13 / 32
Thermal Run-away mechanism – Principle
I The device characteristicI Its associated cooling systemI In region A, the device
dissipates more than thecooling system can extract
I In region B, the devicedissipates less than thecooling system can extract
I Two equilibrium points: onestable and one unstable
I Above the unstable point,run-away occurs
13 / 32
Thermal Run-away mechanism – examples
Always stable
Always unstable Becomming unstablewith ambient
temperature rise
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Thermal Run-away mechanism – examples
Always stable Always unstable
Becomming unstablewith ambient
temperature rise
14 / 32
Thermal Run-away mechanism – examples
Always stable Always unstable Becomming unstablewith ambient
temperature rise
14 / 32
Power dissipation as a function of the junction temp.
50 0 50 100 150 200 250 300
Junction temperature [C]
0
20
40
60
80
100
120
140D
issi
pate
d p
ow
er
[W]
2.0 A4.0 A6.0 A8.0 A10.0 A
15 / 32
Power dissipation as a function of the junction temp.
50 0 50 100 150 200 250 300
Junction temperature [C]
0
20
40
60
80
100
120
140D
issi
pate
d p
ow
er
[W]
1K/W
2K/W
4.5K/W
2.0 A4.0 A6.0 A8.0 A10.0 A
15 / 32
High Temperature Thermal Management
Buttay et al. “Thermal Stability of Silicon Carbide Power JFETs”, IEEE Trans on Electron Devices, 2014
100 150 200 250 300 350time [s]
30
40
50
60
70
80
pow
er [W
]
current changed from 3.65 to 3.7 A
Run-awaySiC JFET:
I 490 mΩ, 1200 VI RThJA = 4.5 K/WI 135 °C ambientI On-state losses
High temperature capability 6= reduced cooling needs!SiC JFETs must be attached to a low-RTh cooling system.
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Conclusions on high-temp. behaviour of SiC JFETs
I SiC JFETs can operate at > 200 °CI RDSon dependent on temperature
Ü sensitive to thermal run-awayI Require efficient thermal management
I low thermal resistance (1-2 K/W)I low or high ambient temperature
(> 200 °C possible)
Falahi et Al. “High temperature, Smart Power Module for aircraft actuators”,HiTEN 2013
0 2 4 6 8 10 12Drain-to-Source voltage [V]
0
10
20
30
40
50
60
70
Dra
incu
rren
t[A
]
-50C -10C 27C 70C 107C
160C
196C
234C
270C
49.0 48.8 48.6 48.4time [µs]
50
0
50
100
150
200
250
Vout [
V]
0.2 0.0 0.2time [µs]
310°C
17 / 32
Conclusions on high-temp. behaviour of SiC JFETs
I SiC JFETs can operate at > 200 °CI RDSon dependent on temperature
Ü sensitive to thermal run-awayI Require efficient thermal management
I low thermal resistance (1-2 K/W)I low or high ambient temperature
(> 200 °C possible)
Falahi et Al. “High temperature, Smart Power Module for aircraft actuators”,HiTEN 2013
0 2 4 6 8 10 12Drain-to-Source voltage [V]
0
10
20
30
40
50
60
70
Dra
incu
rren
t[A
]
-50C -10C 27C 70C 107C
160C
196C
234C
270C
49.0 48.8 48.6 48.4time [µs]
50
0
50
100
150
200
250
Vout [
V]
0.2 0.0 0.2time [µs]
310°C
17 / 32
Conclusions on high-temp. behaviour of SiC JFETs
I SiC JFETs can operate at > 200 °CI RDSon dependent on temperature
Ü sensitive to thermal run-awayI Require efficient thermal management
I low thermal resistance (1-2 K/W)I low or high ambient temperature
(> 200 °C possible)
Falahi et Al. “High temperature, Smart Power Module for aircraft actuators”,HiTEN 2013
0 2 4 6 8 10 12Drain-to-Source voltage [V]
0
10
20
30
40
50
60
70
Dra
incu
rren
t[A
]
-50C -10C 27C 70C 107C
160C
196C
234C
270C
49.0 48.8 48.6 48.4time [µs]
50
0
50
100
150
200
250
Vout [
V]
0.2 0.0 0.2time [µs]
310°C
17 / 32
Conclusions on high-temp. behaviour of SiC JFETs
I SiC JFETs can operate at > 200 °CI RDSon dependent on temperature
Ü sensitive to thermal run-awayI Require efficient thermal management
I low thermal resistance (1-2 K/W)I low or high ambient temperature
(> 200 °C possible)
Falahi et Al. “High temperature, Smart Power Module for aircraft actuators”,HiTEN 2013
0 2 4 6 8 10 12Drain-to-Source voltage [V]
0
10
20
30
40
50
60
70
Dra
incu
rren
t[A
]
-50C -10C 27C 70C 107C
160C
196C
234C
270C
49.0 48.8 48.6 48.4time [µs]
50
0
50
100
150
200
250
Vout [
V]
0.2 0.0 0.2time [µs]
310°C
17 / 32
Outline
Introduction
High-Temperature behaviour of SiC Devices
Packaging for high-temperature converters
Conclusion
18 / 32
Double Side Cooling
I Standard packaging offers cooling through one side of thedie only
I “3-D” or “Sandwich” package offers thermal managementon both sides
I Requires suitable topside metal on the dieI Requires special features for topside contact
19 / 32
Double Side Cooling
I Standard packaging offers cooling through one side of thedie only
I “3-D” or “Sandwich” package offers thermal managementon both sides
I Requires suitable topside metal on the dieI Requires special features for topside contact
19 / 32
The proposed 3-D Structure
Vbus
OUT
GND
JH
JL
I Two ceramic substrates, in “sandwich” configurationI Two SiC JFET dies (SiCED)I assembled using silver sinteringI 25.4 mm×12.7 mm (1 in×0.5 in)
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Ceramic Substrates
SiC JFET
Alumina
0.2 mm
0,3 mm
0.16 mm
0,15 mm
Copper
0.15 mm Gate SourceSource
Drain0.3 mm
Scale drawing for 2.4×2.4 mm2 die
I Si3N4 identified previously forhigh temperature
I For development: use ofalumina
I Etching accuracy exceedsstandard design rules
I Double-step copper etching fordie contact
Ü Custom etching technique
21 / 32
Bonding Material: Silver Sintering
Göbl, C. et al “Low temperature sinter technology Die attachment for automotivepower electronic applications” proc of APE, 2006
Silver PasteI Based on micro-scale silver
particles (Heraeus LTS-117O2P2)I Low temperature (240 °C) sinteringI Low pressure (2 MPa) process
No liquid phase involved:I No movement of the dieI No bridging across terminalsI No height compensation thanks to
wetting
22 / 32
Preparation of the Substrates
plain DBC board
I Final patterns within 50 µm of desired sizeI Two designs, for 2.4×2.4 mm2 and 4×4 mm2 diesI Total copper thickness 300 µm, ≈ 150 µm per step
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Preparation of the Substrates
plain DBC board 1a - Photosensitive resin coating
I Final patterns within 50 µm of desired sizeI Two designs, for 2.4×2.4 mm2 and 4×4 mm2 diesI Total copper thickness 300 µm, ≈ 150 µm per step
23 / 32
Preparation of the Substrates
plain DBC board 1a - Photosensitive resin coating
1b - Exposure andDevelopment
I Final patterns within 50 µm of desired sizeI Two designs, for 2.4×2.4 mm2 and 4×4 mm2 diesI Total copper thickness 300 µm, ≈ 150 µm per step
23 / 32
Preparation of the Substrates
plain DBC board 1a - Photosensitive resin coating
1b - Exposure andDevelopment
2 - Etching
I Final patterns within 50 µm of desired sizeI Two designs, for 2.4×2.4 mm2 and 4×4 mm2 diesI Total copper thickness 300 µm, ≈ 150 µm per step
23 / 32
Preparation of the Substrates
plain DBC board 1a - Photosensitive resin coating
1b - Exposure andDevelopment
2 - Etching 3a - resin coating
I Final patterns within 50 µm of desired sizeI Two designs, for 2.4×2.4 mm2 and 4×4 mm2 diesI Total copper thickness 300 µm, ≈ 150 µm per step
23 / 32
Preparation of the Substrates
plain DBC board 1a - Photosensitive resin coating
1b - Exposure andDevelopment
2 - Etching 3a - resin coating
3b - Exposure and Developpment
I Final patterns within 50 µm of desired sizeI Two designs, for 2.4×2.4 mm2 and 4×4 mm2 diesI Total copper thickness 300 µm, ≈ 150 µm per step
23 / 32
Preparation of the Substrates
plain DBC board 1a - Photosensitive resin coating
1b - Exposure andDevelopment
2 - Etching 3a - resin coating
3b - Exposure and Developpment
4a - Photosentive filmlaminating
I Final patterns within 50 µm of desired sizeI Two designs, for 2.4×2.4 mm2 and 4×4 mm2 diesI Total copper thickness 300 µm, ≈ 150 µm per step
23 / 32
Preparation of the Substrates
plain DBC board 1a - Photosensitive resin coating
1b - Exposure andDevelopment
2 - Etching 3a - resin coating
3b - Exposure and Developpment
4a - Photosentive filmlaminating
4b - Exposure andDevelopment
I Final patterns within 50 µm of desired sizeI Two designs, for 2.4×2.4 mm2 and 4×4 mm2 diesI Total copper thickness 300 µm, ≈ 150 µm per step
23 / 32
Preparation of the Substrates
plain DBC board 1a - Photosensitive resin coating
1b - Exposure andDevelopment
2 - Etching 3a - resin coating
3b - Exposure and Developpment
4a - Photosentive filmlaminating
4b - Exposure andDevelopment
5 - Etching
I Final patterns within 50 µm of desired sizeI Two designs, for 2.4×2.4 mm2 and 4×4 mm2 diesI Total copper thickness 300 µm, ≈ 150 µm per step
23 / 32
Preparation of the Substrates
plain DBC board 1a - Photosensitive resin coating
1b - Exposure andDevelopment
2 - Etching 3a - resin coating
3b - Exposure and Developpment
4a - Photosentive filmlaminating
4b - Exposure andDevelopment
5 - Etching6 - Singulating
I Final patterns within 50 µm of desired sizeI Two designs, for 2.4×2.4 mm2 and 4×4 mm2 diesI Total copper thickness 300 µm, ≈ 150 µm per step
23 / 32
Preparation of the Substrates
I Final patterns within 50 µm of desired sizeI Two designs, for 2.4×2.4 mm2 and 4×4 mm2 diesI Total copper thickness 300 µm, ≈ 150 µm per step
23 / 32
Preparation of the Dies
I Standard aluminium topside finishnot compatible with silver sintering
I Ti/Ag PVD on contact areasI Need for a masking solution
Ü jig with locating pockets.
DieMask
PVD
24 / 32
Preparation of the Dies
I Standard aluminium topside finishnot compatible with silver sintering
I Ti/Ag PVD on contact areasI Need for a masking solution
Ü jig with locating pockets.
DieMask
PVD
Before PVD 24 / 32
Preparation of the Dies
I Standard aluminium topside finishnot compatible with silver sintering
I Ti/Ag PVD on contact areasI Need for a masking solution
Ü jig with locating pockets.
DieMask
PVD
Before PVD After Ti/Ag PVD 24 / 32
Assembly
Screen printing
I Ceramic laser-cut jigs for precise alignment of dies andsubstrate
I Two sintering steps using the same temperature profile
25 / 32
Assembly
Screen printing 2- Mounting in alignment jig
I Ceramic laser-cut jigs for precise alignment of dies andsubstrate
I Two sintering steps using the same temperature profile
25 / 32
Assembly
Screen printing 2- Mounting in alignment jig
3- Die-alignment jig, dies and spacer placing
I Ceramic laser-cut jigs for precise alignment of dies andsubstrate
I Two sintering steps using the same temperature profile
25 / 32
Assembly
Screen printing 2- Mounting in alignment jig
3- Die-alignment jig, dies and spacer placing
4 - First sintering step
I Ceramic laser-cut jigs for precise alignment of dies andsubstrate
I Two sintering steps using the same temperature profile
25 / 32
Assembly
Screen printing 2- Mounting in alignment jig
3- Die-alignment jig, dies and spacer placing
4 - First sintering step 5 - Removal of die-alignment jig
I Ceramic laser-cut jigs for precise alignment of dies andsubstrate
I Two sintering steps using the same temperature profile
25 / 32
Assembly
Screen printing 2- Mounting in alignment jig
3- Die-alignment jig, dies and spacer placing
4 - First sintering step 5 - Removal of die-alignment jig
6 - Screen printing on "drain" substrate
I Ceramic laser-cut jigs for precise alignment of dies andsubstrate
I Two sintering steps using the same temperature profile
25 / 32
Assembly
Screen printing 2- Mounting in alignment jig
3- Die-alignment jig, dies and spacer placing
4 - First sintering step 5 - Removal of die-alignment jig
6 - Screen printing on "drain" substrate
7 - Mounting in alignment jig
I Ceramic laser-cut jigs for precise alignment of dies andsubstrate
I Two sintering steps using the same temperature profile
25 / 32
Assembly
Screen printing 2- Mounting in alignment jig
3- Die-alignment jig, dies and spacer placing
4 - First sintering step 5 - Removal of die-alignment jig
6 - Screen printing on "drain" substrate
7 - Mounting in alignment jig
8 - Second sintering step
I Ceramic laser-cut jigs for precise alignment of dies andsubstrate
I Two sintering steps using the same temperature profile
25 / 32
Assembly
Screen printing 2- Mounting in alignment jig
3- Die-alignment jig, dies and spacer placing
4 - First sintering step 5 - Removal of die-alignment jig
6 - Screen printing on "drain" substrate
7 - Mounting in alignment jig
8 - Second sintering stepResult
I Ceramic laser-cut jigs for precise alignment of dies andsubstrate
I Two sintering steps using the same temperature profile
25 / 32
Some results
Size: 25×25 mm226 / 32
Some results
26 / 32
Some results
0.9 1.0 1.1 1.2time [µs]
50
0
50
100
150
200
Vout [
V]
49.9 50.0 50.1 50.2time [µs]
200°C
I 300 Ω Resistive load, 0.5 A current (no cooling system used)I oscillations dues to external layout
26 / 32
Outline
Introduction
High-Temperature behaviour of SiC Devices
Packaging for high-temperature converters
Conclusion
27 / 32
Conclusion
I SiC JFET able to operate continuously at high temperature(> 200 °C)I Must be provided with efficient thermal management (RTh =1–2 K/W)I Proposition: introduce dual-side coolingI 3D structure using only high-temperature-rated materials
I Should be able to operate continuously at 300 °C, including passivation(parylene HT or F)
I Proposed etching technique offers satisfying resolutionI Silver sintering used for the interconnects, reliability to be investigated
I Package for demonstration of technology, no cooling attempted yet!
28 / 32
Conclusion
I SiC JFET able to operate continuously at high temperature(> 200 °C)I Must be provided with efficient thermal management (RTh =1–2 K/W)I Proposition: introduce dual-side coolingI 3D structure using only high-temperature-rated materials
I Should be able to operate continuously at 300 °C, including passivation(parylene HT or F)
I Proposed etching technique offers satisfying resolutionI Silver sintering used for the interconnects, reliability to be investigated
I Package for demonstration of technology, no cooling attempted yet!
28 / 32
Conclusion
I SiC JFET able to operate continuously at high temperature(> 200 °C)I Must be provided with efficient thermal management (RTh =1–2 K/W)I Proposition: introduce dual-side coolingI 3D structure using only high-temperature-rated materials
I Should be able to operate continuously at 300 °C, including passivation(parylene HT or F)
I Proposed etching technique offers satisfying resolutionI Silver sintering used for the interconnects, reliability to be investigated
I Package for demonstration of technology, no cooling attempted yet!
28 / 32
Conclusion
I SiC JFET able to operate continuously at high temperature(> 200 °C)I Must be provided with efficient thermal management (RTh =1–2 K/W)I Proposition: introduce dual-side coolingI 3D structure using only high-temperature-rated materials
I Should be able to operate continuously at 300 °C, including passivation(parylene HT or F)
I Proposed etching technique offers satisfying resolutionI Silver sintering used for the interconnects, reliability to be investigated
I Package for demonstration of technology, no cooling attempted yet!
28 / 32
Conclusion
I SiC JFET able to operate continuously at high temperature(> 200 °C)I Must be provided with efficient thermal management (RTh =1–2 K/W)I Proposition: introduce dual-side coolingI 3D structure using only high-temperature-rated materials
I Should be able to operate continuously at 300 °C, including passivation(parylene HT or F)
I Proposed etching technique offers satisfying resolutionI Silver sintering used for the interconnects, reliability to be investigated
I Package for demonstration of technology, no cooling attempted yet!
28 / 32
This work was funded by Euripides-Catrenes under the grant name“THOR” and FRAE under the grant name “ETHAER”.
29 / 32
Credits
I picture of the Airbus A350: airbus
I picture of the thrust reverser: Hispano-Suizahttp://www.hispano-suiza-sa.com/spip.php?rubrique48
I picture of the Toyota Prius: Picture by Pawel Golsztajn, CC-SA,available on Wikimedia Commons http:
//commons.wikimedia.org/wiki/File:Toyota_Prius.2.JPG
I downhole gas compressor: http://www.corac.co.uk/products/downhole-gas-compressor
I picture of Jupiter: NASAhttp://en.wikipedia.org/wiki/File:PIA04866_modest.jpg
I MOSFET wafers from Mitsubishihttp://compoundsemiconductor.net/cws/article/fab/
38238/1/siliconcarbidewafers
30 / 32
Static and Dynamic Characterization of 60 mΩ JFET
Falahi et Al. “High temperature, Smart Power Module for aircraft actuators”, HiTEN 2013
0 2 4 6 8 10 12Drain-to-Source voltage [V]
0
10
20
30
40
50
60
70
Dra
incu
rren
t[A
]
-50C -10C 27C 70C 107C
160C
196C
234C
270C
49.0 48.8 48.6 48.4time [µs]
50
0
50
100
150
200
250
Vout [
V]
0.2 0.0 0.2time [µs]
310°C
Previous results show that SiC JFETs are attractive for> 200 °C operation:
I rated at 1200 V (or more), several AmpsI Voltage-controlled devicesI No reliability issue related to gate oxide degradation
31 / 32
Properties of some semiconductors
“Classical” wide-bandgap
Si GaAs 3C-SiC
6H-SiC
4H-SiC
GaN Diamond
Bandgap EnergyEg (eV) 1,12 1,4 2,3 2,9 3,2 3,39 5,6
Elec. mobilityµn (cm2.V−1.s−1) 1450 8500 1000 415 950 2000 4000
Hole mobilityµp (cm2.V−1.s−1) 450 400 45 90 115 350 3800
Critical elec. fieldEC (V.cm−1) 3.105 4.105 2.106 2,5.106 3.106 5.106 107
Saturation velocityvsat (cm.s−1) 107 2.107 2,5.107 2.107 2.107 2.107 3.107
Termal cond.λ (W.cm−1.K−1) 1,3 0,54 5 5 5 1,3 20
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