HIGH SPEED COMPUTINGsalishan.ahsc-nm.org/uploads/4/9/7/0/49704495/2019... · Page 1 Welcome The...

The Salishan Conference on

HIGH SPEED COMPUTING

April 22 – 25, 2019

Salishan Lodge Gleneden Beach, Oregon

Welcome

The Association for High Speed Computing welcomes you to the Salishan Conference on High Speed Computing. This conference was founded in 1981 gathering experts in computer architectures, languages, and algorithms to improve communication, develop collaborations, solve problems of mutual interest, and provide effective leadership in the field of high speed computing. Attendance at the conference is by invitation only; we limit attendance to about 150 of the world’s brightest people. Participants are from national laboratories, academia, government and private industry. We keep the conference small to preserve the level of interaction and discussion among the attendees. The conference agenda and selection of participants has been designed to focus discussion on technical issues of relevance to our conference theme: Entering an Era of Extreme Heterogeneity. The speakers have been selected to address our theme and give attendees information about the latest technologies and issues facing high performance computing (HPC). The evening sessions are structured to encourage informal discussions and networking among all participants. If you have any comments or suggestions for future topics and/or speakers, we encourage you to speak to any of the conference committee members and/or complete the electronic survey at the end of the conference (http://salishan.ahsc-nm.org/2019Survey.html). We hope you find this conference stimulating, challenging, and also relaxing – enjoy! Conference Committee: Katie Lewis and Robin Goldstone, LLNL

Ron Brightwell and Simon Hammond, SNL Carolyn Connor and Christoph Junghans, LANL

Logistics

Conference sessions and the Random Access session will be held in the Long House. Lunches and the working dinner will be held in the Council House. For administrative support, please speak to Dee Cadena, Gloria Montoya-Rivera, or Jan Susco, located in the registration area (Salal Room). If you have specific questions regarding audiovisual equipment or network connectivity, please seek out administrative support. Visit our website at: http://salishan.ahsc-nm.org Next Conference Dates: April 20-23, 2020 April 26-29, 2021 April 25-28, 2022

http://salishan.ahsc-nm.org/2019Survey.html

http://salishan.ahsc-nm.org/

Table of Contents

Welcome and Logistics ................................................................................................................ 1 Lodge Map ................................................................................................................................... 2 Sponsorship .................................................................................................................................. 5 Conference Theme ....................................................................................................................... 7 Conference Program

Monday: Keynote Address .......................................................................................... 10 Tuesday: Session 1: Hardware: Driving and Harnessing Extreme Heterogeneity ..... 11

Session 2: Storage Challenges in an Era of Extreme Heterogeneity – As If We Need More I/O Complexity! .......................................................... 12

Wednesday: Session 3: Software: Maneuvering Through the Space of Extreme Heterogeneity ................................................................................ 13 Random Access ............................................................................................ 14 Student Poster Session ................................................................................ 15 Thursday: Session 4: Heterogeneous Applications: Maximizing Benefits While Minimizing Cost ................................................................................. 16

Session 5: Mapping and Optimizing Workflows for Extreme Heterogeneity .............................................................................................. 17

Survey ......................................................................................................................................... 18 Abstracts .................................................................................................................................... 19 Attendees ................................................................................................................................... 32

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Sponsorship

The Salishan Conference on High Speed Computing is administered, hosted, and managed by The Association for High Speed Computing (AHSC). Additional sponsorship for the evening portions of our program is provided by the corporations listed here. One of the highlights of the conference are the informal discussions held each evening. These sessions help us to go beyond the formal presentations to exchange ideas, solve problems and develop friendships. This year the following companies are helping to sponsor the evening sessions:

Advanced Micro Devices, Inc.

Arm

Cray, Inc.

DDN Storage

Dell EMC

D-Wave Systems, Inc.

Hewlett Packard Enterprise

IBM Corporation

Intel Corporation

Mellanox Technologies

Micron Technology, Inc.

NVIDIA Corporation

Penguin Computing

Seagate Government Solutions

We would like to express our gratitude to these companies for their generous support!

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Conference Theme

Entering an Era of Extreme Heterogeneity

Over the last decade, the field of high-performance computing has seen extreme-scale high performance computing systems become increasingly more heterogeneous. Various types of accelerators have been employed to achieve greater levels of compute performance. Adapting applications to use these accelerators effectively has involved a significant amount of effort, not only in code modifications, but also in developing the programming environment. While several applications have been able to take advantage of heterogeneous computing systems, many still have not. Several industry trends seem to indicate that large-scale homogeneous platforms, which contain a single type of compute engine with a relatively straightforward memory hierarchy, will soon be a thing of the past. The diversity that has appeared in computing technology will likely continue to include more specialized hardware components as power and energy concerns motivate the need for more effective use of transistors. The convergence of memory and storage technologies is increasing the complexity and depth of the memory hierarchy. It is becoming more difficult to map programming abstractions to the hardware effectively, and programming models no longer reflect the important costs associated with critical resources. Hardware heterogeneity leads to performance heterogeneity and optimizing in the presence of non-determinism is extremely challenging. Applications are also evolving to include a more diverse set of capabilities. Traditional high-performance computing applications are expanding to include more functionality, such as support for in-situ analytics, uncertainty quantification, and the ability to compose components to build more complex workflows. New applications are being developed in higher-level languages and frameworks, creating scalability and integration challenges. Container technology is being leveraged to overcome the shortcomings of a single, one-size-fits-all software environment. The limitations of large batch-scheduled space-shared computing systems in supporting more diverse sets of applications are becoming more evident. The expansion of heterogeneity in multiple dimensions - compute, memory, storage, systems, software, applications, and usage models - characterizes Extreme Heterogeneity. The five sessions for the Salishan 2019 conference will explore the challenges and ramifications of this coming era of Extreme Heterogeneity. Session 1: Hardware: Driving and Harnessing Extreme Heterogeneity

The recent report from the ASCAC Subcommittee on Future High Performance Computing Capabilities, which considered both post-exascale (2020’s) and post-Moore (2030’s) timeframes, emerged with a common theme: extreme heterogeneity with continued use of digital computing as foundation. Because of the foreseeable end of CMOS scaling and because the interconnect challenge remains at the heart of modern computing, new technologies, some sustaining, some disruptive, and others enabling new computing paradigms, are under test or

under development. These include, but are not limited to, tools and frameworks to democratize specialized hardware design, die stacking and 3D chip technologies, Non-Volatile Memory (NVM) technologies, Photonics, Resistive Computing, Neuromorphic Computing, Quantum Computing, Nanotubes, Graphene, and Diamond Transistors. Some of these technologies remain highly speculative. Detractors point to Amdahl’s Law contention at existing levels of heterogeneity (i.e., persistence of efficiency and performance barriers) and would question the value of drastically increased heterogeneity. Others wonder if extreme heterogeneity itself can be additionally and indirectly harnessed to make better decisions about what to run and where. What is widely agreed is that these evolving and emerging technologies, if adopted, will strongly impact the hardware architectures and software ecosystems of future high performance computing systems, in particular the processor logic itself, the (deeper) memory hierarchy, and new heterogeneous accelerators. This session will explore the current state-of-the-art, challenges, promise, and potential impact on computing architecture for a subset of existing and future HPC hardware technologies and capabilities.

Session 2: Storage Challenges in an Era of Extreme Heterogeneity - As If We Need More I/O Complexity! Extreme heterogeneity brings new challenges to the storage and I/O space. Traditional HPC applications are being refactored to harness the power of GPUs to add intelligent steering to scientific simulations. The output of simulations becomes input to machine learning engines running co-situ, increasing the need to keep data close to the computation for longer periods of time and elevating the importance of “I” versus “O.” I/O subsystems can no longer be designed for checkpointing alone. Furthermore, accelerators with high bandwidth memory add complexity to the data path and increase the performance disparity between memory and I/O subsystems. Meanwhile, the storage hierarchy itself is becoming more heterogeneous. This session will address the following questions: What is the role of storage class memory? Can it actually be used as memory or is it simply a faster block device? Can the I/O pipeline be optimized by embedding FPGAs into storage devices to perform tasks like compression or erasure coding? Could this trifecta of extreme heterogeneity, evolving I/O patterns, and innovative new storage technologies be enough to steer HPC application developers away from the comfortable yet constraining POSIX I/O model? Session 3: Software: Maneuvering Through the Space of Extreme Heterogeneity With increasing heterogeneity, the software stack and system libraries have the hard job of hiding some of the hardware heterogeneity from the application developer. Possible abstraction layers could be, but are not limited to, runtimes and programming models and hardware-abstraction libraries. It is a difficult task to pick the layers at a level coarse enough to be usable for the application, but fine enough to capture all the details of the hardware functionality. Another important aspect is whether these abstraction layers should be in user- or system-space and hence be part of the vendor-provided stack. This distinction can be especially important for resource management activities, such as scheduling tasks on different portions of the hardware. This analysis also plays in the direction of abstracting different types of accelerators, e.g., GPUs vs. FPGAs and such.

Session 4: Heterogeneous Applications: Maximizing Benefits While Minimizing Cost Extreme heterogeneity offers exciting opportunities for algorithm improvements with potential reductions in complexity, energy usage, and memory footprints. At the same time, heterogeneity creates many challenges for high performance computing applications, including proper delegation of work in a load-balanced way, synchronization across different accelerators, varying bit precision, and mismatched memory hierarchies. Include the difficulty of dealing with disparate instruction sets and attempting to increase the effectiveness of accelerators for more general-purpose computing, and the challenges become even more daunting. In this session, we will explore potential payoffs of extreme heterogeneity for applications, while recognizing and addressing challenges of developing applications in this environment. Session 5: Mapping and Optimizing Workflows for Extreme Heterogeneity Extreme heterogeneity can apply to workloads and hardware systems. For both concerns, identifying a strong mapping is critical to improving performance and efficiency, and ultimately scientific throughput. We might expect the mapping to need to be dynamically generated and require workloads and computing to adapt to a changing system environment or artifacts from workloads. In this session we will consider how a future extreme heterogeneity-based system and workload might be operated and used. Specifically, we will consider the use of technologies such as Cloud, efficient scheduling of resources, and migration of workloads to optimized accelerators or near-data processing. In addition, we are interested in the consideration of end-to-end workflow optimizations.

Conference Program

Entering an Era of Extreme Heterogeneity

Monday April 22, 2019

4:30 - 7:00 pm Registration (Salal Room) 6:00 pm Welcome/Keynote Address Title: From Extreme Heterogeneity to Artificial Intelligent Systems

Speaker: Dimitri Kusnezov, Department of Energy

7:00 pm Reception and Informal Discussions (Immediately following the Keynote in the Council House)

Tuesday April 23, 2019

7:00 am Registration opens (Salal Room) Breakfast available (Terrace) 8:30 am Session 1: Hardware: Driving and Harnessing Extreme Heterogeneity

Chair: Carolyn Connor Title: 3D Integration and Highly Interconnected Systems Speaker: Robert Patti, NHanced Semiconductors, Inc. Title: Nantero NRAM Defines a New Category of “Memory Class Storage” Speaker: Bill Gervasi, Nantero Title: Heterogeneous Accelerators of the Memory, by the Memory, and for the Memory Speaker: Arun Rodrigues, Sandia National Laboratories 10:00 am Break Refreshments available (Terrace) 10:30 am Title: Next Gen Memory Speaker: Wendy Elsasser, Arm 11:00 am Panel Discussion

Tuesday April 23, 2019

12:00 pm Lunch (Council House) 1:30 pm Session 2: Storage Challenges in an Era of Extreme

Heterogeneity – As If We Need More I/O Complexity!

Chair: Robin Goldstone

Title: Persistent Memory for High-Performance Applications

Speaker: Tom Coughlin, Coughlin Associates

Title: Accelerating Scientific Discovery with Key-Value Storage Speaker: Brad Settlemyer, Los Alamos National Laboratory

Title: Heterogeneity, Schmeterogeneity. Object, Schmobject. Long Live POSIX. Speaker: John Bent, DDN Storage 3:00 pm Break Refreshments available (Terrace) 3:30 pm Title: Persistence in a Heterogeneous World Speaker: Paolo Faraboschi, Hewlett Packard Enterprise 4:00 pm Panel Discussion 6:00 pm Dinner and Student Research Showcase 8:00 pm Reception and Informal Discussions (Immediately following dinner in the Cedar Tree Room)

Wednesday April 24, 2019

7:00 am Breakfast available (Terrace)

8:30 am Session 3: Software: Maneuvering Through the Space of Extreme Heterogeneity Chair: Christoph Junghans

Title: Compilers Must be Fast and so FPGAs Will Never Work! Maybe CGRAs Will Save Us?

Speaker: Hal Finkel, Argonne National Laboratory Title: Futurize All the Things! Harnessing AMTs to Run Billions of Tasks on Modern Computing Architectures Speaker: Hartmut Kaiser, Louisiana State University Title: A Software Architecture for Future Multi-Physics Applications Speaker: David Daniel, Los Alamos National Laboratory 10:00 am Break Refreshments available (Terrace)

10:30 am Title: HPC Performance Tools: Myths and Facts Speaker: Bernd Mohr, Juelich Supercomputing Centre 11:00 am Panel Discussion


12:00 pm Lunch on your own

- or -

Advocacy for Women in High Speed Computing Luncheon* Cedar Tree Room – 12:00-2:00 pm *For attendees who purchased at time of registration. No registrations accepted at conference. No exceptions. 1:30 pm No Scheduled Sessions 5:00 pm Random Access (Long House)

We invite Salishan 2019 attendees who want to propose a Random Access talk to sign-up online (maximum of one talk per participant) at: http://salishan.ahsc-nm.org/2019RandomAccess.html. Only a talk title and abstract tweet (max. 280 characters) are needed at time of sign-up. Alternatively, sign-ups can be done in person with the conference organizers. Sign-ups close Tuesday at 8:00 pm. In fairness to at-large attendees, invited session speakers are requested to refrain from submitting proposals for Random Access talks. On Wednesday morning, a comprehensive list of talk titles and tweet abstracts will be published online for voting (an email will be sent to attendees with the link to vote). Every attendee will be allowed three equally-weighted votes until polls close on Wednesday at 1:00 pm. The talks with the most votes will be presented in the Random Access session starting on Wednesday at 5:00 pm. The final agenda of talks will also be posted online by Wednesday at 3:00 pm.

http://salishan.ahsc-nm.org/2019RandomAccess.html


8:00 pm Reception and Informal Discussions (Council House) Student Poster Session (Council House)

This conference selects and hosts students from various universities, inviting them to present posters and discuss their research with our Salishan participants. All conference attendees are encouraged to visit with this year’s students.

Neil Butcher

University of Notre Dame / Sandia National Laboratories “Optimizing Dense Matrix Multiply for Multilevel Memory”

Daniel Dunning

Texas Tech University / Los Alamos National Laboratory “Adaptive Mesh Refinement in the Fast Lane”

Roland Green

Purdue University / Sandia National Laboratories “Exploring Alternative Evaluation Methodologies for GPGPUs”

Nelson Ho

University of San Diego / Lawrence Livermore National Laboratory “Managing Near Memory Accelerators for Sparse Data Structures:

A Software Perspective”

Sumathi Lakshmiranganatha University of Wyoming / Los Alamos National Laboratory

“Performance Study and Optimization of FleCSALE Using Tabular Equation of State”

Philip Taffet

Rice University / Lawrence Livermore National Laboratory “Understanding Congestion in High Performance Interconnection

Networks Using Sampling”

Thursday April 25, 2019

7:00 am Breakfast available (Terrace) 8:30 am Session 4: Heterogeneous Applications: Maximizing

Benefits While Minimizing Cost Chair: Katie Lewis Title: Heterogeneous Supercomputing: HPC and the U.S. Cancer Moonshot on Sierra Speaker: Frederick Streitz,

Lawrence Livermore National Laboratory Title: Load Balancing on Many-Core and Accelerated Systems Speaker Cameron Smith, Rensselaer Polytechnic Institute Title: Exascale-Class Applications on the

Reconfigurable EuroEXA Prototype: Lessons Learnt and Progress So Far

Speaker: Paul Carpenter, Barcelona Supercomputing Center/EuroEXA

10:00 am Break Refreshments available (Terrace) 10:30 am Title: Scientific Applications on Heterogeneous Architectures (Data Analytics and the Intersection of HPC and Edge Computing) Speaker: Michela Taufer, University of Tennessee, Knoxville 11:00 am Panel Discussion

Thursday April 25, 2019

12:00 pm Lunch (Council House) 1:30 pm Session 5: Mapping and Optimizing Workflows for Extreme Heterogeneity Chair: Simon Hammond Title: Scheduling Heterogeneous Dynamic Workloads Speaker: Tom Scogland,

Lawrence Livermore National Laboratory Title: Workflow Management in a Heterogeneous

World Speaker: Ewa Deelman, University of Southern California Title: Exploratory Analysis in an “In Situ World” Speaker: Janine Bennett, Sandia National Laboratories 3:00 pm Break Refreshments available (Terrace) 3:30 pm Title: Heterogeneous Workflows: Searching for Commonalities in the Cloud Speaker: Samuel Skillman, Descartes Labs 4:00 pm Panel Discussion 5:00 pm Reception and Informal Discussions (Council House)

2019 Salishan Conference on High Speed Computing SURVEY

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Thank you for participating in this year’s conference. It would be appreciated if you can take a few minutes to

complete this brief online survey:



Abstracts

Keynote Address

From Extreme Heterogeneity to Artificial Intelligent Systems

Dimitri Kusnezov Department of Energy

Extreme heterogeneity is an important descriptor for the classes of broad technologies emerging for artificial intelligence important to the Department’s missions. Earlier this year, the President signed an Executive Order on Maintaining American Leadership in Artificial Intelligence, where he stated that “Continued American leadership in Artificial Intelligence is of paramount importance to maintaining the economic and national security of the United States.” Secretary of Energy Perry also launched the DOE Artificial Intelligence Program that supports this vision. DOE’s historic leadership in high performance computing, delivering and deploying novel technologies at scale, and pressing missions increasingly inundated in data, present leadership opportunities for DOE in this space. These challenges include how we develop uncertainty quantification for learning systems, cognitive computing for hybrid AI/HPC architectures and decision support in intelligent systems located at the sources of data. I will outline DOE’s strategy in this emergent domain and the opportunities that exist to build on our expertise in the innovative application of technologies to national scale challenges.

Session 1

Hardware: Driving and Harnessing Extreme Heterogeneity

3D Integration and Highly Interconnected Systems

Robert Patti NHanced Semiconductors, Inc.

Heterogeneity is an excellent way to achieve major system performance gains, as increasingly diverse capabilities can be brought to bear on each problem. But how can collections of diverse processing elements be transformed into an agile unified system? In order to skillfully direct an orchestra of components, we must examine and refocus our paradigms and design priorities. In this talk, we will discuss using 3D integration and tightly coupled intelligent networking to create seamless, flexible communication and collaboration in advanced heterogeneous systems.

Nantero NRAM Defines a New Category of “Memory Class Storage”

Bill Gervasi Nantero

Nantero NRAM is an exciting new memory based on carbon nanotubes. NRAM has the potential to replace DRAM as the main memory of the future. It seems to combine the best of all features: full DRAM speed, non-volatility with centuries of data retention, unlimited write endurance, wide operating temperature range, low power, low cost, and scalable to hundreds of gigabits per die in the next decade. This presentation will describe the fundamental operating characteristics of carbon nanotube memory, show test results for performance and describe models for future generations of devices down to 5nm logic processes. The talk will also cover system applications for plug and play memory modules from servers through workstations and notebooks. Significant benefits are described for other applications including storage devices such as SSDs, and also the benefits for immunity from power loss for artificial intelligence architectures. A new JEDEC standard under development, the DDR5 NVRAM, will be disclosed as well.

Session 1

Hardware: Driving and Harnessing Extreme Heterogeneity

Heterogeneous Accelerators of the Memory, by the Memory, and for the Memory

Arun Rodrigues

Sandia National Laboratories

For many applications, memory continues to be the latency and bandwidth bottleneck. A wide variety of emerging memory technologies and architectures are attempting to alleviate these constraints, but they face substantial hurdles in providing enough useful bandwidth to the processor. This talk will explore several complementary efforts to improve the performance of HPC systems by adding accelerators with a memory focus.

Next Gen Memory

Wendy Elsasser Arm

Traditional memory sub-systems are being augmented with emerging memory technologies increasing the complexity and depth. Knowledge of these emerging technologies is crucial to analyze the trade-offs in complexity, energy, and performance. This talk will look at current and future memory technologies, where they fit into the system, and interface technologies that can be leveraged to access them.

Session 2 Storage Challenges in an Era of Extreme Heterogeneity –

As If We Need More I/O Complexity!

Persistent Memory for High-Performance Applications

Tom Coughlin Coughlin Associates

A major shift in computing architectures is underway, enabled by developments in fast persistent memories (PMs) that will replace or supplement volatile memories. This shift is being driven by computational workloads created by IoT and big data applications. This talk will focus on emerging persistent memories (MRAM, RRAM, PCM, FRAM, etc.), their applications for logging and caching and their use in applications such as machine learning. It will also look at the development of protocols (such as NVMe, NVMe-oF, RDMA) and software models developed by SNIA and other trade organizations that allow maximal use of these new memory/storage technologies. We will also discuss the future of persistent memory and its role in the growing heterogenous storage and memory hierarchy.

Accelerating Scientific Discovery with Key-Value Storage

Brad Settlemyer Los Alamos National Laboratory

The popularity of key-value storage has rapidly increased in the last several years, enabling the rise of massively distributed cloud computing services. This fundamental paradigm shift has displaced traditional file system and database installations and is disrupting storage system access at all levels ranging from user applications to storage hardware. In this talk we explore how key-value storage differs from existing storage system architectures and why the use of variable-length key-value pairs has initiated a paradigm shift in the design of storage systems. But further, we explore what key-value storage means for high-performance computing and how it may accelerate scientific discovery. Finally, we discuss why the adoption of key-value storage may be in its early stages, and the disruptions caused by key-value storage may only be at the beginning.

Session 2 Storage Challenges in an Era of Extreme Heterogeneity –

As If We Need More I/O Complexity!

Heterogeneity, Schmeterogeneity. Object, Schmobject. Long Live POSIX.

John Bent DDN Storage

Perhaps heterogeneity at the compute layer is scary; at the storage layer, it shouldn’t be. We can hide it for casual users and expose it for power users. In this talk, we will reexamine the trends that have brought us heterogeneous storage (and the tiering it implies) and consider whether heterogeneous storage remains in our future. We will discuss how heterogeneity affects storage interfaces (if at all) and will conclude with a brief examination of other economic trends in storage and their implications.

Persistence in a Heterogeneous World

Paolo Faraboschi Hewlett Packard Enterprise

The improvement slowdown of general purpose processing and memory technologies in the last decade has caused the computing industry to revisit the customization and specialization fronts, and advance approaches based on heterogeneity. When it comes to the data persistence layer (a.k.a. storage), heterogeneity comes in different forms: compute, memory, and usage. Accelerators, and their embedded high-bandwidth memory, need first-class access to the persistence tier. New memory technologies, such as NVM variants, can offer significant performance improvement vs. flash, but are still too expensive for capacity. Use cases beyond defensive I/O (checkpointing) require sharing, fine grain memory accesses, and object abstractions that don’t well fit in the traditional standard HPC storage hierarchy. This talks argues that the persistence system needs to fully embrace heterogeneity in these three distinct aspects. Industry-wide efforts promoting new memory-semantics interconnect standards could provide the necessary support, are promising, but have not yet fully matured. As an example, the talk concludes with an overview of the technologies that HPE is developing as part of the PathForward program, in collaboration with the US DOE, to use Gen-Z as the underlying transport mechanism to access the persistence layer that ties together heterogeneous memory technologies, accelerators and near data processing technology, and novel usage models that blur the boundaries between memory and storage.

Session 3 Software: Maneuvering Through the Space of

Extreme Heterogeneity

Compilers Must be Fast, and So FPGAs Will Never Work! Maybe CGRAs Will Save Us?

Hal Finkel

Argonne National Laboratory

With the end of Moore's Law, Dennard scaling, and other trends underlying the HPC industry for decades, we're naturally driven toward solutions which more-efficiently use a fixed transistor-power budget. Field Programmable Gate Arrays (FPGAs), for example, have long been suggested as a potential solution in this space. In this talk, I'll argue that while FPGAs are a terrific technology, they can't serve as first-class accelerators in HPC systems due to user-productivity constraints: compilers for FPGAs are very slow, and compilers can't be that slow; application kernels can be big, and FPGAs can't be that big. Current-day FPGAs also lack the sophisticated memory subsystems practically required by modern HPC applications. The good news is that this doesn't mean that reconfigurable computing in HPC is dead. Coarse-Grained Reconfigurable Architectures (CGRAs) offer a potential solution, and moreover, FPGAs have themselves been growing CGRA-like features for years. I'll also touch on how we can achieve performance portability in practice, which requires autotuning, and provides yet another reason why compilers must be fast.



Futurize All Things!

Harnessing AMTs to Run Billions of Tasks on Modern Computing Architectures

Hartmut Kaiser Louisiana State University

With the advent of modern computer architectures characterized by — amongst other things — many-core nodes, deep and complex memory hierarchies, heterogeneous subsystems, and power-aware components, it is becoming increasingly difficult to achieve best possible application scalability and satisfactory parallel efficiency. The community is experimenting with new programming models that rely on finer-grain parallelism, and flexible and lightweight synchronization, combined with work-queue-based, message-driven computation. The recently growing interest in the C++ programming language in industry and in the wider community increases the demand for libraries implementing those programming models for the language. In this talk, we present a new asynchronous C++ parallel programming model that is built around lightweight tasks and mechanisms to orchestrate massively parallel (and distributed) execution. This model uses the concept of (Standard C++) futures to make data dependencies explicit, employs explicit and implicit asynchrony to hide latencies and to improve utilization, and manages finer-grain parallelism with a work-stealing scheduling system enabling automatic load balancing of tasks. We have implemented such a model as a C++ library exposing a higher-level parallelism API that is fully conforming to the existing C++11/14/17 standards and is aligned with the ongoing standardization work. This API and programming model has shown to enable writing parallel and distributed applications for heterogeneous resources with excellent performance and scaling characteristics.



A Software Architecture for Future Multi-Physics Applications

David Daniel

Los Alamos National Laboratory

The simulation of complex multi-physics problems faces two key challenges on future heterogeneous exascale-class computers: abstracting exascale hardware from multi-physics code development, and solving integral problems at multiple physical scales. The Ristra project at Los Alamos National Laboratory is developing a software framework (FleCSI) that limits the impact of disruptive computer technology on the development of multi-physics codes. FleCSI enables the adoption of novel programming models and data management methods to address the challenges and diversity of new technology. Simultaneously, Ristra is exploring the use of multi-scale numerical methods that offer improved physics fidelity and computing efficiency. This talk will discuss our design approach, progress in developing a diverse suite of multi-physics applications, as well as reflecting on lessons learned from the from the project so far.

HPC Performance Tools: Myths and Facts

Bernd Mohr Juelich Supercomputing Centre

Current high-end HPC systems consist of complex configurations of increasingly heterogeneous components. In addition, the hard- and software configuration can change dynamically due to fault recovering processes or power saving efforts. Deep hierarchies of large, complex software components are needed to operate and use them. Developing efficient and high-performance application software for these systems is challenging. Therefore, sophisticated performance measurement and analysis capabilities are required.

After a very short introduction of the most important terms and methods of performance measurement and analysis of parallel programs, the presentation will review some of the most common (mis)conceptions in this area and will debunk them either as “myth,” “it depends,” or “fact.” The main part of the talk will discuss the current state-of-the-art in freely available open-source and commercial offerings of parallel performance measurement and analysis tools. A special focus will be on the issues of scalability of performance tools and the analysis of accelerated application codes.

Session 4 Heterogeneous Applications:

Maximizing Benefits While Minimizing Cost

Heterogeneous Supercomputing: HPC and the U.S. Cancer Moonshot on Sierra

Frederick Streitz Lawrence Livermore National Laboratory

The marriage of experimental science with simulation has been a fruitful one – the fusion of HPC-based simulation and experimentation moves science forward faster than either discipline alone, rapidly testing hypotheses and identifying promising directions for future research. The emergence of machine learning at scale promises to bring a new type of thinking into the mix, incorporating data analytics techniques alongside traditional HPC to accompany experiment. Such explorations can develop highly complex workflows that benefit greatly from heterogeneous computing. I will discuss one such complex workflow: a multi-scale investigation of Ras biology on a realistic membrane that makes effective use of the Sierra supercomputer at LLNL.

Load Balancing on Many-Core and Accelerated Systems

Cameron Smith

Rensselaer Polytechnic Institute Load balancing within and between many-core and accelerator-based nodes is an important part of achieving high application performance. The combination of tools and methods applied to achieve these goals must consider application requirements, and hardware limitations. Experience to date on GPU systems, Cray XC40, and up to 2^20 processes of the IBM BlueGene/Q provides system insight and new methods. From these experiences a path forward to achieve load balancing within and between accelerated nodes is planned. Tools and methods for load balancing must execute quickly relative to the runtime of the simulation and satisfy multiple application criteria. Quick execution requires that the load balancing tools provide APIs for in-memory integration and, when possible, operate within the same memory space as the simulation. The methods exposed by the APIs range from slower global procedures that can handle highly imbalanced partitions to faster localized procedures targeted at partition improvement. One tool being developed to meet some of these needs is EnGPar. It provides quick multi-criteria partition improvement procedures using diffusive methods. Applications using EnGPar range from PHASTA CFD using finite elements, FUN3D CFD using node-centered finite volume, to XGCm particle plasma physics on unstructured meshes.



Exascale-Class Applications on the Reconfigurable EuroEXA Prototype: Lessons Learnt and Progress So Far

Paul Carpenter

Barcelona Supercomputing Center The EuroEXA project is co-designing and implementing a petascale-level prototype based on a novel processing unit with FPGA acceleration. The project aims to provide the template for an upcoming exascale system through a holistic approach, innovating across the technology and the application/system software pillars. This talk will outline how the project is optimising the entire stack from language runtimes to low-level kernel drivers in order to meet the needs of a rich set of Exascale-class applications, across climate and weather, physics and energy, and life sciences and bioinformatics. It will explain how the applications have been used to drive the co-design of the architecture, and how they are being ported and optimized for the EuroEXA prototypes. We will describe how the unique capabilities of the EuroEXA architecture, e.g. coherence islands and reconfigurable computing (FPGAs), will be exploited by the applications through portable programming environments (MPI, GPI, OpenStream, OmpSs, Maxeler toolchain and PSyClone). This talk will share the preliminary results from the first year of the project, including the successes so far and unexpected challenges, and it will outline our strategies and plans for the next three years. It will conclude with some thoughts on the future of high-performance computing, the challenges of performance portability, and how applications will likely have to be restructured for exascale.



Convergence of Data Generation and Analytics in the Era of Heterogeneous Applications and Edge Computing

Michela Taufer

University of Tennessee, Knoxville This talk discusses two emerging trends in computing (i.e., the convergence of data generation and analytics, and the emergence of edge computing) and how these trends can impact heterogeneous applications. Next-generation supercomputers, with their extremely heterogeneous resources and dramatically higher performance than current systems, will generate more data than we need or, even, can handle. At the same time, more and more data is generated at the “edge,” requiring computing and storage to move closer and closer to data sources. The coordination of data generation and analysis across the spectrum of heterogonous systems including supercomputers, cloud computing, and edge computing adds additional layers of heterogeneity to applications’ workflows. More importantly, the coordination can neither rely on manual, centralized approaches as it is predominately done today in HPC nor exclusively be delegated to be just a problem for commercial Clouds. This talk presents case studies of heterogenous applications in precision medicine and precision farming that expand scientist workflows beyond the supercomputing center and shed our reliance on large-scale simulations exclusively, for the sake of scientific discovery.

Scheduling Heterogeneous Dynamic Workloads

Tom Scogland Lawrence Livermore National Laboratory

As the heterogeneity of our hardware has been increasing, so has the heterogeneity of application pipelnes running on the hardware. One extreme example required running six different job types, spanning 1,000 nodes but one instance to 14,000 instances on two cores each, continually creating jobs of each shape based on job completion and the results of a feedback loop through a machine learning algorithm adjusting the job queue based on importance. This talk will discuss some recent dynamic heterogeneous workloads of that type that have been targeting Sierra and how we address, and plan to address, some of the uniqueissues of extremely heterogeneous systems and software in the Flux resource manager.

Session 5

Mapping and Optimizing Workflows for Extreme Heterogeneity

Workflow Management in a Heterogeneous World

Ewa Deelman University of Southern California, Information Sciences Institute

Science applications are continuing to increase in size and complexity, consuming ever more computing resources to produce simulation results and extract knowledge and insight from vast amounts of measured and simulated data. These applications may consist of an ensemble of workflows that implements a recursive search through a multidimensional space, where each workflow is a mix of interdependent high-performance and high-throughput computations. Meanwhile, the computing resources and software stacks charged with the execution of these workflows continue to grow in complexity to include tightly-coupled heterogeneous processors and multimode memory systems. In this highly complex, evolving and dynamic environment, automation is critical to relieving scientists as much as possible from the mundane and, in many cases, time-consuming tasks of data flow management, job scheduling, fault recovery and workflow adaptation. This talk examines the workflow management challenges in these environments, exploring issues of resource control, job and data scheduling, application and system monitoring, and fault tolerance. The talk will be given in the context of the Pegasus Workflow Management System and the applications it supports.

Exploratory Analysis in an “In Situ World”

Janine Bennett

Sandia National Laboratories

Simulations on HPC systems can generate data up to five orders of magnitude greater than the storage capacity of the system. This bottleneck poses unique challenges for exploratory analysis, in which scientists glean insights by formulating and testing hypotheses using their simulation output. Historically, exploratory analysis has been performed post hoc, after the simulation is complete, with interactive exploration occurring in the year(s) after the output is generated. However, current approaches to managing the HPC I/O bottleneck involve moving some subset of exploratory analysis in situ, as the simulation is running. In this talk I will highlight unique research challenges in operating and mapping exploratory analysis workflows that are posed by the in situ paradigm shift. I will also present recent methodological and algorithmic research results that begin to mitigate some of these challenges.

Session 5

Mapping and Optimizing Workflows for Extreme Heterogeneity

Heterogeneous Workflows: Searching for Commonalities in the Cloud

Samuel Skillman Descartes Labs

The landscape of scientific computing is changing rapidly with the advent of massive commercial cloud availability. At Descartes Labs we can perform computations over petabytes of data at the scale of hundreds of thousands of cores without owning a single physical server. However, cloud native computation faces many of the same fundamental challenges as traditional high performance computing, including how to orchestrate many different moving pieces of large scale heterogeneous computation and analysis while allowing computational results to be reproducible, discoverable, shareable and secure. We will discuss some of the technological trends that we have identified through our business, and how we have incorporated different workflow management tools in order to scale as an organization. In particular, we will talk about how open-source cloud native technologies such as Kubernetes, Spinnaker, and Kubeflow Pipelines allow our Scientists and Engineers to rapidly and efficiently iterate without breaking things. Finally, we will discuss the patterns that emerge out of data intensive multi-stage analysis workflows which often involve a mixture of highly heterogeneous hardware and computation.

Attendees

Marc Adams NVIDIA [email protected]

Jamie Bramwell Lawrence Livermore National Laboratory [email protected]

Heidi Ammerlahn Sandia National Laboratories [email protected]

Ron Brightwell Sandia National Laboratories [email protected]

Mark Anderson National Nuclear Security Administration [email protected]

Jason Burmark Lawrence Livermore National Laboratory [email protected]

James Ang Pacific Northwest National Laboratory [email protected]

Neil Butcher University of Notre Dame [email protected]

Richard Arthur GE Global Research [email protected]

Dee Cadena The Association for High Speed Computing [email protected]

Jonathan Beard Arm [email protected]

Joann Campbell Los Alamos National Laboratory [email protected]

Janine Bennett Sandia National Laboratories [email protected]

William Carlson IDA Center for Computing Sciences [email protected]

John Bent DDN Storage [email protected]

Paul Carpenter Barcelona Supercomputing Center/EuroEXA [email protected]

Martin Berzins SCI Institute/University of Utah [email protected]

Laura Carrington EP Analytics/PMaC Lab [email protected]

Shekhar Borkar Qualcomm [email protected]

Jonathan Carter Lawrence Berkeley National Laboratory [email protected]

mailto:[email protected]







Barbara Chapman Brookhaven National Laboratory [email protected]

David Daniel Los Alamos National Laboratory [email protected]

Andrew Chien Argonne National Laboratory [email protected]

Marcus Daniels D-Wave Systems, Inc. [email protected]

Giridhar Chukkapalli Marvell Semiconductor, Inc. [email protected]

David Dawson Lawrence Livermore National Laboratory [email protected]

Almadena Chtchelkanova National Science Foundation [email protected]

Bronis de Supinski Lawrence Livermore National Laboratory [email protected]

Robert Clay Sandia National Laboratories [email protected]

Ewa Deelman University of Southern California [email protected]

Guillaume Colin de Verdiere CEA [email protected]

Scott Doebling Los Alamos National Laboratory [email protected]

S. Scott Collis Sandia National Laboratories [email protected]

David Donofrio Lawrence Berkeley National Laboratory [email protected]

Carolyn Connor Los Alamos National Laboratory [email protected]

Sudip Dosanjh LBNL/NERSC [email protected]

René Copeland D-Wave Systems, Inc. [email protected]

Erik Draeger Lawrence Livermore National Laboratory [email protected]

Tom Coughlin Coughlin Associates [email protected]

Nicolas Dube Hewlett Packard Enterprise [email protected]

Candace Culhane Los Alamos National Laboratory [email protected]

Daniel Dunning Texas Tech University [email protected]












Tarek El-Ghazawi George Washington University [email protected]

Maya Gokhale Lawrence Livermore National Laboratory [email protected]

Wendy Elsasser Arm [email protected]

Robin Goldstone Lawrence Livermore National Laboratory [email protected]

Paolo Faraboschi Hewlett Packard Enterprise [email protected]

Elsa Gonsiorowski Lawrence Livermore National Laboratory [email protected]

Charlie Fazzino ExxonMobil [email protected]

Brent Gorda Arm [email protected]

Andrew Feldman Cerebras Systems [email protected]

Richard Graham Mellanox [email protected]

Wu-chun Feng Virginia Tech [email protected]

Jeffrey Grandy Lawrence Livermore National Laboratory [email protected]

Hal Finkel Argonne National Laboratory [email protected]

Keith Gray BP [email protected]

Joerg Gablonsky The Boeing Company [email protected]

Roland Green Purdue University [email protected]

Alan Gara Intel Corporation [email protected]

William Gropp University of Illinois at Urbana-Champaign [email protected]

Ada Gavrilovska Georgia Institute of Technology [email protected]

Samuel Gutierrez Los Alamos National Laboratory [email protected]

Bill Gervasi Nantero [email protected]

Mary Hall University of Utah [email protected]


















Scot Halverson Los Alamos National Laboratory [email protected]

Larry Hoelzeman Cray, Inc. [email protected]

Simon Hammond Sandia National Laboratories [email protected]

Wayne Howell IBM Corporation [email protected]

William Harrod IARPA [email protected]

Michael Ignatowski Advanced Micro Devices, Inc. [email protected]

David Hass NVIDIA [email protected]

Andrew Jones NAG [email protected]

Martin Herboldt Boston University [email protected]

Christoph Junghans Los Alamos National Laboratory [email protected]

Andy Herdman AWE plc [email protected]

David Kahaner Asian Technology Information Program [email protected]

Michael Heroux Sandia National Laboratories [email protected]

Hartmut Kaiser Louisiana State University [email protected]

Nelson Ho Lawrence Livermore National Laboratory [email protected]

Laxmikant Kale University of Illinois [email protected]

Thuc Hoang National Nuclear Security Administration [email protected]

Laurence Kaplan Cray, Inc. [email protected]

Torsten Hoefler ETH Zurich Universitaetsstrasse 6 [email protected]

Beth Kaspar Los Alamos National Laboratory [email protected]

Robert Hoekstra Sandia National Laboratories [email protected]

Jeff Kirk Dell EMC [email protected]

















Kevin Kissell Google [email protected]

James Laros Sandia National Laboratories [email protected]

Tom Klitsner Sandia National Laboratories [email protected]

Hermann Lederer Max Planck Computing and Data Facility [email protected]

Fairy Knappe Penguin Computing [email protected]

Katherine Lewis Lawrence Livermore National Laboratory [email protected]

Peter Kogge University of Notre Dame [email protected]

Alex Long Los Alamos National Laboratory [email protected]

Douglas Kothe Oak Ridge National Laboratory [email protected]

Robert Lowrie Los Alamos National Laboratory [email protected]

Michael Krajecki University of Reims [email protected]

Vincent Lucarelli National Security Agency [email protected]

Jay Kruemcke SUSE [email protected]

Robert Lucas University of Southern California [email protected]

Dimitri Kusnezov Department of Energy [email protected]

Arthur Maccabe Oak Ridge National Laboratory [email protected]

John LaBry Micron Technology [email protected]

Satheesh Maheswaran AWE plc [email protected]

Sumathi Lakshmiranganatha University of Wyoming [email protected]

Sid Mair Penguin Computing [email protected]

Arvindh Lalam nCorium [email protected]

Michel McCoy Lawrence Livermore National Laboratory [email protected]
















Pankaj Mehra Samsung Electronics [email protected]

Jesse Otero Department of Defense [email protected]

Thomas Metzger Intel Corporation [email protected]

Yoonho Park IBM Corporation [email protected]

Ronald Minnich Google [email protected]

Robert Patti NHanced Semiconductors, Inc. [email protected]

Bernd Mohr Juelich Supercomputing Centre [email protected]

Joseph Pawlowski Micron Technology, Inc. [email protected]

Stephen Monk Sandia National Laboratories [email protected]

Stephen Pawlowski Micron Technology, Inc. [email protected]

Gloria Montoya-Rivera Los Alamos National Laboratory [email protected]

Olga Pearce Lawrence Livermore National Laboratory [email protected]

David Mountain Department of Defense [email protected]

Robinson Pino Department of Energy [email protected]

Rob Neely Lawrence Livermore National Laboratory [email protected]

Stephen Poole Los Alamos National Laboratory [email protected]

Henry Newman Seagate Government Solutions [email protected]

Loïc Pottier University of Southern California [email protected]

Jeffrey Nichols Oak Ridge National Laboratory [email protected]

Terri Quinn Lawrence Livermore National Laboratory [email protected]

Ron Oldfield Sandia National Laboratories [email protected]

Tim Randles Los Alamos National Laboratory [email protected]














Gabriel Rockefeller Los Alamos National Laboratory [email protected]

Pavel Shamis Arm [email protected]

Arun Rodrigues Sandia National Laboratory [email protected]

Gilad Shainer Mellanox Technologies [email protected]

Michael Rosenfield IBM Corporation [email protected]

Horst Simon Lawrence Berkeley National Laboratory [email protected]

Robert Ross Argonne National Laboratory [email protected]

Samuel Skillman Descartes Labs [email protected]

Michael Schulte Advanced Micro Devices, Inc. [email protected]

Anthony Skjellum University of Tennessee at Chattanooga [email protected]

Martin Schulz Technical University of Munich [email protected]

Cameron Smith Rensselaer Polytecnic Institute [email protected]

Tom Scogland Lawrence Livermore National Laboratory [email protected]

George Stelle Los Alamos National Laboratory [email protected]

Rick Scott DDN Storage [email protected]

Rick Stevens Argonne National Laboratory [email protected]

Steve Scott Cray, Inc. [email protected]

Erik Strack Sandia National Laboratories [email protected]

Bradley Settlemyer Los Alamos National Laboratory [email protected]

Frederick Streitz Lawrence Livermore National Laboratory [email protected]

James Sexton IBM Corporation [email protected]

Samantika Sury Intel Corporation [email protected]



















Jan Susco Lawrence Livermore National Laboratory [email protected]

Robert Wisniewski Intel Corporation [email protected]

Philip Taffet Rice University [email protected]

Michael Wolf Sandia National Laboratories [email protected]

Michela Taufer University of Tennessee, Knoxville [email protected]

Michael Wolfe NVIDIA [email protected]

Jon Trantham Seagate Government Solutions [email protected]

Peter Ungaro Cray, Inc. [email protected]

Ash Vadgama AWE plc [email protected]

Jeffrey Vetter Oak Ridge National Laboratory [email protected]

Michael Vildibill Hewlett Packard Enterprise [email protected]

Richard Vuduc Georgia Institute of Technology [email protected]

Tad White IDA Center for Computing Sciences [email protected]

Walter Witkowski Sandia National Laboratories [email protected]













Conference Notes

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