HIGH SPEED FIR ADAPTIVE FILTER FOR RADAR APPLICATIONS · 2016-11-01 · ii BONAFIDE CERTIFICATE...

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HIGH SPEED FIR ADAPTIVE FILTER FOR

RADAR APPLICATIONS

A PROJECT REPORT

Submitted by

LAVANYA.M

Register No: 14MAE008

in partial fulfillment for the requirement of award of the degree

of

MASTER OF ENGINEERING

in

APPLIED ELECTRONICS

Department of Electronics and Communication Engineering

KUMARAGURU COLLEGE OF TECHNOLOGY

(An autonomous institution affiliated to Anna University, Chennai)

COIMBATORE-641049

ANNA UNIVERSITY: CHENNAI 600 025

APRIL 2016

ii

BONAFIDE CERTIFICATE

Certified that this project report titled, “HIGH SPEED FIR ADAPTIVE FILTER FOR

RADAR APPLICATIONS”, is the bonafide work of LAVANYA. M [Reg. No. 14MAE008]

that carried out the research under my supervision. Certified further that, to the best of my

knowledge the work reported herein does not form part of any other project or dissertation on

the basis of which a degree or award was conferred on an earlier occasion on this or any other

candidate.

The candidate with university Register No.14MAE008 is examined by us in the project

viva-voce examination held on............................

INTERNAL EXAMINER EXTERNAL EXAMINER

SIGNATURE

Ms. A. KALAISELVI

PROJECT SUPERVISOR

Department of ECE

Kumaraguru College of Technology

Coimbatore-641 049

SIGNATURE

Dr. A. VASUKI

HEAD OF THE DEPARTMENT

Department of ECE

Kumaraguru College of Technology

Coimbatore-641 049

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ACKNOWLEDGEMENT

First, I would like to express my praise and gratitude to the Lord, who has

showered his grace and blessings enabling me to complete this project in an excellent

manner.

I express my sincere thanks to the management of Kumaraguru College of

Technology and Joint Correspondent Shri Shankar Vanavarayar for his kind

support and for providing necessary facilities to carry out the work.

I would like to express my sincere thanks to our beloved Principal

Dr.R.S.Kumar, Ph.D., Kumaraguru College of Technology, who encouraged me

with his valuable thoughts.

I would like to thank Dr.A.Vasuki, Ph.D., Head of the Department,

Electronics and Communication Engineering, for her kind support and for providing

necessary facilities to carry out the project work.

In particular, I wish to thank with everlasting gratitude to the project

coordinator Mrs.S.Umamaheswari, (Ph.D), Department of Electronics and

Communication Engineering, throughout the course of this project work.

I am greatly privileged to express my heart felt thanks to my project guide

Mrs.A.Kalaiselvi, ME (Ph.d), Assistant professor, Department of Electronics and

Communication Engineering, for her expert counselling and guidance to make this

project to a great deal of success and I wish to convey my deep sense of gratitude to

all teaching and non-teaching staff of ECE department for their help and co.operation.

Finally, I thank my parents and my family members for giving me the moral

support and abundant blessings in all of my activities and my dear friends who helped

me to endure my difficult times with their unfailing support and warm wishes.

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ABSTRACT

Adaptive FIR filter is used in RADAR to detect weak RADAR signal. The unwanted

signal is removed by using LMS algorithm. The Adaptive Filter Co-efficient is changed to

get desired signal. Implementation of FIR adaptive filter requires more hardware and power

consumption. The number of optimization techniques are proposed to reduce hardware,

power consumption and Speed. The optimization algorithm used in FIR Adaptive filter are

Vedic mathematics, CORDIC algorithms, KA algorithm e.t.c. Among these algorithm

CORDIC algorithm are widely used in RADAR application due to it’s simple architecture

and processor independent nature. MAC operation can done efficiently in CORDIC

structures compared to other traditional methods. Any complex operation like

Trigonometric operation sine, Cosine, Multiplication, division can done in less

computation time by using shifter and adder structures. CORDIC reduce the computation

time to 70% of its orginal value. Although speed is high in CORDIC structure the area

occupied by CORDIC structure is high. The speed and chip area of CORDIC structure is

improved by combining CORDIC with KA architecture. The larger computation is splitted

into smaller computation unit using KA algorithm and the computation operation is

performed without multiplier using CORDIC structures, hence overall speed and chip area

are improved.

TABLE OF CONTENTS

CHAPTER NO TITLE PAGE

NO

ABSTRACT iv

LIST OF TABLES vii

LIST OF FIGURES viii

LIST OF ABBREVIATION ix

1 INTRODUCTION 1

1.1 Adaptive Filter 1

1.2 FIR Filter 2

1.3 Existing Methods for Adaptive filter 4

2 LITERATURE REVIEW 9

3 METHDOLOGY 11

3.1 CORDIC Algorithm 11

3.2 Overview of CORDIC 12

3.2.1 Advantage 13

3.2.2 Disadvantage 13

3.3 Computation in CORDIC 14

3.3.1 Rotation Scaling 15

3.3.2 Scaling 15

3.3.3 Rotation 16

3.4 Types of CORDIC structures 16

3.4.1 Sequential CORDIC structures 16

3.4.2 Parallel or Cascading CORDIC structures 17

3.4.3 Pipelined CORDIC structures 17

3.5 KA Architecture 18

3.5.1 KA 2-way Architecture 18


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4 IMPLEMENTATION OF KA AND CORDIC

STRUCTURES

22

4.1 CORDIC Multiplier 22

4.2 FIR Filter 22

4.3 FIR Adaptive Filter 23

4.4 KA Equation 23

4.4.1 KA 2-way Algorithm 24

4.4.2 KA 3-way Algorithm 24

5 SIMULATION RESULT 26

5.1 CORDIC incorporated KA(2-way) FIR

Adaptive filter

26

5.2 CORDIC incorporated KA(3-way) FIR

Adaptive filter

32

5.3 RTL schematics 37

5.4 Synthesis Report 39

6 CONCLUSION 44

REFERENCE 45

LIST OF PUBLICATIONS 47

vi

vii

LIST OF TABLES

TABLE NO TABLE NAME Page No

5.1.1 Comparision of 12-bit Adaptive Filter 27

5.1.2 Comparision of 16-bit Adaptive Filter 29

5.1.3 Comparision For Higher Bits 32

5.2.1 Comparision for Adaptive FIR Filter 34

5.2.2 Comparision of Higher order Bits 36

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LIST OF FIGURES

Figure No Figure Name Page no

1.1.1 Adaptive Filter 1

1.2.1 Direct Form of FIR filter 3

1.2.2 Transposed form of FIR filter 3

3.1.1 CORDIC Algorithm 9

3.2.1 Block Diagram for CORDIC Processor 11



4.4.1 Flowchart for KA 2-way algorithm 24

4.4.2 Flowchart for KA 3-way algorithm 25

5.1.1 KA(2-way) and CORDIC adaptive FIR filter-12 bit 26

5.1.2 Comparison of CORDIC FIR Adaptive filter and CORDIC

incorporated KA(2-way ) FIR Adaptive filter-12 bit

27

5.1.3 KA (2-way) and CORDIC adaptive FIR filter-16 bit 28

5.1.4 Comparison of CORDIC FIR Adaptive filter and CORDIC

incorporated KA(2-way ) FIR Adaptive filter-16 bit

29




5.2.2 Comparision of Adaptive filter 34


5.4.1 RTL schematics of CORDIC and KA(2-way) FIR adaptive

filter

37

5.4.2 RTL schematics of CORDIC and KA(3-way) FIR adaptive

filter

38

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LIST OF ABBREVATIONS

ABBREVIATIONS NOMENCLATURE

CORDIC COordinate Rotation Digital Computer

FIR Finite Impulse Response

KA Karatsuba Algorithm

LMS Least Mean Square

LUT Look Up Table

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CHAPTER 1

INTRODUCTION

1.1 ADAPTIVE FILTER

An adaptive filter is a computational device that attempts to model the

relationship between two signals in real time in an iterative manner. An adaptive filter

is a system with a linear filter that has a transfer function controlled by variable

parameters and a means to adjust those parameters according to an optimization

algorithm. Adaptive filter are often realized either as a set of program instruction

running on an arithmetic processing devices such as microprocessor or DSP chip, or as

set of logic operation implemented in field programmable array(FPGA). LMS and RLS

are two types of adaptive algorithm.

x(n)

Y(n)

d(n)

Figure 1.1.1 Adaptive Algorithm

X(n) is an input signal that fed into a device called an adaptive filter, that

compute output signal y(n) at time n. the error signal is computed as difference between

desired signal d(n) and y(n).

E(n) =d(n)-y(n) (1)

W(n+1)=w(n)+µe(n)x(n) (2)

Delay Delay Delay

CORDIC

and KA

CORDIC

and KA CORDIC

and KA CORDIC

and KA

LMS

ALGORITHM

2

1.2 FIR FILTER

"FIR" means "Finite Impulse Response". If we put in an impulse, that is, a

single "1" sample followed by many "0" samples, zeroes will come out after the "1"

sample has made its way through the delay line of the filter.

In the common case, the impulse response is finite because there is no feedback

in the FIR. A lack of feedback guarantees that the impulse response will be finite.

Therefore, the term "finite impulse response" is nearly synonymous with "no feedback".

However, if feedback is employed yet the impulse response is finite, the filter still is a

FIR. An example is the moving average filter, in which the nth prior sample is

subtracted (fed back) each time a new sample comes in. This filter has a finite impulse

response even though it uses feedback, after N samples of an impulse, the output will

always be zero.

The difference function of FIR filter that defines how the input signal is related

to the output signal is: y[n] = x[n]b[0] + x[n-1]b[1] + x[n-2]b[2] + …… x[n-m-1]b[m-

1] where b[i] are coefficients of the filter, x[n] is an input signal, y[n] is an output

signal and ‘m’ is the order of the filter. The transfer function of a FIR filter is:

H(Z)=∑𝑏(𝑛). 𝑧−𝑛 (3)

The above equation is the filter’s equation in z domain where b[n] represents the

filter co-efficient also called as the filter response. The output of a filter to an input

response of x[n] is determined by the convolution function,

Y(n)=h(n)*x(n) (4)

The Lth-order LTI FIR filter is graphically interpreted in Fig 1.2.1. It can be seen

to consist of a collection of a “tapped delay line,” adders and multipliers. One of the

operands presented to each multiplier is an FIR coefficient, often referred to as a “tap

weight” for obvious reasons. Historically, the FIR filter is also known by the name

“transversal filter,” suggesting its “tapped delay line” structure.

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1.2.1 DIRECT FORM OF FIR FILTER

Figure 1.2.1 Direct form of FIR filter

FIR Filter with transposed structure

X(n)

Figure 1.2.2 Transposed form of fir filter

A variation of the direct FIR model is called the transposed FIR filter. It can be

constructed from the FIR filter in Figure1.2.1 by Exchanging the input and output ,

Inverting the direction of signal flow, Substituting an adder by a fork and vice versa

A transposed FIR filter is shown in Fig.1.2 2 and is general and the preferred

implementation of an FIR filter. The benefit of this filter is that we do not need an extra

A0

A1 Al `A2

A0 A1 A2 Al

Delay

DELAY

Delay

ay

DELAY

4

shift register for x[n], and there is no need for an extra pipeline stage for the adder (tree)

of the products to achieve high throughput.

1.3. EXISTING METHODS FOR ADAPTIVE FILTER

1.3.1. CORDIC

The current trend back toward hardware intensive signal processing has revealed

a relative lack of understanding of hardware signal processing architectures. Many

hardware efficient algorithms exist, but these are generally not well known due to the

dominance of software systems over the past quarter century. Among these algorithms

is a set of shift-add algorithm, collectively known as CORDIC, for computing a wide

range of functions including multiplication, division, trigonometric, hyperbolic, linear,

exponential and logarithmic functions. The commonly used software solutions for the

digital implementation of these functions are table lookup method and polynomial

expansions, requiring number of multiplications and additions/subtractions.

In 1959, Volder proposed a special purpose digital computing unit known as

COordinate Rotation DIgital Computer (CORDIC), while building a real time

navigational computer for use in an aircraft. This algorithm was initially developed for

trigonometric functions which were expressed in terms of basic plane rotations.

The hardware realization of the algorithm equations require multiplications,

additions/subtractions and accessing the table stored in memory for trigonometric

coefficients. The CORDIC algorithm computes 2D rotation using iterative equations

employing shift and add operations. The versatility of CORDIC was enhanced by

developing algorithms on the same basis for conversion between binary to Binary

Coded Decimal (BCD) number representation by Daggett in 1959.It’s an unified

algorithm to compute rotation in circular, linear and hyperbolic coordinate systems

using the same CORDIC algorithm, embedding coordinate systems as a parameter.

During the last 50 years of the CORDIC algorithm a wide variety of applications

has emerged. The CORDIC algorithm has received increased attention after an unified

approach was proposed for its implementation. Thereafter, CORDIC based computing

has been the choice for scientific calculator applications such as, HP-2152A co-

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processor, HP-9100 desktop calculator, HP-35 calculator are a few such devices based

on the CORDIC algorithm. The CORDIC technique can be used in many applications,

such as single chip CORDIC processor for DSP applications ear transformations, digital

filters, and matrix based signal processing algorithms. More recently, the advances in

the VLSI technology and the advent of EDA tools have extended the application of

CORDIC algorithm to the field of biomedical signal processing, neural networks,

software defined radio and MIMO systems to mention a few.

1.3.2 KA ALGORITHM

KA algorithm is known as Karatsuba Algorithm. It’s a fast multiplication

algorithm based on divide and Conquer Method. It was discovered by Anatoly

Karatsuba in 1960. It reduces the multiplication of two n-digit number to at most single

–digit multiplication in general. It’s therefore faster than classical algorithm which

reduces n2 single digit products. The took-cook algorithm is a fastest generalization of

Karatsuba method. It’s an efficient digital serial multiplication. The multiplier operand

is divided into K-way to reduce the complexity from O(n2 )

The overall performance is improved for higher order of K at the cost of

complexity. Recent Days KA algorithm is more popular for it’s high speed. Two-way

algorithm can reduce the speed to O(n1.47 ) .

In order to solve the problems of Successive Multiplication in some applications

E.g multiplicative inversion, exponentiation and point multiplication, three operand

multiplication a recursive KA are used. The basic step of Karatsuba’s algorithm is a

formula that allows one to compute the products of two large numbers and using three

multiplications of smaller numbers, each with about half as many digits.

The basic steps of Karatsuba’s algorithm is a formula that allows one to compute

the product of two large numbers and using three multiplications of smaller number

each with about half as many digit as x or y ,plus some additions and digit shifts.

Let x and y be represented as n-digit strings in some base B. For any positive

integer m less than n, one can write the two given number as

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01 xBxx m (5)

01 yByy m (6)

Where x0 and y0 are less than Bm

The product is

01

2

1

2

2 ZBZBZBZxy mmm (7)

Where

112 yxZ (8)

10011 yxyxZ (9)

000 yxZ (10)

Karatsuba's basic step works for any base B and any m, but the recursive

algorithm is most efficient when m is equal to n/2, rounded up. In particular, if n is 2k,

for some integer k and the recursion stops only when n is 1, then the number of single-

digit multiplications is 3k, which is nc where c = log23.

The additions, subtractions and digit shifts (multiplications by powers of B) in

Karatsuba’s basic step take time proportional to n, their cost becomes negligible as n

increases. More precisely, if t (n) denotes the total number of elementary operations that

the algorithm performs when multiplying two n-digit numbers, then

dcnnTnT ])2/([3)(

for some constants c and d.

)()(3log2nonT

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It follows that, for sufficiently large n, Karatsuba's algorithm will perform fewer

shifts and single-digit additions than longhand multiplication, even though it is basic

step uses more additions and shifts than the straightforward formula. For small values

of n, however the extra shift and add operations may make it run slower than the

longhand method.

It can done for any bases. By using binary base we can do calculation for any

digit by a single program. We can apply recursive algorithm to break into smaller parts

or we can use K-way algorithm. In KA 2-way the multiplier operand is divided into two

equal part and for KA 3-way the multiplier operand is divided into three equal part and

their corresponding product is obtained by KA equation. It is more efficient and suitable

for recursive algorithm.

1.3.4 VEDIC MATHEMATICS

It’s used for long multiplications. For any pair of long numbers requires many

intermediate stages and requires register to record the results of each of the intermediate

stages and sum of intermediate value produces the final answer. VEDIC mathematics

provides short –cuts to avoid lots of intermediate stages.

The Vedic math’s (Vertically and Crosswise), allows you to multiply any pair of

single digit numbers without using anything higher than the 5x multiplication table.

The steps involved in calculating product are

1) Write the two single digit numbers one above the other.

2) Subtract each number from 10 and place the result to the right of the original

number.

3) Multiply the two numbers on the right (the answers to the subtractions in the previous

step) and place the answer underneath them on the answer line (this is the first part of

the answer). If the answer to the multiplication is 10 or more, just place the right-most

digit on the answer line and remember to carry the other digit to the next step.

8

4) Select one of the original numbers and subtract the number diagonally opposite it. If

there was no carry from the previous step just place the result on the answer line below

the original numbers, if there was a carry add this to the result before you place it on

the answer line.

1.3.5 LOOKUP TABLE METHOD

The size of Look up Table depend on the amount of data stored. Accuracy is less

in small look up Table and memory size will be more for the large look up table. So,

we have to select proper size for look up table and it occupies more memory. In the

recent past, a number of look-up table-based algorithms have been proposed for the

software implementation of GF(2n) multiplication. Look-up table-based algorithms can

provide speed advantages, but they either require a large memory space or do not fully

utilize the resources of the processor on which the software is executed. In this work,

an algorithm for GF(2n) multiplication is proposed which can alleviate this problem. In

each iteration of the proposed algorithm, a group of bits of one of the input operands

are examined and two look-up tables are accessed. The group size determines the table

sizes, but does not affect the utilization of the processor resources. It can be used for

both software and hardware realizations and is particularly suitable for implementations

in memory constrained environment, such as smart cards and embedded cryptosystems

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CHAPTER 2

LITERATURE REVIEW

Efficient Digital-serial based KA based multiplier over binary Extensions field

using block recombination approach [2]

This paper is to design k-way BRKA (block recombination KA) Digital-serial

multiplication by using sub quadratic space complexity architecture. It provides

necessary trade-off between space and time complexity. It have Fast computation by

using polynomial form. K-way can implement in 2-way and k-way. The 2-way BRKA

approaches require less area and 8-way BRKA approaches produces result with less

chip area and less computation time. The speed of the system is high

Implementation of Adaptive FIR Filter for pulse Doppler Radar [3]

This paper is to implement Bank of filter which is designed for the required

bandwidth of Doppler shift to detect target signal and all filter are designed such a way

that clutter are cancelled each other Pipelined CORDIC unit reduce the complexity of

FIR filter and Simple architecture. But power consumption is high. The number of

micro rotation is optimized to get reduced chip area. For better adaptation and

performance of Adaptive filters and to minimize quantization error, the number of

iterations is also optimized.

Karatsuba implementation of FIR filters [4]

This paper is to implement Fir Filter using Karatsuba formula to speed up the

multiplication by splitting operands into two parts and product is calculated based on

the Karatsuba equation. Hardware complexities is reduced and speed in increased. Extra

arithmetic operations are need for padding.

Implementation of Adaptive Filter Based on LMS Algorithm [5]

This paper is to implement LMS adaptive equalizer using VHDL. It reduce the

effect of distortion introduced in the channel and cable of recover of original signal as

best as possible. Hardware complexity, on-linear effects are reduced by using adaptive

10

algorithm. LMS algorithm is implemented with pipelined architecture to get higher data

rates with less clock speed and less power consumption.Channel distortion is reduced

A Modular pipelined implementation of a delayed LMS transversal adaptive filter

[6]

This paper investigate efficient realization of a delayed least mean square

(DLMS) transversal adaptive filter. A time-shifted version of DLMS algorithm is

derived. The restructured algorithm, due to its order recursive nature, is well suited to

parallel implementation. In addition, a pipelined systolic-type architecture which

implements the algorithm is also presented. The performance of the pipelined system is

analysed and equation for speedup is derived.

The application and simulation of Adaptive filter in Noise cancelling [7]

In this paper adaptive filter is designed for noise cancellation application, the

statistical characteristics of signal and noises are usually unknown or can’t have been

learned so that we hardly design fix coefficient digital filter. In allusion to this problem,

the theory of the adaptive filter and adaptive noise cancellation are researched deeply

in the thesis. Noise cancelling is compared for LMS and RLS algorithm.

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CHAPTER 3

METHDOLOGY

3.1 THE CORDIC ALGORITHM

Figure 3.1.1 CORDIC algorithm

Fig 3.1.1 shows the graphical representation of CORDIC algorithm. The basic

concept of the CORDIC computation is to decompose the desired rotation angle into

the weighted sum of a set of predefined elementary rotation angles such that the rotation

through each of them can be accomplished with simple shift-and-add operations.

In the above figure we have considered an initial vector P1(X, Y), which is

rotated by angle Φ to get the final vector P2 (X’, Y’). Rotating a vector in a Cartesian

plane by the angle Φ (anti clockwise) can be arranged such that

x'=xcosΦ–ysinΦ (11)

y'=ycosΦ+xsinΦ (12)

The above equations are further reduced to:-

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x'=cosΦ*x-ytanΦ (13)

y'=cosΦ*y+xtanΦ (14)

If the rotation angles are restricted such that tan (Φ) = ± 2-i the multiplication by

the tangent term is reduced to a simple shift operation. Arbitrary angles of rotation are

obtainable by performing a series of successively smaller elementary rotations. Those

angular values are supplied by a small lookup table (one entry per iteration) or are

hardwired, depending on the implementation type. However, the required micro-

rotations are not perfect rotations, they increase the length of the vector(pseudo-

rotation) and in order to maintain a constant vector length(true rotation), the obtained

results have to be scaled by a scaling factor K. Removing the scaling constant from the

iterative equations yields a shift-add algorithm for vector rotation.

The CORDIC rotator is normally operated in one of two modes, the vector

rotation mode and the angle accumulation mode. In the rotation mode, a vector (x, y) is

rotated by a given angle Φ. The objective is to compute the final co-ordinate. In

accumulation mode the desired angle Φ is not given. The objective is to rotate the given

initial vector back to x-axis, so that the angle between them can be acquired. In our

thesis we shall carry out the design of the CORDIC algorithm based on the rotation

mode. To generate cosine and sine values of given angle Φ, we substitute the values (1,

0) in place of the initial co-ordinates and get the required results from the final co-

ordinates.

3.2 OVERVIEW OF CORDIC

CORDIC or Coordinate Rotation Digital Computer is a simple and hardware-

efficient algorithm for the implementation of various elementary, especially

trigonometric, functions. Instead of using Calculus based methods such as polynomial

or rational functional approximation, it uses simple shift, add, subtract and table look-

up operations to achieve this objective. The CORDIC algorithm was first proposed by

Jack.E.Volder in 1959. It is usually implemented in either Rotation mode or Vectoring

mode. In either mode, the algorithm is rotation of an angle vector by a definite angle

but in variable directions. This fixed rotation in variable direction is implemented

13

through an iterative sequence of addition/subtraction followed by bit-shift operation.

The final result is obtained by appropriately scaling the result obtained after successive

iterations. Owing to its simplicity the CORDIC algorithm can be easily implemented

on a VLSI system. The block diagram of the CORDIC processor is shown below in Fig

3.2.1

Figure3.2.1 Block Diagram for CORDIC processor

3.2.1 ADVANTAGES

1) Hardware requirement and cost of CORDIC processor is less as only shift registers,

adders and look-up table (ROM) are required.

2) Number of gates required in hardware implementation, such as on an FPGA, is the

minimum as hardware complexity is greatly reduced compared to other processors such

as DSP multipliers. It is relatively simple in design. No multiplication and only

addition, subtraction and bit-shifting operation ensures simple VLSI implementation.

Delay involved during processing is comparable to that during the implementation of a

division or square-rooting operation.

3.2.2 DISADVANTAGES

Large number of iterations required for accurate output results in low speed and

thus time delay is high. Power consumption is high in some architecture types. In

regular CORDIC VLSI structure, ROM is used to store the pre-computed values of arc

tangents. However ROM based CORDIC processor design is not preferred because

ROM has slow speed (ROM access time) and consumes more power.

14

3.3 COMPUTATION IN CORDIC

According to the previously discussed rotation equations

x' = x cos Φ – y sin Φ (15)

y' = y cos Φ + x sin Φ (16)

Simplifying the equations further

x' = cos Φ * x - y tan Φ (17 )

y' = cos Φ * y + x tan Φ (18)

Now, to get the desired results from the above equations, the other requirements are

Adder, Subtractor and Multiplier.

To reduce the mathematical complexity, we drop the cosine term initially.

Now to eliminate the multiplication term we substitute:-

tan(φ) = ±2-i

where, i is the count of iterations.

Hence, Φ is a chosen set of specific angular values (in degrees), stored in the

algorithm itself, to satisfy the above relation.

Therefore, the final working equations are arranged a

x(i+1) = x(i) – y(i)2-i (19)

y(i+1) = y(i) + x(i)2-i (20)

By breaking the rotation angle φ into a series of small successive shrinking

angles, such that, tanφ(i) = ±2-i, hence the multiplication with the tangent term can be

replaced by a division by a power of two, which is efficiently done in digital computer

hardware using a bit shift.

The above working equations clearly reflect, that the CORDIC algorithm can be

implemented using only adder, subtractor , controlled bit-shift register.

15

Although there are requirement of other components, but the main computational

blocks are the adder, subtractor and the controlled bit-shift registers. The CORDIC

algorithm is basically implemented by two steps.

3.3.1 ROTATION SCALING

The angular accumulator adds a third difference equation to the CORDIC

algorithm

z(i+1) = z(i) – d.tan-1(2-i) (21)

where, d decides the direction of rotation, clockwise or anti-clockwise.

3.3.2 SCALING

As we drop the COSINE term initially from the iterative process to make

computation easy, scaling operation is required to move the end-point of the final vector

back to the desired trajectory.

We know: cos(φ) = 1/(1 + tan2 φ)-1/2

Substituting: tanφ(i) = +2-I, we get:

cos(φ) = 1/(1 + 2-2i)-1/2 = ki

where, Ki is a constant known as scaling factor.

The scaling factor being a constant, is precomputed according to the following

equation:-

K(n)=∏𝐾𝑖 = ∏ √1 + 2−2𝑖𝑛−1𝑖=0

the value is calculated as given below and stored for a fixed number of iterations ;

K= lim𝑛→∞

(𝑘(𝑛)𝑛)=0.607252935

The scaling factor is applied at the end of successive iterations by using simple

bit-shift and addition-subtraction operation to get the desired output.

Hence, the final equations are written as

16

Xi+1=Ki(xi-(yi*di∗ 2−2𝑖)) (22)

Yi+1=Ki(yi-(yi*di*2−2𝑖)) (23)

where, di represents the direction of rotation for each individual iteration i.

3.3.3 ROTATION

The initial vector is rotated by a given definite angle, which is achieved by a

sequence of iterations of micro-rotations of variable direction, choosing angles from the

above given table only, followed by required addition or subtraction. Now the direction

of each of these elementary rotations is represented by a decision vector and an

additional adder – subtractor comes into play which accumulates the elementary

rotation angles at each single iteration. These angular values are supplied one at a time

per iteration.

3.4 TYPES OF CORDIC STRUCTURES

CORDIC algorithm, for calculation of sine and cosine values, is of three types.

Each of the types has its own advantages and disadvantages. Depending upon the

requirement of the design, the best suitable architecture is chosen.

The three types are

1) Sequential or iterative

2) Parallel or cascaded

3) Pipelined

3.4.1 SEQUENTIALOR ITERATIVE CORDIC STRUCTURES:

In this type of CORDIC architecture, a single iteration process takes place in a

single clock cycle.

Advantages

The hardware complexity is least and it occupies the least area. It has maximum

number of clock cycles per iteration. Power consumption is least.

17

Disadvantages

Maximum number of clock cycles are required to calculate the output, thus

calculation time is large. Variable shifters do not map well on certain FPGAs due to

high fan-in.

3.4.2 PARALLEL OR CASCADED CORDIC STRTURES

In this type of architecture, all the iterations take place in a single clock cycle.

Advantages

It has considerable delay, but processing time is reduced as compared to the

iterative process. Shifters are of fixed size and so can be implemented in the wiring.

Constants can be hardwired instead of requiring storage space.

Disadvantages

The amount of hardware required is large and the area required is maximum.

Power consumption is highest among the three CORDIC architectures.

3.4.3 PIPELINED CORDIC STRUCTURES

It is comparatively the most efficient CORDIC architecture. In this method

multiple iterations take place in multiple clock cycles. It is implemented by inserting

registers within the different adder stage.

Advantages

FPGA implementation is easy, as registers are already available, thus requiring

no extra hardware. Number of iterations after which the system gives accurate result

can be modelled, considering clock frequency of the system. When operating at greater

clock period power consumption in later stages reduces due to lesser switching activity

in each clock period.

18

Disadvantages

Hardware complexity as well as area required is more than sequential

architecture. Power consumption is lower than parallel architecture but higher than

sequential structure

3.5 KA ARCHITECTURE

KA algorithm is a recursive algorithm based on divide and conquer method. It

divides larger operand into K small number and product is calculated K-way algorithm.

In this project CORDIC is combined with KA 3- way algorithm.

3.5.1 KA 2-WAY ARCHITECTURE

Let A and B be the two operands of the multiplier. It can be spitted into two equal

parts. A0B0 and A1B1 are given to CORDIC structures. A0 A1and B0B1 are added and

given to CORDIC structure. The output is calculated by using adder and zero padding.

2/

10

MXAAA (24)

2/

10

MXBBB (25)

C is the product of A and B. Then C can be calculated by using KA equation as

MM XKXKKKKC 1

2/

10010 )( (26)

Where,

M represents the number of bits

X represents the base

000 BAK , (27)

111 BAK , (28)

))(( 101001 BBAAK (29)

19

A B

A0 A1 B0 B1

C

Figure 3.5.1 KA 2- way Architecture

3.5.2 KA 3-WAY ARCHITECTURE

The given multiplier operand A and B are divide into three equal part. The

partial products are calculated by using CORDIC structure and the intermediate result

is calculated by using subtractor. The final product is obtained by using adder and zero

padding.

Let A and B be the two multiplication operand. The operand can expressed as

2

3/2

1

3/

0 AXAXAA Nn (30)

2

3/2

1

3/

0 BXBXBB Nn (31)

C is the product of A and B. The C can be calculated by three way equation.

3/4

43

3/2

2

3/

10

NNNN XCXCXCXCCC (32)

R0 R1

SHIFT REGISTER ADDER SHIFT REGISTER ADDER

SHIFT REGISTER ADDER SHIFT REGISTER

ADDER AND ZERO PADDING

20

Where

00 PC (33)

01011 PPPC (34)

210012 PPPPC (35)

)( 21123 PPPC (36)

24 PC (37)

Where 43210 ,,,, CCCCC

000 BAP (38)

111 BAP (39)

))(( 101001 BBAAP (40)

))(( 202002 BBAAP (41)

))(( 212112 BBAAP (42)

The inner multiplication is done by using CORDIC structures .So CORDIC

is incorporated in KA-3 way. The speed and chip area occupied by KA 3 way is less

than KA 2 way architecture. CORDIC is incorporated in KA 3 way to get high

performance.

KA 3-way produces higher performance with complex architecture.

21

B

A

B0 B1 B2

A0 A1 A2

C

Figure 3.5.2 KA 3-way Architecture

R0

R1

Shift

register

Shift

Register

ADDER ADDER ADDER ADDER ADDER ADDER

Shift

register

Shift

register

Shift

Register

Shift

register

Adder Adder Adder Adder Adder Adder

Subtractor Subtractor Subtractor

Adder and Zero Padding

22

CHAPTER -4

IMPLEMENTATION OF CORDIC AND KA STRUCTURES

The CORDIC algorithm is based on mainly three components: controlled shift

registers, adders and subtractors. We have designed the algorithm using these three

blocks and other components as required in VHDL. All the components used are

designed individually in VHDL and finally using the structural mode of styling,

interfacing among all the components is completed.

4.1. CORDIC MULTIPLIERS

Let X and Y are two operands and multiplication result is obtained as

Z= X* Y (43)

Where

Z is composed of shifted version of Y. The unknown value for Z is obtained by driving

X to zero. It’s processed one bit at a time.

If the ith bit of X is non-zero then y is right shifted by i bits and added to current

value of Z. Then ith bit is removed from X by subtracting 2i from X .For negative number

ith bit is removed by adding 2 power.

Every bit of X is verified non-zero value. The y is shifted for every non-zero

position of X and accumulated. The corresponding Bit position is made zero. The

process is repeated until X is having zero bit.

4.2 FIR FILTER

Fir filter is implemented using convolution operation. The reset signal is given

to initialize the circuit and output is produced for each output. The output is calculated

by convoluting FIR filter co-efficient with input signal

23

4.3 FIR ADAPTIVE FILTER

The input signal X1, X2, X3 from the input port is stored in input register. The

co-efficient are stored in the co-efficient register. The output signal is calculated by

convoluting input signal and filter co-efficient. The multiplier operation in MAC

operation is performed by KA and CORDIC structures.

The given multiplier operand is splitted into two equal parts for KA 2-way and

is splitted into three equal parts for KA 3-way. The splitted operands are stored in the

register and corresponding intermediate values are calculated by using CORDIC

structures. The product of the multiplier operand is calculated by intermediate values

LMS algorithm are used to update the filter co-efficient based on the error

generated by the system. The error is calculated by subtracting the desired signal with

output signal. The Filter co-efficient calculated from LMS algorithm are used for next

iteration.

The above process is repeated for few iterations to get the output signal equal

to the desired signal. The FIR adaptive filter is designed for CORDIC structures,

CORDIC incorporated KA(2-way) Structure and CORDIC incorporated KA(3-way)

Structures.

4.4 KA EQUATIONS

KA algorithm is known for its high performances. It’s a recursive algorithm. An

algorithm is based on divide and conquer method. It divides larger operand into two

small number and product is calculated by three multiplication of small number. The

multiplication in KA algorithm can be done with a CORDIC structure to increase the

speed. By incorporating CORDIC in KA structure the chip area will also be reduced.

The KA can work in any numbers of base - n. The operands can be divided into k-way.

24

4.4.1 KA 2-WAY ALGORITHM

Let A and B be the two operands of the multiplier. It‘s splited into two equal part

and stored in shift register. The intermediate values K01, K0 and K1 are calculated by

using CORDIC structures and the product is calculated by adding intermediate value

and Zero padding.

Figure 4.4.1 Flowchart for KA 2 -WAY ALGORITHM

4.4.2 KA 3WAY ALGORITHM

The multiplication operand is divided into three parts and values are stored in

register. The P0, P1, P2, P01, P12 and P02 are calculated by using CORDIC structures and

C0, C1, C2, C3 and C4 are calculated from the intermediate values. The product C is

calculated by adding intermediate value and Zero padding.

Splitting of Multiplier operand into

two equal parts

Calculation of K01, K0 and K1 using

CORDIC structure

Calculation of Product using adder

and zero padding

25

Figure 4.4.2 Flowchart for KA 3- WAY ALGORITHM

Splitting of Multiplier operand into

three equal parts

Calculation of P01, P0, P2, P02, P12, P1

using CORDIC structure

Calculation of product using adder

and Zero padding

Calculation of C0, C2, C1, C3, C4 by

using adder and subtractor

26

CHAPTER 5

SIMULATION RESULT

The entire module is coded using VHDL and simulated using Xilinx ISE 9.2 I

software and implemented in Spartan DSP family. The whole block of CORDIC and

KA FIR adaptive filter is simulated for 12bit, 16 bit, 32 bit, 24 bit and 48 bit. The

simulation results of CORDIC and KA FIR adaptive filter with 12 bit, 16 bit, 32 bit and

24 bit are indicated below.

5.1 SIMULATION RESULT FOR KA 2-WAY and CORDIC FIR

ADAPTIVE FILTER

The below result show the output of KA and CORDIC FIR Adaptive filter for

12-bit, 16-bit and 24-bit. X1, X2, X3 are the input signal and co-efficient are taken as 4,

3 and 2. The output signal is represented by Y1, Y2, Y3 which have the convolution

value of X 1, X2, X3 and filter co-efficient.

Figure 5.1.1 KA(2-way) and CORDIC ADAPTIVE FIR FILTER-12 BIT

27

The performance of CORDIC FIR adaptive filter and CORDIC incorporated KA

FIR adaptive filter are compared for 2-way. CORDIC incorporated FIR adaptive filter

produce High Speed and reduced chip area.

TABLE 5.1.1 Comparison of 12- bit Adaptive Filter

Figure 5.1.2 Comparison of CORDIC FIR adaptive filter and CORDIC

incorporated KA 2-way FIR adaptive filter

0

5

10

15

20

25

30

35

40

45

50

CORDIC FIR ADPFILTER

KA & Cordic FIRADP FILTER

28

20

50

29

13.2369.954

No of slices No of 4 i/p LUT Time delay

Parameter CORDIC Adaptive

FIR filter

(12 bit)

CORDIC Incorporated

KA Adaptive FIR filter

(12 bit)

Number of slices 28 20

Number of four input LUT 50 39

Number of bounded IOB 56 56

Time Delay(ns) 13.236 9.954

28


29

The speed of the KA incorporated CORDIC structure is more for 12 bit and 16

bit compared to CORDIC structure. LMS algorithm is implemented for adaptive filter

for few iterations and their performance is verified for standard and non-standard bits.

Table 5.1.2 Comparison of 16 bit Adaptive Filter

Figure 5.1.4 Comparison of CORDIC FIR Adaptive Filter and KA and CORDIC

FIR Adaptive Filter-16 bit

0

10

20

30

40

50

60

70

CORDIC ADP FIR FILTER

KA AND CORDIC ADP FIR FILTER

33

28

61

51

19.04

9.993

No of Slices No of LUT Delay

Parameter CORDIC FIR

Adaptive filter

(16 bit)

CORDIC Incorporated

KA FIR Adaptive filter

(16 bit)


Number of four input LUT 61 51

Number of Bounded IOB 74 74


30


31

Figure 5.1.6 KA (2-way) and CORDIC ADAPTIVE FIR FILTER-48 BIT

32

The CORDIC incorporated KA adaptive filter is implemented for 8- bit, 16-bit,

12-bit, 24-bit and 32 bit. The performances of higher order bits are compared.

Table 5.1.3 Comparison for Higher Bits

Parameter CORDIC incorporated

KA adaptive FIR filter

16-bit

CORDIC incorporated

KA adaptive FIR filter

24-bit


Number of four input

LUT

51 146

Number bounded of

IOB

74 110


5.2 SIMULATION RESULT FOR KA 3-WAY and CORDIC FIR

ADAPTIVE FILTER

The below result show the output of KA 3-way and CORDIC FIR Adaptive filter

for 24-bit and 48 bit. X1, X2, X3 are the input signal and co-efficient are taken as 4, 3

and 2. The output signal is represented by Y1, Y2, Y3 which have the convolution value

of X 1, X2 , X3 and filter co-efficient.

33

Figure 5.2.1 KA (3 –way) and CORDIC ADAPTIVE FIR FILTER -24BIT

34

The performance of CORDIC FIR adaptive filter and CORDIC incorporated KA

FIR adaptive filter are compared for 3-way. It’s observed that the area occupied by the

KA 3 –way is less compared to CORDIC structure and CORDIC incorporated KA 2-

way. Further the speed of the CORDIC incorporated KA(3-way) FIR adaptive filter is

high.

Table 5.2.1 Comparison for Adaptive FIR filter

Parameter CORDIC

Adp FIR

Filter

CORDIC

Incorporated

KA 2-way Adp

FIR Filter

CORDIC

Incorporated KA

3-way Adp FIR

Filter

Number of slices 80 76 53

Number of four input LUT 158 146 100

Number of bounded IOB 110 110 110

Time Delay(ns) 31.372 17.762 11.384

Figure 5.2.2 Comparison of Adaptive FIR filter

8076

53

158

146

100

31.372

17.762 11.3840

20

40

60

80

100

120

140

160

180

CORDIC FIR ADP FILTER CORDIC and KA 2-way FIR ADPFILTER

CORDIC and KA 3-way FIR ADPFILTER

Number of slices Number of four i/p LUT Time Delay (ns)

35

FIGURE 5.2.3 KA(3-way) and CORDIC ADAPTIVE FIR FILTER-48 BIT

36

The KA 3-way is implemented for higher order bits (48 bits) and their

performance are compared with (24- bits).The number of bounded IOB for 48 bits and

24 bits are appropriate.

Table 5.2.2 Comparison of Higher order Bits

Parameter KA and CORDIC FIR

Adp Filter for 24 bits

(3-way)

KA and CORDIC Adp

FIR filter for 48 bit(3 –

way)


Number of four I/P LUT 100 108

Number of bounded IOB 110 220

Time delay(ns) 11.384 14.357

37

5.4 RTL SCHEMATICS

The RTL schematics of KA incorporated CORDIC FIR adaptive filter is given

in figure 6.3.1.The input signal is represent by X1, X2, X3 and desired signal is

represented by d0, d1, d2.The output signal of CORDIC Incorporated KA FIR adaptive

filter is represented by Y1, Y2, Y3.

Fig 5.4.1 RTL schematics of CORDIC and KA(2-way)FIR adaptive filter

38

Fig 5.4.2 RTL schematics of CORDIC and KA(3-way) FIR adaptive filter

39

5.5 SYNTHESIS REPORT FOR 48-BIT CORDIC INCORPORATED

KA 3- WAY FIR ADAPTIVE FILTER

Release 9.2i - xst J.36

Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.

--> Parameter TMPDIR set to ./xst/projnav.tmp

CPU : 0.00 / 0.77 s | Elapsed : 0.00 / 0.00 s

--> Parameter xsthdpdir set to ./xst

CPU : 0.00 / 0.77 s | Elapsed : 0.00 / 0.00 s

--> Reading design: fir.prj

TABLE OF CONTENTS

1) Synthesis Options Summary

2) HDL Compilation

3) Design Hierarchy Analysis

4) HDL Analysis

5) HDL Synthesis

5.1) HDL Synthesis Report

6) Advanced HDL Synthesis

6.1) Advanced HDL Synthesis Report

7) Low Level Synthesis

8) Partition Report

9) Final Report

9.1) Device utilization summary

9.2) Partition Resource Summary

9.3) TIMING REPORT

=============================================================

============

Device utilization summary:

40

---------------------------

Selected Device : 3s500eft256-4

Number of Slices: 53 out of 4656 1%

Number of 4 input LUTs: 100 out of 9312 1%

Number of IOs: 182

Number of bonded IOBs: 110 out of 190 57%

IOB Flip Flops: 47

Number of GCLKs: 1 out of 24 4%

---------------------------

Partition Resource Summary:

Minimum period: No path found

Minimum input arrival time before clock: 11.384ns

Maximum output required time after clock: 4.283ns

Maximum combinational path delay: No path found

Timing Detail:

--------------

All values displayed in nanoseconds (ns)

=============================================================

==

Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'

Total number of paths / destination ports: 15929 / 47

-------------------------------------------------------------------------

Offset: 11.384ns (Levels of Logic = 13)

Source: x2<8> (PAD)

Destination: y3_15 (FF)

41

Destination Clock: clk rising

Data Path: x2<8> to y3_15

Gate Net

Cell:in->out fanout Delay Delay Logical Name (Net Name)

---------------------------------------- ------------

IBUF:I->O 9 1.218 0.995 x2_8_IBUF (Madd_cc2_add0001R1)

LUT1:I0->O 1 0.704 0.000 Madd_cc2_add0004_Madd_cy<0>_rt

(Madd_cc2_add0004_Madd_cy<0>_rt)

MUXCY:S->O 1 0.464 0.000 Madd_cc2_add0004_Madd_cy<0>

(Madd_cc2_add0004_Madd_cy<0>)

XORCY:CI->O 2 0.804 0.447 Madd_cc2_add0004_Madd_xor<1>

(Madd_output_2_addsub0005C5_mand)

MULT_AND:I1->LO 0 0.741 0.000 Madd_output_2_addsub0005C5_mand

(Madd_output_2_addsub0005C5_mand1)

MUXCY:DI->O 1 0.888 0.000

Madd_output_2_addsub0005_Madd_cy<10>

(Madd_output_2_addsub0005_Madd_cy<10>)

MUXCY:CI->O 1 0.059 0.000



MUXCY:CI->O 1 0.059 0.000



XORCY:CI->O 2 0.804 0.622

Madd_output_2_addsub0005_Madd_xor<13> (output_2_addsub0005<13>)

LUT3:I0->O 1 0.704 0.595 Madd_output_2_add0000C121

(Madd_output_2_add0000C12)

LUT3:I0->O 1 0.704 0.000 Madd_output_2_add0000_Madd_lut<14>

(N485)

MUXCY:S->O 1 0.464 0.000 Madd_output_2_add0000_Madd_cy<14>

(Madd_output_2_add0000_Madd_cy<14>)

XORCY:CI->O 1 0.804 0.000 Madd_output_2_add0000_Madd_xor<15>

(output_2_add0000<15>)

42

FDC:D 0.308 y3_15

----------------------------------------

Total 11.384ns (8.725ns logic, 2.659ns route)

(76.6% logic, 23.4% route)

=============================================================

============

Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'

Total number of paths / destination ports: 47 / 47

-------------------------------------------------------------------------

Offset: 4.283ns (Levels of Logic = 1)

Source: y1_14 (FF)

Destination: y1<14> (PAD)

Source Clock: clk rising

Data Path: y1_14 to y1<14>

Gate Net

Cell:in->out fanout Delay Delay Logical Name (Net Name)

---------------------------------------- ------------

FDC:C->Q 1 0.591 0.420 y1_14 (y1_14)

OBUF:I->O 3.272 y1_14_OBUF (y1<14>)

----------------------------------------

Total 4.283ns (3.863ns logic, 0.420ns route)

(90.2% logic, 9.8% route)

=============================================================

============

CPU : 18.66 / 19.55 s | Elapsed : 19.00 / 19.00 s

43

-->

Total memory usage is 193888 kilobytes

Number of errors : 0 ( 0 filtered)

Number of warnings : 89 ( 0 filtered)

Number of infos : 1 ( 0 filtered)

44

CHAPTER 7

CONCLUSION

With the advancement in VLSI design for Digital Signal Processing (DSP)

applications high-throughput, low-power and low-area are very important parameters.

In this project, the FIR ADAPTIVE filter is implemented for CORDIC and KA

Structure and performance is compared with CORDIC filter. The Adaptive filter is

designed in multiplier less environment by using CORDIC structures. The chip area

problem in CORDIC structure is fixed by combining CORDIC and KA algorithm.

Computation time of the system is reduced to 50% for CORDIC incorporated KA-2

way FIR adaptive filter and less than 50% for CORDIC incorporated KA 3-way FIR

adaptive filter. Implementation of higher bit CORDIC incorporated KA 2-way and also

KA 3 –way filter is performed to verify the number of bounded IOB. The graph and the

simulation result in chapter 5 and 6 shows performance CORDIC incorporated KA(2-

way) FIR adaptive filter and CORDIC incorporated KA(3-way) FIR adaptive filter

having clutters. By using reference signal, the desired output is obtained by LMS

algorithm. The proposed architecture can be implemented for RADAR signal also.

45

REFERENCES

1)Vanitha.A, Venkatesh Kumar N ,“Design Implement and Simulation of adaptive

FIR Filter using CORDIC structures for Radar applications”, International Journal

of Engineering Science and Innovative Technology (IJESIT), Volume 2, Issue 4,

July 2013

2)Chung-Hsin Liu, Chiou-Yng Lee and Pramod Kumar Meher,“Efficient Digital-

serial based KA based multiplier over binary Extensions field using block

recombination approach “ IEEE Transactions on circuits and systems –I:Regular

papers,Vol.62,No.8,August 2015

3)AmritakarMandal, Brajesh Kumar Kaushik, Brijesh Kumar,R.P.Agarwal

“Implementation of Adaptive FIR Filter for pulse Doppler Radar” proceedings of

the IEEE pp.978-1-4244-9190-2

4)Albicococo.p, Cardarllic.G.C,pontarelli,“Karatsuba implementation of FIR

filters”,International Journal on VLSI Signal Processing, 978-1-4673-5050-1

5) B.Swapna Reddy, V. Rama Krishna, “ Implementation of Adaptive Filter Based on

LMS Algorithm”,International Journal of Engineering Research & Technology

(IJERT) Vol. 2 Issue 10, October – 2013

6)N.Takagi.T.Asada and S.Yajiima,“Redundant CORDIC method with constant

scale factor for Sine and Cosine computation “,IEEE Trans. On computers, Vol-

C-40,No,.9,pp 989-995,1991

7) Meyer M.D and Agarwal p,“A modular pipelined implementation of a delayed

LMS traversal adaptive filter”, in IEEE international symposium on circuits and

system,May 1990,pp 1943-1946.

46

8) Ying He,HongHe,LiLi,YiWu,Hongyan pan,“The Applications and simulation of

Adaptive Filter in Noise Canceling,” in International Conference on computer

Science and Software Engineering,Vol:4 year:2008,PP.1-4

9)J.E.Volder,“The Birth of CORDIC”,International journal on VLSI signal

processing, Vol.30,pp 25-101,2000.

10)C-Y.Lee and P.K.Meher, “Efficient bit-parallel multipliers over finite

fieldsGF(2𝑚),”comput.Elect.Eng,vol.36 no.5,pp.955-968,2010

47

LIST OF PUBLICATIONS

Conferences

M.Lavanya and A.Kalaiselvi, “High speed Adaptive FIR filter for RADAR

Applications”, IEEE Conference on Wireless Communications, Signal

Processing and Networking(WISPNET) on 23 to 25 March 2016 at SSN College

of Engineering, Chennai. IEEE ISBN: 978-1-4673-9338-6/16 @2016

M.Lavanya and A.Kalaiselvi, “Novel FIR Adaptive Filter Structures for RADAR

Application”, IEEE Sponsered 3rd International Conference on Innovations in

Information, Embedded and Communications Systems (ICIIECS’16) on 17 th

and 18 th March,2016 at Karpagam College on Engineering, Coimbatore.

Journal

M.Lavanya and A.Kalaiselvi, “Novel FIR Adaptive Filter Structures for RADAR

Applications”, Pakistan Journal of Bio Technology(Annexure-II)

(communicated)

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