High Speed Electronics and Photonics Grouppeople.ee.ethz.ch/~fyuriy/oe/IfE-HSEP-2006...

Prof. Dr. H. JäckelElectronics Laboratory, IfE

Swiss Federal Institute of Technology [email protected] , http://www.ife.ee.ethz.ch, http://www.photonics.ethz.ch

http://www.first.ethz.ch28.11.2006

Electronics Laboratory, Electronics Laboratory, IfEIfEOverviewOverview

High Speed Electronics and High Speed Electronics and Photonics GroupPhotonics Group

09.12.2006227.07.2006 Prof. H. Jäckel / Electronics Laboratory / ETH Zürich [email protected]

Overview:High Speed Electronics and Photonics Group

Electronics Laboratory, ETH Zürich

Research Activities at the Electronics Laboratory

••••

↑ 200mV /div,2. 5ps /div →

↑ 200mV /div,2. 5ps /div →

InP Photonic Crystals for ultra dense Optical ICs

65-80nm CMOS for mm-wave RF and 40 Gb/s Electronics(ETH-IBM CASE Collaboration)

+200 Gb/s ICs with InP/GaAsSbHeterojunction Bipolar Transistors(in-house InP technology)

0.1-60 GHz TWA in 80nm CMOS

Hole depth 2420nm

1μm

2μm

Hole depth3530nm

Holes depth: →3.5um @ 250nm Ø

InP-based Tb/s Photonicssub-ps mode-locked diode laserssub-ps all-optical switches

09.12.200627.07.2006 3Prof. H. Jäckel / Electronics Laboratory / ETH Zürich [email protected]


High Speed Electronics:+200 Gb/s InP/GaAsSb DHBTs

40 Gb/s, 60 GHz CMOS

we,eff=0.7μm

wC=1.2 μm

E

B

C

Limits of Transistor Electronics: InP/GaAsSb DHBTs for 80 +200 Gb/s Electronics

1) Vertical and lateral device scaling into the 200nm range, 2) GaAsSb-type II baseQuantitative comparison to advanced 2-D nonstationary Hydrodynamic Device SimulatorPerformance benchmarking with simple demonstrators, eg. Ring-oscillators, Frequency Dividers

DRLM DRLM

56 GHz Frequency-Phase Locked Loop

VCO

Current DHBT Data: 200 nm thick Collector, we=0,7μm, le=4 - 8μmfT = 233 – 260 GHz @ jC=500 kA/cm2 / UCE=1.25Vfmax = 240 – 248 GHz @ jC=500 kA/cm2 / UCE=1.25VUCE0 >2.5Vβ >100

80 Gb/s MUX

27.07.2006 Prof. H. Jäckel / Electronics Laboratory / ETH Zürich [email protected] 5

6


1) 2-D hydrodynamic Type-I and II DHBT- and Circuit Simulations:

2) Scaling InP/GaAsSb technology toward submicron emitters we → 200nm:

Type I: InP/InGaAs/InP (graded)

we = 200nm ; wC=600nm ; dB=25nm ; dC=100nm →fT = 570 GHzfmax= 445 GHztg = 1.77 psB = 215 Gb/s (RO, MUX)

InP/GaAsSb DHBTs: towards 200-300 Gb/s ICs

25.01.2006

EmitterBase

Collector

200nm

Air-bridge Width ~0.6μm

Type II: InP/GaAsSb/InP

we = 200nm ; wC=600nm ;dB=15nm ; dC=100nm (50) →fT = 750 GHzfmax= 600 GHztg = 1.58 psB = 245 (300) Gb/s (RO, MUX)

gap S

S

EW

CW

Base

Scut

BW

Collector

Scut

S gap

BS

Sub−Collector

Base Mesa

CollectorMesa

SC

UndercutUndercut

Emitter

ES

Contact Metal

Emitter Mesa

we

dC

dB

wC

we=200nm

4x10 Gb/s Transceiver Array in 90nm CMOS for short distance MM-fiber links using AlGaAs VCSELs at 850nm (2.5mW/GHz)

Opt. Output @10Gb/s: Electrical output @10Gb/s:

50um multimode fiber/ PCB waveguide

In progress: 40 Gb/s receiver IC in 60 – 80nm CMOS for fiber-opics09.12.2006727.07.2006 Prof. H. Jäckel / Electronics Laboratory / ETH Zürich [email protected]


nm-scale CMOS for digital multi-10 Gb/s ICs

Half-Rate Phase

Detector

I-Q Generator

PhaseInter-

polator

Analog Filter

Reference

Input Clock Buffer

BypassCaps

Data Synchronization

Bypass Caps

Output Buffers

Bypass Caps

Digital Loopfilter

320 μm

Clock Buffer and

Frequency Divider by 32

• mm-Wave-applications from GHz to ~60 GHz for Mobile Com • 10 and 40 Gb/s ICs for Fiberoptics (Transmitter / Receivers) • Ultra Wide Band (UWB) RF-Communication for LANs, WANs, 3-10 GHz

40Gb/s 90nm CMOS TIA + LA, 26Gb/s Half-Rate CDR for Tb/s interconnects:

CASE Center for AdvancedSilicon Electronics

TIA

COMP Capacitors

COMP Capacitors

Bypass Capacitors

Bypass Capacitors

Bypass

Capacitors

Bypass

Capacitors

Output Buffer

Hig

h R

esis

tive

Subs

trat

e

6 LAs

Byp

ass C

apac

itors

140μm

90nm CMOS for mm-wave RF-ICsResearch Examples: 1-56 GHz CMOS 4-stage Travelling Wave Amplifier with 8 dB Gain:

InOut

• S21 > 8dB from close to DC-59GHz• S21 = 9.7dB ± 1.7dB from 10-59GHz• P-1dB,out = 12.5dBm @ 20GHz• Vdc= 2V• Idc= 66mA• Size: 0.85 x 0.35 mm2

CASE Center for AdvancedSilicon Electronics

26-42 GHz SOI CMOS Low Noise (4dB) Amplifier: Low power 4.5 GHz UWB-Wavelet Generator:



Photonic Integration for High Density, Multi-Functionality and

Ultrahigh Speed in the InP-Material System

09.12.2006

Trends in Photonic Integration: DensityProgress in Monolithic Photonic Integration:

Status and Projections

1125.01.2006 Prof. H. Jäckel / Electronics Laboratory / ETH Zürich [email protected]

• current integration level modest• typ. ~100 devices /cm-2

• device complexity high

• Nano-Photonics• Photonic Crystals(bandgap WG)

• Photon Wire Circuits(high contrast WG)

• Micro-Photonics(low contrast WG)

• (Hybrid Integration)


Future optical / electronic Confinement Concepts for λ-scaled photonic devices:- strong guiding (photon wires) and periodic dielectrics (1-3D Photonic Crystals)- dispersion engineering (slow light)- Quantum Dots, nm-scaled optoelectronic materials

courtesy M.Smit, COBRA-TU Eindhoven

opti

cal a

nd e

lect

roni

c co

nfin

emen

t

Q-dotQuantum-Photonic Devices

?λ- and nano scale

PhC-resonator


Ultrafast Tb/s Photonics: Beyond the Speed of Transistor Electronics I

Monolithically integrated 600fs mode-locked Diode Laser

09.12.2006

fs Mode-Locked Lasers Diodes (MLLD) @1550nm

Objectives for monolithic integration:• MLLD for Tb/s-OTDM-systems require sub-ps optical pulses e.g. τpulse ~500fs @ 1000Gb/s• size reduction, mechanical and temperature stability and high optical data rates

State-of-the-Art: pulse width tpulse~2ps at low frep limited by slow saturable absorbers ! ultra fast absorbers

Functional Integration: SOA + passive WG + Interfaces + Absorber/Modulator

1325.01.2006 Prof. H. Jäckel / Electronics Laboratory / ETH Zürich [email protected] 09.12.20061327.07.2006 Prof. H. Jäckel / Electronics Laboratory / ETH Zürich [email protected]

Mode-locking conditions:Esat, absorber < Esat, SOA

τsat, absorber < τsat, SOA

conventional MLLD (with slow SOA-type absorber)

Passive Waveguide

, SOA

Novel MLLD with UTC (Uni Travelling Carrier) absorber

avoiding slow hole drift ![ for photodiodes T.Ishibashi et al., 2001]

integration of a 3rd device section !

UTC Absorber

09.12.2006

Lateral MOCVD-Regrowth Process-FlowTechnology choice: MOCVD–lateral regrowth for freedom in layer composition

2 SiO2-masked additional regrowth steps for UTC and passive WG

Regrowth challenges: optimization between- SiO2-mask under-etch- MOCVD gas pressure- MOCVD growth temperature- total growth thickness

Solution: 2-step growth of WG-core and top-cladding optimized regrowth:


residualroughness

1.5μm

SOA WG

SiO2-mask

mask-underetch

passive WG UTC

layer etchSiO2-mask

mask overhang, μm

heig

ht o

f gro

wth

arte

fact

regrowthSiO2-mask

09.12.2006

UTC-MLLD Fabrication Sequence I


Basic Process Data:

• Number of masks: 16

• Number of growth: 5

• MOCVD pressure:30mb thick upper cladding 160mb thin lower waveguide

• Growth temperature: 6300C

• Total temperature cycle: 3h

SOA-QW-bandgap shift:growth biasing ~ 0.8nm/growth-hour

• Growth mask: SiO2

Fig.9a: SEM of butt-coupling UTC-WG Fig.9b: SEM of butt-coupling SOA-WG 1 = SOA growth 2 = UTC growth 4 = Waveguide cladding regrowth (undoped) 1a = Etch buffer 3 = Waveguide core (proposed, i.e. not grown on this sample) 1b = Etch stop regrowth 5 = P-Contact regrowth (doped)

300nm


UTC WG SOA

P-InGaAs

UTC P-contact

Bond pad

Waveguide

N-contact

SOA P-contact

PolyimideN-contact

A

A'

B B'

UTC WG SOA

P-metallisation Polyimide Bond pad

InGaAsP active layer InGaAs contact layer InGaAsP waveguide p-InP InGaAsP etch stop

2 3 1

45 5

Top View: Schematic Cross-Section:

SEM-Cross-Section of 3-Section MLLD:UTC WG SOA

Completed UTC-MLLD for frep= 40 GHz:

UTC WG SOA

09.12.2006

fs-Pulse measurement and Simulation of UTC-MLLD


Results: pulse width reduction ~4-5x to 600fs, small residual reflections are still present 09.12.20061627.07.2006 Prof. H. Jäckel / Electronics Laboratory / ETH Zürich [email protected]

600fs

time, ps

Aut

ocor

rela

tion

(a.u

.)2-photon absorptionautocorrelation:

3.2ps

Δf=0.6THz=MfrepM=LSOA/LUTC+1=14

Δf

0 50 100 150 200ps

multiple pulsestemporal separation1.6ps ≡ 2-LUTCr=140μm

time, ps

Distributed time-domain model of hybrid mode-locked , 2-section UTC-MLLD with internal reflections(R=5% , LSOA=930mm, LUTC=70mm):

UTC-MLLD: FFT of autocorr.: conventional MLLD:

09.12.2006

Densification of Optoelectronic Devices and OICs

to the Wavelength scale

InP-based Photonic Crystals


09.12.2006

Densification of optoelectronic InP-devices and OICs


mm - cm-sized devices for OICs based on low contrast waveguides are mainly interconnect-limited!bend

Nor

m. f

requ

ency

Norm. propagation constant

Photonic Bandgap

Ref

M.K.Chin et al., 19995μm ETH, D. Erni

air holes

dielectric

a~λ/2air-holes(lattice constant a~400nm, ∅~200n)

planar WG(InP/InGaAsP/InP)

Substrate(InP)

1μm

current, voltage

(High contrast PhC-membrane:) Low contrast PhC on substrate:

Solution: high contrast WG, Photon Wires or Photonic Crystals

reduce device size and interconnect area to a few 10λ2

increase photon density and nonlinearities dispersion engineering “slow light”new device functionsmanipulation of electronic transitions

Challenges:- nano-scale technology- competition against existing solutions- functional completeness- engineering CAD platforms- interconnection to fiber-world- active PhCs, contacting and current-injection

09.12.2006

2D- and 3D-Simulation of planar, substrate-type PhCs

1925.01.2006 Prof. H. Jäckel / Electronics Laboratory /ETH Zürich [email protected]

hole depth: 1.5um ETH, K. Rauscher hole depth: 2.5um

air

holes

substrate


airInP cladding (200nm) InGaAsP core (430nm) InP cladding (600nm) InP-Substrate

- PhC functions are not very intuitive need for fast engineering models- fast 2D-models not accurate enough (out-of-plane scattering neglected) - 3D-model are a reference but are too time consuming

phenomenological 2D-model with hole scattering loss represented by complex dielectric constant ε

Hole depth and out-of plane scattering:

hole etch depth ~3μm for passive, ~4μm for active PhCs for low contrast InP/InGaAsP/InP WGhigh losses for W1-WG α~500 dB/cm by 3D-FDTD

3D-(FDTD, SEMCADTM) vs. 2D-(MMP)-simulation:

the role of scattering losses

Example: optimized power splitter:

1 SiN/Ti-hard mask, EBL-resist 2 EBL+PEC 3 RIE of hardmask 4 ICP-RIE of GaInAsPdeposition PMMA patterning

3a 3b 4

Major Process Characteristics: - proximity corrected e-beam litho (30kV) - max. PMMA thickness <300nm- SiNx/Ti hard-mask, max. reliable etched thickness 400nm- SF6-, CHF3-based RIE etching of hard-mask

- optimized Ar/Cl2/N2 ICP cyclic etch chemistry for deep holes:Ar: physical etchingCl2: chemical etching N2: hole sidewall passivation, shape control

09.12.2006

InP/InGaAsP-Photonic Crystals: Process Flow I


Open Issues:

- hole wall roughness and scattering losses

- carrier lifetime reduction dueto surface damage

- hole etch tolerances

PMMA

3.5μm

1

3

4

09.12.2006

Photonic Crystal Standing WavemeterScanning Nearfield Optical Microscope (SNOM)-Measurement of standing wave pattern in W1 PhC WG

dispersion relation k(ω): attenuation α:

SNOM set-up:


Results:- SNOM-wavemeter: precise k(ω)-, α-measurements- loss ~900dB/cm are state-of-the-art,

but high compared to membranes (III-V, SOI)- 3D-FDTD-simulation: loss ~500dB/cm


Courtesy: Nano-Optics Group, ETH

09.12.2006

Interfacing Photonic Crystal: Power SplitterMix&Match-lithography (optical and e-beam litho) interface to fibers-PhCs

shallow ridge (width=1.5μm / height=300nm) deep trench (w=0.5μm / h=3μm) WG PhC WG

2225.01.2006 Prof. H. Jäckel / Electronics Laboratory / ETH Zürich [email protected] 2227.07.2006 Prof. H. Jäckel / Electronics Laboratory / ETH Zürich [email protected]

Optical EBLridge WG trench ridge WG

2μm

Optimized PhC-splitter:

10μm

Transmission measurement:

Out 1, 2

Alignment tolerance: optical - EBL

350nm alignment tolerance


Ultra fast Tb/s Photonics: Beyond the Speed of Transistor Electronics II

All Optical Switches for Tb/s fiberoptic data communication

500 fs Switching WindowAND-Function


Concepts of All Optical Switches

data out

Ps data in Pc1,2 delayed

control

k

E(k)

EV(k)

EC1(k)

EC2(k)

TPA IBT

ISBT

Valence band

Conduction band

PS

ISBTQW-stack

PC

PS

Gain-pumped ISBT-AOS

In-line all-optical gain switch: MZ-Interferometric SOA switch:fast ISBT absortpion recovery slow IBT absoption recovery

τrecovery~1/Bdata typ.< 1ps τrecovery>>1/Bdata

Interband and Intersubband transitions in QWs: Sub-ps Switching Performance:

+ fast, low saturation energy- complicated structure and control

drawback of ISBT:only active for TM-polarization !

PS

ISB TQW -stack

P C

PS

ISBT active WG

passive WG


Challenges of ultrathin Quantum Wells

Sb and In interdiffusion

Destroyed interfaces

Non square-like potential

Reduced separation energy between states

AlAs layer improves the interface quality

The InGaAs/AlAsSb system: intersubband transition energy decrease:

AlAs-Monolyer interfaces for stopping Sb- and In-interdiffusion:


Honeycomb TM-mode PhCs for ISBT-AOS

• Honeycomb PhCs provide an interesting compromise

• Honeycomb PhC require a large r/a-ratio

• Honeycomb lattice: (n=3.24, h=0.45a, r/a=02.4)

largest TM-PBG for manufacturable PhC structures

up to 12% bandgap (200nm bandwidth @ 1550nm)

Processing challenges for high r/a<0.22-ratio:

Material CollapseConnection r/a=0.22 of a =530nmr/a=0.24 of a =530nm

2D band diagram of honey comb PhCs (substate type):

n=3.24, r=0.24a


Honeycomb Photonic Crystal TM-mode waveguides

K 'Γ −

K 'Γ0

0.1

0.3

0.5

0.4

0.2

Wave vector kx

f

Requirements:- large TM-bandgap at 1550nm - small group velocity vgr for high nonlinearity - „acceptable“ a/r-ratio for reliable fabrication

Removing two rows of holes

• Type I: W1 PhC waveguide in direction and its 2D band diagramK 'Γ −

Γ K '0.1

0.2

0.3

0.4

0.5

Wave vector kx

f

• Type II: W2 PhC waveguide in direction and its 2D band diagram

Introducing one row of holes

FIRST-LAB: Example of Technology-Sequence of an InP/InGaAs-Heterojunction Bipolartransistor-ICFIRST-LAB: Example of Technology-Sequence of an InP/InGaAs-Heterojunction Bipolartransistor-IC

InP-Wafer 12 Mask-Prozess, 4-5 week processing in the clean-room

05.07.2002 23

Resistors Capacitors

CollectorDry-Etching

Basis / EmitterMetal Contacts

Epitaxy

Circuits and ICElektron-BeamLithography

Emitter wet etching

Optical Lithography

Wet Processing

Dry-Etching RIEMetal Evaporation

Collaborations:

Project funding: NSF NCCR Quantum Photonics-, ETH-TH-, ETH-INIT-Grants, ePIXnet EU-Grant:

09.12.2006

Thanks for your attention !


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