AllAll--Digital Quadrature Modem Digital Quadrature Modem for High Speed Wireless for High Speed Wireless

CommunicationsCommunications

Abhishek Mitra 19991003Abhishek Mitra 19991003IIIT AllahabadIIIT Allahabad

2727thth Jan 2003 to 22Jan 2003 to 22ndnd May 2003May 2003

Under guidance of

Mr. Vishwajit Mitra

HFCL R&D

ReferencesReferences

§§ A VLSI Architecture for a HighA VLSI Architecture for a High--Speed AllSpeed All--Digital Digital Quadrature Modulator and Demodulator for Digital Quadrature Modulator and Demodulator for Digital Radio Applications. ”Henry Radio Applications. ”Henry SamueliSamueli and Bennett and Bennett C. Wong”, IEEE Journal on Selected Areas in C. Wong”, IEEE Journal on Selected Areas in Communications, Vol8, No 8, October ‘90Communications, Vol8, No 8, October ‘90§§ A BPSK / QPSK Timing A BPSK / QPSK Timing –– Error Detector for Error Detector for

Sampled Receivers. “Floyd M Gardner”, IEEE Sampled Receivers. “Floyd M Gardner”, IEEE Transactions on Communications, Vol. COMTransactions on Communications, Vol. COM--34, 34, No 5, May ‘86 No 5, May ‘86 §§ A survey of CORDIC algorithms for FPGA based A survey of CORDIC algorithms for FPGA based

computers. “Ray computers. “Ray AndrakaAndraka”, FPGA 98, Monterey, ”, FPGA 98, Monterey, CA, USACA, USA

ModemModem

–– QPSK (Quadrature Phase Shift Keying)QPSK (Quadrature Phase Shift Keying)–– 10MHz Data rate10MHz Data rate–– IF at 10MHzIF at 10MHz–– UptoUpto 40MHz Data rate40MHz Data rate–– Reconfigurable Devices (FPGA)Reconfigurable Devices (FPGA)–– Digital FilteringDigital Filtering–– Digital Modulation and DemodulationDigital Modulation and Demodulation–– Applications: Point to Point W/Less Links and Satellite Applications: Point to Point W/Less Links and Satellite

Communications.Communications.

QPSK ModulationQPSK Modulation

Input (I ) Mixer (Q) Mixer Sum Sum (solved) 00

ctωsin−

ctωcos−

ctct ωω cossin

)135sin( °−ctω

01

ctωsin−

ctωcos ctct ωω cossin +

)135sin( °+ctω

10

ctωsin

ctωcos−

ctct ωω cossin − )45sin( °−ctω

11 ctωsin

ctωcos ctct ωω cossin + )45sin( °+ctω

Waveform Sample Tn Sample

Tn+1 Sample Tn+2

Sample Tn+3

Sine (Q) Cosine (I)

0 1

1 0

0 -1

-1 0

ModulatorModulator

§§ 32 bit RRC filtering32 bit RRC filtering§§ IF at 10MHzIF at 10MHz§§ Analog LPF with B/W 13MHzAnalog LPF with B/W 13MHz§§ 10bit precision digital output10bit precision digital output§§ Parallel multiplication (LUT based)Parallel multiplication (LUT based)§§ When I carrier is sampled ‘1’ or ‘When I carrier is sampled ‘1’ or ‘--1’, the Q carrier 1’, the Q carrier

is sampled ‘0’ which means at any sampling is sampled ‘0’ which means at any sampling instant we need to process only one of the carrier. instant we need to process only one of the carrier. §§ PRBS Generator used to generate Random PRBS Generator used to generate Random

SequenceSequence

ModulatorModulator k=0,1,2,3,4,5,6,7,8

Block Diagram (Modulator Section)

h4k

h4k + 1

-h4k +2

-h4k +3

Idata

Qdata

Clk 4X

4 – To – 1 Multiplexer

D / A Converter

IF Output

Gain Block

PtoSConverter

Digital FilterDigital Filter§§ Root Raised Cosine (Low Pass)Root Raised Cosine (Low Pass)§§ Avoids ISIAvoids ISI§§ Digital Filter Coefficients:Digital Filter Coefficients:

7 4 7 4 --7 7 --16 16 --12 9 33 38 8 12 9 33 38 8 --48 48 --93 93 --77 27 203 390 511 77 27 203 390 511 511 390 203 27 511 390 203 27 --77 77 --94 94 --48 8 38 33 9 48 8 38 33 9 --12 12 --16 16 --7 4 77 4 7§§ Transmit filter has to meet the following specifications:Transmit filter has to meet the following specifications:§§ Operating FrequencyOperating Frequency : : 10 MHz.10 MHz.§§ No. of TapsNo. of Taps :: 3232§§ Roll of factor Roll of factor ?? : : 0.30.3§§ Pass band BandwidthPass band Bandwidth :: 13 MHz13 MHz

Impulse Response Frequency Response

TxTx Sub FilterSub Filterh0 h3 h7 h11 h15 h19 h23 h27

Dn+7 dn+6 dn+5 dn+4 dn+3 dn+2 dn+1 dn

H0*Dn+7 h3*dn+6 h7*dn+5 h11*dn+4 h15*dn+3 h19*dn+2 h23*dn+1 h27*dn

To normalizer and DAC

10

-1,1

13

Transmit SpectrumTransmit Spectrum

Simulated, 10 MHz Actual, 10MHz

DemodulatorDemodulator

§§ 10MHz IF, sampling rate = 40MHz10MHz IF, sampling rate = 40MHz§§ 32 bit RRC Filter32 bit RRC Filter§§ 16bit I,Q rail 16bit I,Q rail subfilterssubfilters, clocked at 20MHz, clocked at 20MHz§§ Automatic Gain ControlAutomatic Gain Control§§ Demodulation = DeDemodulation = De--Multiplexing and Inversion Multiplexing and Inversion

ControlControl§§ Timing RecoveryTiming Recovery§§ Carrier RecoverCarrier Recover§§ CMA EqualizerCMA Equalizer

Demodulator Block DiagramDemodulator Block Diagram

h=0,1,2…,15 Receiver Block Diagram

ADC

VCXO

1 – To -2 De- Multiplexor

RRC h2k

RRC h2k

Gardner Algo

Analog Filter

Clock Recovery

AGC & Carrier Recovery

CMA Adaptive Equalizer

Slicer

Error Calculation

Error

Digital IF at Baud Rate

Fs=4*Baud

I Rail

Q Rail

Rx Sub Filter (pipelined)Rx Sub Filter (pipelined)H0 h2 h4 h6 h8 h10 h12 h14 h16 h18 h20 h22 h24 h26 h28 h30

D15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0

10

10

D15*h0 d14*h2 d13*h4 d12*h6 d11*h8 d10*h10 d9*h12 d8*h14 d7*h16 d6*h18 d5*h20 d4*h22 d3*h24 d2*h26 d1*h28 d0*h30

20

To normalizer and further subsystems10

AmbiguitiesAmbiguities

§§ Clock AmbiguityClock Ambiguity§§ Carrier AmbiguityCarrier Ambiguity§§ Polarity AmbiguityPolarity Ambiguity§§ I / Q Channel AmbiguityI / Q Channel Ambiguity§§ ResolvingResolving

Clock RecoveryClock RecoveryCarrier Recovery / Carrier Recovery / DerotationDerotationDifferential EncodingDifferential EncodingInternal Channel SelectorInternal Channel Selector

Clock RecoveryClock Recovery

§§ Garderner’sGarderner’s Zero Crossing DetectorZero Crossing Detector§§ e(ne(n) = I(n) = I(n--1/2)[I(n) 1/2)[I(n) –– I(nI(n--1)] + Q(n1)] + Q(n--1/2) [1/2) [Q(nQ(n) ) –– Q(nQ(n--1)]1)]

§§ Error = Sum of both I and Q channels Error = Sum of both I and Q channels §§ 10 bit digital error output converted to 10 bit digital error output converted to

analoganalog§§ Error signal is used to control the VCXOError signal is used to control the VCXO

Carrier RecoveryCarrier Recovery

§§ Carrier ambiguities result in a rotating constellationCarrier ambiguities result in a rotating constellation§§ DeDe--rotation is neededrotation is needed§§ Using CORDIC algorithms (iterative algorithm for Using CORDIC algorithms (iterative algorithm for

coordinate rotation)coordinate rotation)§ If the rotation angle is limited to tan( 2-i) then

multiplication by tangent term becomes a shift operation.

§ The final equation results in

]tan[cos']tan[cos'

φφφφ

XYYYXX

+=−=

2..[1 diYiXiKiXi −=+ -i]

2..[1 diXiYiKiYi +=+ -i]

Carrier RecoveryCarrier Recovery

Before After

CMA EqualizerCMA Equalizer

§§ Iterative Algorithm, Step size = 2Iterative Algorithm, Step size = 2§§ The algorithm fits the constellation points to The algorithm fits the constellation points to

a circle of constant magnitude.a circle of constant magnitude.§§ Dependent on the accuracy of the AGCDependent on the accuracy of the AGC§§ Decision directed algorithmDecision directed algorithm§§ C=C=C+cmaerrorC+cmaerror§§ CmaCma error = (Radius CMA)^2 error = (Radius CMA)^2 –– (Radius C)^2(Radius C)^2

FPGAFPGA

§§ Reprogrammable Digital HardwareReprogrammable Digital Hardware§§ Extremely Customizable and parallel executionExtremely Customizable and parallel execution§§ Very fast speed (150 MHz)Very fast speed (150 MHz)§§ Very low design turnaround timeVery low design turnaround time§§ Simulation / Synthesis ToolsSimulation / Synthesis Tools§§ Testing, Debugging, and ImplementationTesting, Debugging, and Implementation§§ XC 2S 200 (200 K system gates)XC 2S 200 (200 K system gates)§§ XC 2V 1500 (1.5 M system gates)XC 2V 1500 (1.5 M system gates)

ImplementationImplementation

§§ Quadrature Modulator (Tested)Quadrature Modulator (Tested)§§ Quadrature Demodulator (Tested)Quadrature Demodulator (Tested)§§ PRBS generator (24 bit Maximal Length)PRBS generator (24 bit Maximal Length)§§ Digital FiltersDigital Filters

Parallel Execution (Parallel Execution (TxTx) (Tested)) (Tested)Pipelined Execution (Rx) (Tested)Pipelined Execution (Rx) (Tested)§§ Timing Recovery (Tested)Timing Recovery (Tested)§§ Carrier Recovery (Under Test)Carrier Recovery (Under Test)§§ CMA Equalizer (Under Test)CMA Equalizer (Under Test)

Test BenchTest Bench

§§ Spectrum AnalyzerSpectrum Analyzer§§ OscilloscopeOscilloscope§§ Personal Computer Personal Computer §§ Xilinx ISEXilinx ISE§§ ModelSimModelSim SimulatorSimulator§§ MATLABMATLAB§§ Modulator BoardModulator Board§§ Demodulator BoardDemodulator Board

Test SetupTest Setup

FPGASPARTAN 2 DAC Gain

Up Mixer

IF

10Digital Data

IF

Osc.

I/Q

Filter, Modulator

TransmitterTransmitter

ReceiverReceiver

FPGAVIRTEX 2

Digital Data

MixerIF

Osc.

IF

AGC ADC

I/Q

Demodulator,Filter,

AGC,

Carrier Recovery

Clock Recovery

CMA Equalizer

Clock RecoveryClock Recovery

VCXO

Clock Out

Filter

DAC10 Error

From FPGA