High-Performance ROM Design For Embedded

Applications Lin Hii Zlubiao Shao

Depamnent of ElectroNcs Engineering X i " Jiaotong University, Xi'an. 7 10019. P.R. China

Abstract: In tlus paper we describe a CMOS Read Only Memory arclitectnre designed for lugh performances and low power consumption using dyilamnic logic. A NOR-type stmctnre ROM is designed using tlie wired-nor cell a m y and single-phase operational clock control. By nsiiig tlie precliarge-discharge dynanuc logic, the voltage swing of tlie bitline can be kept small. thus iinprovc tlic opcratiiig speed and reduce the switclung power. The single-phase operational clock also benefits tlie interfacing to otlier blocks in tlie ASIC. This arcliitectun, is well snited for nicinories embedded within ASICs or SOCs due 10 its escellent speedlpower pcrfonnance and is v e n convenient for iinple~nentation using typical CMOS ASIC Process. Simulation and fabrication results sliow tliat tlie designed 1K words*28 bits Mask ROM n-orks a.ell as inicro-code inemor?. in tlie nucro-prograiiuned inicroprocessor.

1. Introduction

Einbedded Read Only Memories are required in an iiiipoflant nnniber of situations wlien designing ASICs. Studies 11ave shown tliat large finite state machines are usually siiialler and faster when implemented using a ROM. ROM mainly consists of inemor). cell amy. address dccodcr. sense amplifier. and 110 buffer. The on-chip ROM is nsually applied to store fixed infoni%ition such as nucro-code. lookup tables. words library. Tlie micro-code ROM is a key component in tlie Micro-progniiuiied nucroprocessors. n~lucli is in cllarge of generating (lie control signals for CPU execution. Microprogni~~i~~iing coiitrol approacli is coinlnonly used i n current processor design Such approacli lias many advantages including tlie reylarity of layont and tlie ease for clianging tlie inicro-code and lience is vcr?. coiivenient for silicon implementation. The designing of micro-code ROM lias become a key point in today's microprocessor design. wliose perfonimncc will be tlie possible bottlenecks for the CPU perfoniiance.

Tlie goal of tliis paper is to present a modular ROM arcliitccture fittiiig tliosc requirements. Several new ROM structnres are introduced and discussed first. Tlien a NOR-type CMOS ROM design is presented. wliicli lias been integrated into tlie micro-programmed microprocessor as the micro-code ROM. Esperiinental results show tlie correctliess of tliis ROM design.

2. Typical NAND-type ROM Structure

Two different architectures are coinnionly used in current ROM design: NAND-type and NOR-type. Tlie selection of different architecture results in different circuitty implementation tradeoffs. For Uie NAND-type ROM. tlie uiemnory cell transistors are stacked in serials. thus the source and drain area can be shared between hvo transistors. Hence the layout area can be greatly reduced. Considering current SOC with 4 0 4 0 % area could possibly be tlie inemnon blocks. tlie Iugh densities is tlie prii~ir) . highlight of NAND-type ROM. Its drawbacks inainly lie in: 1. Bitline lias to pass a long stacked traiisistors to discliarge wlien clianging froin '1'' to " 0 , thus slow down the working speed. 2. NAND-type ROM needs both enhancement and depletion-type MOS tramistors in tlie iiieinory cell array. Typical CMOS process. liowcver. does not provide tlie depletion-type transistor.

a i 13O- I

d o , ai0 i do i

Fig.1. Typirnl NAND-type ROM Strurtum

A typical NAND-type ROM circuit diagram is shown in Figure 1. AOI-structure is chosen for Uie inemnor). cell array to reduce tlie cell a m y silicon area. CK is the clock signal responsible for tlie precliarge of address decoder and ineiiiory cell amy. Row decoder-Y selects one bitline froin several parallel connected bitlines. Row decoder-X selects tlie wordline according to tlie input address. The un-selected wordlines remain high and condnct tlie nMOS wliereas tlie selected bitline become low 'The corresponding cell can't be conducted if it is an enluiiceiiient nMOS. and tlie bitline can't disclmrge to low. this represents storing "1". If Uie cell is a depletion

0-7803-7889-X/03/S17.00@2003 IEEE. 494

nMOS. it is ali

nl and pl are iised for preclurge. The output will be charged to Idgh when they conduct. wluch can decrease the effects of rising time. CK1 and CK2 are two-phase non-overlap clocks. When CKl is low. the decoder and cell amy enter into precliarge whereas the data output when ck2 is low.

7

Fii, S. NOR-type ROM with single-phase clock

5. Techniques for High-speed and Low-power ROM ciiruits

a) capacitance. If all bitlines are precharged to high during the precliarge phase. the power consumption is a big cost Tluougli selected bitline preclwe. onl? the bitline need accessed is precharged to high. the power waste can be greatly rediiced. This method is shown in Fig.7 [3].

As we know. ever?. bitline contains large parasitic

i '8

Fig. 6 Selcrrpd bithic prmhargo drruit b) tlie NAND-Fpe decoder in the address decoder is not a good idca. Tlic long disclurgc path can greatly affcct tlic high-speed perfonnance. A novel NOR-type address decoder can be used instead to accelerate tlie working speed [4]. This circuit is shown in Fig 8.

For the rcquirernent of high-speed ROM. adopting

T

4 Fix.. 7 NOR-type Row Decoder

Compared with conventional NAND-type decoder, nMOS M n MU, and a NAND are added. The address signals are rexersed to input to the address decoder. thus tlie parallel connected transistors can't be conducted.

Therefore node 1 can't discharge and the wordline reinnins high.

Noticed tlut C2 is much larger than C1. only a small capacitance C1 will need to be charged when the decoder begin to evaluate. Hence tlie power consuinption will also be reduced.

6. Iniplementation of a NOR-type ROM for Embedded Application

An on-clup inemory is needed lo act as micro-code ROM in the micro-programmed microprocessor design. The ineinory capacity is 1K wordsx28 bits. For the low clocking frequency reason a simplified style circuits is adopted in the design. Tlus can ensure that the design can be finished in a short time and the circuits operate reliably and robustly.

NOR-type memory cell array is applied in the ROM structure. There are 8 row lines and 2 column lines for address lines distribution. The Row decoder uses two stages decoder. The predecoder is shown in Fig. 9

Fig.8 Pre-clecder cireuit

11 .I Yeolder

Fip.9 Micro-code ROM Circuit

The column decode is essentially a Musl: 1 based on pass-transistor. Such Mus ,is very siniple in structure. However. it usually doesn't have enough driven capacity. Careful siinulation is needed to select the pass transistor W/L ratio. The full-swing bitlines greatly simplify the sense amplifier design. A simple CMOS inverter with the PMOS device sized six liines larger tllal llie NMOS device perfonns well in tenns of speed and noise-margin. Short circuit currents in the sense amplifier circuits are avoided by using a delayed enable signal (Sense Enable). Precise control is needed to generate tlie timing for the

delayed enable signal tlat activated the sense aniplifies circuits.

CcllsI Bitline

128 236 512

Fig.10 Opcmtinnnl tinting of singlc-phsr controI

The interface signals between the micro-code ROM aiid othcr blocks in tlie processor are Phil and Plii2. These two signals also act as tlie control signals for the micro-code ROM. PIU2 and phi1 are two-phase non-overlap clocks. When Phi2 is low the cell array and addrcss dccodcr arc prcchargcd. Wlicn Phil is low, address is decoded and corresponding data is output. The clocking control diagram is shown in Fig. 10

Ipm &mii ROM I$~cgnat ixd ROM Taccess ~ d c ? i h i ~ z Taccess P~@IMIIZ

7.2 0.287 I 11.9 0.3116 13,s 0.4535 18.6 0.5378 22.2 0.8294 30.4 0.9025

Pig.11 Tlw cowmtionnl NOH-lypr ROM Circuit

For the comparison purpose. anotlier NOR-type ROM is designed usiug the conventional single-phase ~eclniiqnc slio~\n in Fig.11. Tlie key different point of these two structures is that the bitlinc is the bottom node of each cell in Fig.9 nther than the top node in Fig. 11 . For studying the effectiveness of the new circuits. we liave tried different numbers of tlie NMOS cells i n oue bitline in the simulations. Simulation results are listed in Table 1

After finislung the layout based on O.6um CMOS process. tlie parasitic RC pinmeters can he ertncted. We use Star-Sitn to post-simulate tlie whole ROM circuits. Some simulation results is shown in Fig. 11. The sinidation sl~ows that tlic access time is only 13.5 11s. n-lucli can satisfi the need of microprocessor. This microprocessor has been fabricated using 0.6nm CMOS ASIC process. The chip tcsting result sliows that tlie designed Mask ROM works mell.

- Fig. 11 hliem-rodc ROM Input

i m . . ~ ~ .. . ~ ... . . .. .

Pip. 12. Post-siarulution results

7. Conclusion: We described a ROM arcluteclnre oriented toward

high speed and low power consumption. These two goals liave been aclueved using a precharge-discharge dynanuc logic combined with the NOR-type cell army. Several new ROM aclutectures lave also becn introduced and researched. A 1K words * 28 bits CMOS Mask ROM I u s been iiiiplernented using tlie structure presented in the paper. TICS CMOS ROM Ins been used as micro-code inemnot) in tlie micro-progranuned microprocessor.

References: [ I ] Jan. M. Rabaey. Digital Integrated Circuits: A

Design Perspective. Pg.560-572. Prentice-Hall International.. Inc..1999

[2j C.-R. Cliang. J.-S. Wang, and C.-H. Yang, IEEE J.of SSC.p.1516.Vol.36.No.lO.Oct.2001.

[3j N.Weste and K.Eshragluan. Principles of CMOS VLSI Design: A Systems Perspective, Second edition. Pg.583-590. Addison-Wesley. 1993. J . 4 Wang, C.-R. Ch;" and C. Yeh. IEEE J.of SSC_ p.125O.Vol. 36.No.8.Aug.2001

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