High Performance Low Power Single ChipReconfigurable Supercomputer for High-end

Aerospace ApplicationsVenkateswaran N∗, Arvind M†, Karthik C†, Karthik G†, Vishwanath V† and Viswanath K†

∗Director, WAran Research FoundaTion(WARFT)Chennai - 600 033 Email: waran@warftindia.org

†Research Trainee, WARFT,†Names Arranged in Alphabetical Order

Abstract— When it comes to Aerospace applications, power-aware computing plays an important role. There is always atrade-off between the power consumed and the performanceachieved. On the other hand, in on-board supercomputers, bothpower and performance are of equal importance, due to themission criticality of applications and hence, no trade-off isacceptable. In this paper, we present the capability of MemoryIn Processor Super Computer On a Chip (MIP SCOC)[1][2] toachieve sustained higher order performance by consuming lesspower as against the ALU architectures employed in conven-tional supercomputing clusters. The unique features of the MIPSCOC, the Algorithm Level Functional Units (ALFU) and theAlgorithm level Instruction Set Architecture (ALISA), are greatlyresponsible for achieving very high performance to power ratio.These varied class of algorithm level functional units are directlyamenable for efficient FPGA based implementation over theALU based node architectures. Through intensive simulations ofthe process of Mapping synthetic applications (custom designed,involving widest class of algorithms) on MIP SCOC, it is broughtout that the power reduction is achieved by drastic cut downin the number of memory accesses. By simulation it is foundthat on an average the ratio of number of MIP instructionsto that of IA32 for the designed synthetic applications is foundto be 1 to 330. The ALFUs are pipelinable and also parallelexecution of ALISA takes place across them. The average numberof instructions executed parallely in MIP SCOC is in the orderof few hundreds, leading to a peak performance of 1.72 TeraOpsand sustained performance of 1.46 TeraOps, in terms of MIPinstructions. Such compaction of high performance and lowpower aspects onto a single chip reduces the size of the on-boardsupercomputer to a large extent.

I. I NTRODUCTION

Evolution of novel architectural concepts is essential tosuccessfully harness the DSM technology which greatlyaggravates the Von-Neumann bottleneck. The conceptof Processor In Memory (PIM) architecture[3]was thefirst step that moved away from the conventional systemdesign approaches. In PIM-based architectures, memoryand processing logic are placed on the same die. The PIMarchitecture thus exploits large memory bandwidth andsignificantly low memory latency. Major supercomputerprojects based on PIM are VIRAM, Gilgamesh, BlueGene/Land DIVA[4][5][6][7].

The Memory In Processor architecture[8][1][2][9] wasproposed with the objective of improving the memory-processor bandwidth and attaining TeraOPS peak performanceat the node level itself. This is achieved by evolving anunconventional node and instruction set architecture whichwill exploit the power of DSM technology, giving rise toanother class of processing paradigm - Super Computer On aChip (SCOC).

Section II elucidates the various Aerospace applicationswhich demand high computational power for their execution.Section III analyzes the various computational requirementsof the Aerospace applications. Section IV discusses thevarious features of the MIP SCOC including its InstructionSet Architecture, Compiler Design and Algorithm LevelFunctional Units. Section V and VI deals with thereconfigurability[10] and the Low Power aspects of theMIP SCOC respectively.

II. OVERVIEW OF AEROSPACEAPPLICATIONS

A. Space Maneuvering

Satellites and interplanetary vehicles maneuvering betweenExtra Terrestrial objects require a lot of computations tobe performed. An orbital maneuver[11] is required when achange from one orbit to another is required. The same canbe accomplished by applying thrust or force in the reversedirection using propellants. The maneuvering can either beimpulsive or non-impulsive depending upon whether theexerted thrust is for a short time burst or for a low thrustexerted for a prolonged time interval. Only the former casecan be used for propulsion and serves to minimize the airdrag. The other kind of maneuvers are used for attitudemaneuvering. Attitude control is nothing but the control ofthe angular position and rotation of the spacecraft, relativeto the object that it is orbiting around. This is to positionthe spacecraft in the right orbit Due to mutual gravitationalperturbations between the planets and the satellites revolvingaround them. The eccentricities of the orbits may vary forthe satellites.

In order to escape from the planetary orbits necessarycalculations are to be made in order to maintain the angularvelocity of the revolving satellite. Sometimes a change intrajectory path may be required by the space craft which maybe accomplished through space maneuvering[12]. Effectivemaneuvering would help the spacecraft in reaching the desiredorbital plane without much fuel loss.

There are two types of maneuvers namely planned andunplanned maneuvers. Computations in planned maneuversare to execute programmed trajectories, ascent from trajectoryto satellite orbit, escape from planetary orbits, intermediatechanges in trajectories and launch to desired orbital planes.They involve solving of differential equations in the arena ofCelestial Mechanics and Aerodynamics.

Whenever an object or any obstacle is detected alongthe path of the spacecraft, the first step is the acquisition ofparameters such as distance, direction and velocity of theobstacle. Secondly these parameters are analyzed in order todetermine the instantaneous positional velocity of the obstaclewhich would involve intense scalar computations. ThirdlyIn-Flight Control and Velocity Correction mechanisms areexercised by the On-board Super Computers for successfulmaneuvering.

Reaction Thrusters are used primarily to control thedisturbances arising out of the system due to parasitictorques due to the usage of solid propulsion motors. ReactionThrusters are nothing but rocket propulsion elements. Theyare also employed in the mechanism of Velocity VectorManagement where using liquid propellants the short termintermittent forces are exerted by the reaction controlsystems in order to facilitate landing on the desired targetby the spacecraft and to control any irregularities in motionof the spacecraft. In these types of systems control is avital and crucial factor. Also the other major mechanism,which deserves attention, is the space rendezvous betweentwo spacecrafts, often between a spacecraft and a spacestation[13]. The space rendezvous is an orbital maneuverwhere the two space vehicles arrive at the same orbit, theorbital velocities of both are made the same aiding therendezvous to be performed smoothly.

B. Space Medicine

The Prolonged Manned spacecraft journey involves varioushealth risks. The first of it being the exposure to radiations andatmospheric gases. These radiations may be those originatingfrom the sun or those from beyond the solar system. Theradiation and their intensity level has to be monitored andcalls for efficient penetration proof mechanisms.

Cardiovascular disorders arise because Blood flow isquite normal when humans stay in the earth since much ofthe blood is collected in the lower part of the body[14].

But the blood flow activities become abnormal during spacetravel with much of the blood accumulating in the upperportion of the body. This would result in further complicationsleading to loss in body mass, and decrease in the calciumand phosphorus content in the body. Sometimes the redblood corpuscles also undergo transformations in their normalshapes and prolonged space travel also brings down the redblood corpuscle content by a considerable level.

Further it has been observed that the crew memberswere subjected to psychological stresses as they wereconfined to the spacecraft during their monotonous spacejourney. Also due to the loss of muscular activity and gravity,muscle atrophy results. Hence the Heart Beat Rate and BloodFlow Analysis are of utmost importance[15]. The spectralanalysis of the Heart Beat must be done. The heart rate can beQuantified using Time Domain Analysis or Frequency DomainAnalysis. Time Domain analysis process involves immensescalar Computations, which can be performed at ease usingthe High Level Scalar Functional Units available in the MIPSCOC. Since these functional units are pipelined and workin parallel the execution time for these algorithms is very less.

Further the brain activities must be tracked and analyzedfor their proper functioning during space travel. This wouldinvolve pattern matching to detect any mismatches or changesin the brain functioning from their positions. This wouldinvolve image processing which may include FFT Analysis,EEG Analysis, 2D plane projection, Linear matrix relatedtransformations and comparison of transformed images usingdedicated convolvers. Image segmentation can be done usinggraph partitioning algorithms and Image pattern matchingmakes use of matrix comparisons operations for detectingmismatches and the same can be handled by the matrix corefunctional units available in MIP SCOC.

Also the air composition inside the spacecraft can bemonitored and can be maintained or brought back to a desiredlevel. Due to prolonged space travel,it will be mandatoryto keep track of the air continuously. Contaminants may bepresent in the breathing atmosphere for many reasons. The airinside must be monitored for the presence of contaminantsand the level of contamination. Certain levels can prove to beharmful to crew’s health.

This necessitates continuous recycling of the air withinthe spacecraft. This process is done completely by automationwithout having one to manually monitor the air composition.This would involve scalar and vector operations for calculatingthe desired ppm value within the spacecraft. This wouldinvolve equation solving in Linear Algebra using Non LeastSquare Methods, Differential Equations to calculate thechanges in the parameters and the De-convolution process forcomparison of the present air composition with the statisticaldata already collected.

C. Remote Sensing

The other space application which is of primary importanceis Remote Sensing. Remote Sensing is the process ofaccumulation of information about a specified target bymeans of a device which is separated from the targetby a specified distance. This can help in exploring theresource availability on a particular planet known as planetaryExploration. Further it helps in target recognition and trackingthe target coordinates which involves the usage of imageconvolution and other Matrix Based Operations. SpectralAnalysis of photographs taken above the earth surface mustbe done.

They involve FFT analysis ,Acoustic Sounding methodsfor target detection etc. They involve techniques of stochasticmodeling, Image Compression and Digital Image Processing.Hazardous weather conditions can also be detected andreported. Modern remote sensing normally includes digitalprocesses but can also be done with non-digital methods. Thiskind of data collection normally makes use of the emittedor reflected electromagnetic radiations from the inspectingdevice towards the object under examination at a certainfrequency. The object under examination would reflect backor emit radiation at a wavelength and intensity quite differentfrom the one transmitted. Some remote sensing systemsuse acoustic variations to detect a target’s presence andparameters such as its distance and instantaneous velocity areused if the object is in motion.

III. R EQUIREMENT ANALYSIS FOR HIGH END AEROSPACE

APPLICATIONS

The aerospace applications that demand high performancecomputers for their execution are the ones which needextensive computing resources[16]. This high performancerequirement of the applications discussed previously can beachieved with the help of reconfigurable Memory In ProcessorSupercomputer On Chip (MIP SCOC)[8]. This feature ofreconfiguration increases Fault Tolerance and Reliability. Theresources which are available are a collections of identicalBasic blocks. When one block or a set of blocks fail theycan be replaced by an identical set of blocks with great ease.The other aspect to be taken into account, then consideringAerospace applications is the power consumed by theprocessors in executing computationally intense problems.The satellites or the space stations are equipped to satisfy thepower requirements of the On-Board Supercomputer until themission of the space craft is accomplished. In such cases,low power architecture becomes indispensable.

The computational nodes have to be designed to executethe varied operations of the applications. The process ofcompilation becomes tedious when the application involveslarge scale mapping and scheduling. The space applicationsalso demand an architecture with reduced device dimensions.

IV. MIP REVIEW

This review is based on the past papers on the MemoryIn Processor architecture. With the DSM technology onecan place hundreds of ALUs and Registers and evolve apowerful node. However such an approach is naive at best,as billions of low level instructions need to be executedand mapping within a node (resource allocation) becomesextremely complex. To reduce the above complexity, the nodeshould possess a wide class of Algorithm Level FunctionalUnits(ALFUs) like Matrix Multipliers and Graph theoreticunits.In this context the Architecture of all these functionalUnits should be designed to have a memory like Cell-Basedarchitecture.

Because of the increasing demand in the application areaslike Space maneuvering, Space Docking, Space Medicine,Remote Sensing, Satellite Imaging, Galaxy simulation,Brain modelling etc., it becomes mandatory to evolvesupercomputing clusters whose node architecture is highlytuned towards the application. This to a large extentalleviates the time complexity which is currently predicted inpetaflop years for applications running in general purposesupercomputers.

But evolving such architectures tuned to specific applicationsmay be cost prohibitive. This necessarily leads to theevolution of a new concept of Simultaneous MultipleApplication Mapping(SMAPP). Under such conditions itis necessary to make the node architecture heterogeneousinvolving varied functional units covering wide applications.

Though the simultaneous multiple application mappingmay appear complex, it is resolved by the higher level ALISA-based library design resulting in a simplified mapping process.On the other hand, the ALU-libraries for general purposesupercomputers are designed specific to every application andare bound to be complex due to their generic(ALU) nature.Thus the general purpose supercomputers become unsuitablefor handling simultaneous multiple applications.

All Functional Units are organized as 2-D Cell Arraysintegrating 1 Bit SRAM as in Figure .1 with every cell of theFunctional Units.

The control of both the processor and the memory are alsointegrated at the physical level. Based on extensive analysisof wide class of Algorithms the different types of ALFUsare organized into Segments. These segments are logicallygrouped into columns. There are eight columns each havingfour segments. Inter and intra column communication isprovided using three stage non-blocking Clos interconnectionnetwork.

Fig. 1. Merging of 1 bit SRAM into Functional cell.

A. MIP Instruction set Architecture

The MIP (Memory In Processor) Instruction SetArchitecture is a higher order ISA designed to suit thealgorithm level capabilities of the MIP SCOC functionalunits.

The MIP SCOC ISA is referred as Algorithm LevelInstruction Set Architecture (ALISA)[17] and is presentedin the Table shown in Figs.2,3. The instructions of ALISAare categorized into Graph-theoretic, Vector-Related, MatrixRelated, Scalar, ALFU - ALFU and SRAM - ALFU datatransfer.

Every instruction in ALISA is a substitute for a large numberof corresponding ALU instructions. Each instruction inALISA is at a sub-algorithm level that gets executed on anALFU directly.

This brings down the corresponding number of memoryfetches in MIP SCOC over the conventional ALU based nodearchitecture of the current supercomputing clusters. The designof ALISA makes the MIP Instruction Set Architecture simpler.

Fig. 2. MIP Instruction Set Architecture.

Fig. 3. MIP Instruction Set Architecture.

B. MIP Compiler On Silicon

In MIP SCOC, due to the presence of ALFUs, a rigorousmapping process is involved in scheduling ALISA instructionsand balancing computations within the ALFUs population.This mapping in the MIP SCOC node is a complex process.To manage the complexity, a hardware based compiler[17]isneeded matching the MIP SCOC performance. Compilers forsuperscalar processors were the first to incorporate implicitdetection of instruction level parallelism and scheduling thesame. The most frequently used libraries will exist in theexecutable form. These executable libraries are bound toinvolve billions of instructions. Though the library existsin executable form, resource allocation (as in superscalars)during execution will be a time consuming process. Inparticular, if the resources within a node as in MIP SCOCbecome heterogeneous and large in number, a software basedmethodology will be too tedious a process for making optimalresource allocation. Hence, we resort to a hardware basedsolution (mapping and scheduling)for resource allocations inthe MIP SCOC reducing the compilation process delay.

Fig. 4. A Basic MIP Node Architecture.

This hardware means is achieved by a set of eight SecondaryCompilers On Silicon (SCOS) mesh connected units drivenby a Primary Compiler On Silicon (PCOS) unit. These PCOSand SCOS units posses a MIP based design similar to thatof ALFUs. In order to enable concurrent instruction issueto the various columns, the functionality of the COS hasbeen partitioned into two levels specifically as the primaryand secondary compilers on silicon. These SCOSs functionunder a common host-compiler (Primary COS - PCOS),which control the allocation of the sub-libraries. The problemis allocated by the hosts (in a cluster environment) to thePCOS in terms of built-in libraries. The PCOS takes up theincoming set of libraries, decomposes them into sub-librariesand passes them to the respective SCOSs for execution withina particular column.

The PCOS takes care of mapping the problem to thedifferent SCOSs that are under its control. The executionof the sublibraries is carried out by the SCOSs independentof each other and they communicate with the PCOS uponcompletion. As problem execution proceeds, communicationbetween the SCOSs may be required to move the sub-libraryresults across the columns for further execution. A mesh-connected topology is employed for linking the eight SCOSsfor efficient execution. The Basic node architecture of MIPSCOC is shown in Fig.4

1) PCOS Library specification:The library specificationwithin the PCOS provide details for decoding andperforming the necessary operation. This specificationprovides information about the operation to be performed,logical schedule time instants, dependencies and HLF unitsrequired. In the PCOS, the library is broken into sub-libraries.When multiple sub-libraries are associated with the sametime-stamp, they are scheduled in parallel. Based on the SCOSresource constraints, PCOS might schedule the sublibrariesover multiple cycles.

2) SCOS Sub-Library specification:The sub-librariesare executed within a specific column controlled by aSCOS. These sub-libraries break into HLF instructions thatperform the required operation. A single instruction word cantrigger multiple HLF units simultaneously. Data movementwithin a column occurs due to dependency between theHLF instructions. Based on operation the appropriate Moveinstruction triggers transfer within or across segments.

C. ALFU (Algorithm Level Functional Units)

The instruction control words for executing the algorithmlevel instructions in the respective ALFUs present in thecolumn segments are issued by the different SCOSs. Theseinstruction control words are generated with their associatedoperands and their corresponding HLF id. These instructioncontrol words trigger the ALFU’s local controller and thenecessary operations are performed to carry out the executionof the algorithm level instruction. To simplify the decodingprocess of identification of HLF unit types, each HLF typehas a field in the instruction control word. If a particular HLFunit is not being triggered for a particular operation, a ’NO-OP’ fills up that field.

V. RECONFIGURATION IN MIP SCOC

Reconfiguration in MIP SCOC Reconfigurability[10]is defined as the ability to adjust the functionality ofan architecture for new application requirements throughrearrangement or change of the basic blocks. Reconfigurabilityprovides flexibility and fault tolerance aspects of the systemwhich are indispensable in considering the criticality of thespace applications.

Fig. 5. Re-Configuration in ALFUs

Fig. 6. 32-bit Multiplier Architecture

Reconfiguration in MIP SCOC begins initially with theidentification of Basic Blocks.The functional unit design isrepresented in terms of the basic block design Reconfigurationis a phenomenon where these basic blocks can be dynamicallyConfigured in order to form the Algorithm Level FunctionalUnits(ALFU’s)as shown in Fig.5.

The basic block(Fig.14) has been fixed up to be two 64-bitMultipliers, and two 128-bit adders. The components of thebasic block say the 64-bit multiplier are built by using four32-bit multipliers and in turn these 32-bit multipliers using16-bit multipliers and so on.The architecture of a 32-bitmultiplier is shown in Fig.6.The Figures 7,8,9,10,11,12 givethe snapshots of the gates getting triggered at various timeinstances of 32-bit and 128-bit adders.The Figure.5 gives anexample of reconfiguring the resources for various matrixoperations.

Fig. 7. 32 bit Multiplier Snap Shot-1

Fig. 8. 32 bit Multiplier Snap Shot-2

Fig. 9. 32 bit Multiplier Snap Shot-3

Fig. 10. 128 bit Adder Snap Shot-1

Fig. 11. 128 bit Adder Snap Shot-2

Fig. 12. 128 bit Adder Snap Shot-3

The main elements of the basic block have been designedand verified using VHDL coding.This VHDL output for asubset of MIP instructions along with their reconfigurationas timing diagrams are presented from Figures six throughtwelve. The table shown in fig.13 gives the different gatedelays associated with the different adder and multipliercomponents at a clock speed of 500 MHz.

The clock used in the MIP are of three levels namelyat the COS level, the segment level and then Block level witha speed of 500 MHz, 1500 MHz and 3000 MHz respectively.Controls at the PCOS, SCOS, segment and basic block areall distributed controls.

Fig. 13. Gate Delays

Fig. 14. Basic Block Diagram

Fig. 15. a)and b)Adjoint and Transpose Calculation for the set of 144 BasicBlock design c)and d)Adjoint and Scalar Division Calculation for the set of144 basic block design

Figures 15,16,17 show the utilization of the resourcesat every stage in computing the cofactor and determinant inthe process finding matrix inversion. Firstly 96 multipliersand 8 adders are used up in parallel for the cofactorcomputation. Then 48 adders and 4 adders are used up inthe determinant computation. Similarly the reconfigurationprocess is explained for the remaining adjoint calculation andthe scalar division operations.

Fig. 16. Co-Factor and Determinant Calculation for the set of 144 basicblock design

Fig. 17. Co-Factor and Determinant Calculation for the set of 144 basicblock design

VI. L OW POWER ASPECTS

The Memory In Processor Architecture aims at reducingthe Power consumed by the chip. Firstly the instructionsbeing at the Algorithm Level in the ALISA, the numberof instructions gets reduced significantly when comparedwith the conventional architectures. Then, the fine grainedintegration of the memory with the processing elements inthe architecture, along with the Algorithm Level FunctionalUnits minimize the number of memory accesses.

This decrease is mainly due to the reduction in thenumber of Instruction Fetches and the local availabilityof the intermediate data. The increased Memory processorbandwidth because of the integration of the memory with theprocessing elements helps in reducing the access time.

The memory bandwidth is the one which decides theperformance of the current day processors. The reductionin the number of memory accesses not only increasesthe performance but also brings down the power to alarge extent. The architecture with its characteristic LowPower consumption suits the requirement of the On-BoardSupercomputers.

1) Simulation Results:To prove the memory efficiency ofthe architecture, synthetic applications have been designedwith a combination of algorithms of varying computationaland communicational complexity. These synthetic applicationsare then decompiled into equivalent IA32 instructions.

Fig. 18. Low Power Table

The same synthetic applications are converted into MIPinstructions using the MIP compiler. On comparing thenumber instructions there is a huge difference between that ofMIP and Ia32. The results are shown in the Table in Fig.18.The table differentiates between the various aspects of MIPand the IA32. The ratio of number of instructions of that ofMIP to that of IA32 comes around 1 to 330. The simulationresults shown in Fig.18 bring out the low power aspectsof MIP SCOC without sacrificing on performance. TheALFU architectures are such that a single ALISA instruction,say for instance, a matmul (Matrix Multiplication) or ascalar multiplication instruction can initiate pipelined parallelexecution of scores of operations. This is substantiated bythe fact that a single ALISA instruction gets mapped onto allthose similar type ALFUs which together function to executea higher order problem.

2) Illustration: For example, mapping of matrixmultiplication problem of order 16x16 would require 64, 2x2MATMUL ALFU Units and these 64 Units can be triggeredusing a single MATMUL instruction fetch. Effectively, oneinstruction fetch leads to 64 instruction executions. Thedata corresponding to all the individual ALFUs is loadedin parallel onto them. Further, a single ALISA instructionon an average corresponds to numerous conventional ALUInstructions. In this case, a single MATMUL instructioncorresponds to 8 Scalar Multiplication Instructions and 4Scalar Addition Instructions. Apart from this, a single ChainMatrix Adder (CMA) instruction that initiates the 64 CMAHLF Units used here, can trigger the addition of 8, 2X2Matrices corresponding to each CMA HLF Unit. The CMAunit is made up of 4 MOA Units each capable of adding upto64 operands.

Effectively, 2 MIP Instruction fetches (1 of MATMULand 1 of CMA) can perform Matrix Multiplication ofmatrices of the order of 16X16. The corresponding number ofALU Instructions sums up to 2560. Hence, the execution ofa single ALISA instruction on an average would correspondto a few hundred ALU instructions as proved by oursimulation results. In this case, the ratio of the number ofMIP Instructions to that of ALU Instructions is 1:1280.

VII. C ONCLUSION

This paper highlights the reconfigurability of the MIPSCOC and the memory efficiency of the Algorithm LevelInstruction Set Architecture (ALISA) over the conventionalALU based ISAs. Synthetic applications analogous to realworld applications such as aerospace related applications,have been chosen to establish the above stated fact. Thenode level simulations show a drastic decrease in the averagememory fetch operations. These applications could serveas effective benchmarks in evaluating the performance ofsupercomputers.

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