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HIGH PERFORMANCE CMOS WITHMETAL INDUCED LATERAL CRYSTALLIZATION

OF AMORPHOUS SILICON

A DISSERTATION

SUBMITTED TO THE DEPARTMENT OF

ELECTRICAL ENGINEERING

AND THE COMMITTEE ON GRADUATE STUDIES

OF STANFORD UNIVERSITY

IN PARTIAL FULFILLMENT OF THE REQUIREMENTS

FOR THE DEGREE OF

DOCTOR OF PHILOSOPHY

Amol Ramesh Joshi

March 2003

c© Copyright by Amol Ramesh Joshi 2003

All Rights Reserved

ii

I certify that I have read this dissertation and that, in my opinion, it is fully adequate

in scope and quality as a dissertation for the degree of Doctor of Philosophy.

Krishna Saraswat(Principal Advisor)



James Plummer(Associate Advisor)



Michael Deal

Approved for the University Committee on Graduate Studies.

iii

Abstract

Depending on the circuit architecture, the performance of VLSI chips is dominated by in-

terconnects and it will get even worse in the future. With every generation, as the transistor

size keeps shrinking, the chip size is increasing. As a result, the interconnect cross sections

are shrinking but the lengths are increasing. Fabricating an integrated circuit using multi-

ple layers of transistors is a promising approach towards improving chip performance. In a

multiple layer integrated circuit (3-D IC) scheme, blocks of circuits are arranged in differ-

ent layers of Si on the same chip, instead of placing them side by side, and then connected

by short, vertical interconnects. This has an advantage of reducing lengths as well as the

number of long interconnects so that the chip can operate at higher speeds.

For a 3-D IC, it is desirable to have the performance of transistors, fabricated on upper

layers, close to that of bulk-Si transistors. However, a significant reduction in fabrica-

tion temperatures may be needed in order to preserve the lower layers of transistors and

interconnects. In this thesis, we present high performance CMOS devices with a peak

processing temperature of 500C which constitute a promising step towards realizing 3-

D integrated circuits. The lowering of processing temperature is achieved by using metal

induced crystallization (MIC) of silicon. Needle-like crystal growth during metal induced

lateral crystallization (MILC) is used to obtain a MOS channel free of grain boundaries.

Using this MOS channel with the dopant activation during MIC, high performance, submi-

cron CMOS devices are obtained.

v

A physical model for crystal growth during nickel induced crystallization is discussed in

detail and compared with the experimental observations of crystal growth from literature.

The model makes use of two regimes of crystal growth: diffusion limited and surface

reaction limited. It also attempts to compare MIC and solid phase crystallization (SPC).

Dopant activation has been found to occur during MIC. An interesting application of

MIC for dopant activation in MOS gate electrode is demonstrated and its effects on the

reliability of gate oxide are analyzed.

MIC may enable us to build transistors needed for 3-D integrated circuits at lower

temperatures and therefore help relieve problems that may be faced by many VLSI chips

in the future.

vi

Acknowledgments

I would like to thank my advisor, Prof. Krishna Saraswat for his support and guidance even

when things were not working out. It was a pleasure to work with him.

I also thank Prof. James Plummer and Dr. Michael Deal for being on my orals as well as

reading committee. I thank Prof. Piero Pianetta for being the Chair of my orals committee.

Funding for my Ph.D. work was provided by DARPA and MARCO Interconnect Focus

Center. I thank them for keeping my research going.

Irene Sweeney helped me a lot during my Ph.D. She took care of the administrative

hurdles very efficiently.

Throughout my Ph.D. career, Dr. James McVittie was very resourceful. He offered lots

of relevant advice and helped me with finding old and rare references in a short time. He

also helped me with getting approval for introducing Nickel in the fabrication facility.

The experimental work of transistor fabrication was mostly done at Stanford Nanofabri-

cation Facility (SNF). I would like to thank the people who maintain the facility especially

Gladys Sarmiento, Bob Wheeler, Nancy Latta, Keith Gaul, Len Booth, Mark McCord,

Paul Jerabek, Margaret Prisbe and Robin King. Dr. Eric Perozziello provided important

information on special lab processes.

Some critical work with ebeam was done at UC Santa Barbara Nanofab. I thank Bill

Mitchell and Ernie Caine for accepting my work at a short notice and for finishing my long

pending work in two days.

vii

I am thankful to Prof. Tsu-Jae King of UC Berkeley and her students, especially Dr. Nick

Lindert and Dr. Wen-Chin Lee for Ni deposition.

At Stanford, I got a lot of help for TEM from Dr. Ann Marshall, Yaocheng Liu and

Rohit Shenoy. Chi On Chui helped me obtain lots of SEM pictures.

My research and thesis would not be complete without help from Saraswat group mem-

bers. I am most thankful to Dr. Vivek Subramanian who was my mentor when I joined

Saraswat group. He also got me started on my project on Metal Induced Crystallization.

Tejas Krishnamohan coauthored my paper on theory of metal induced crystallized. In the

process I received valuable understanding of MILC which I would have probably missed

otherwise. I interacted a lot with Chi On Chui about devices for 3-D ICs and other experi-

ments on MIC. Other past and present members from whom I got a lot of help through stim-

ulating discussions on different topics are Dr. Albert Wang, Dr. Navakant Bhat, Dr. Steve

Jurichich, Dr. Mayur Joshi, Dr. Shahram Alibeik, Dr. Tien-Chun Yang, Dr. Pawan Kapur,

Dr. Ben Shieh, Dr. Ting-Yen Chiang, Dr. Shukri Souri, Dr. Nabeel Ibrahim, Dr. Pranav

Kalavade, Rohit Shenoy, Gaurav Chandra, Ali Okyay and Ammar Nayfeh.

People from various other groups also helped me through discussions. I would like

to mention Yaocheng Liu, Sameer Jain, Kailash Gopalakrishnan, Dr. Niranjan Talwalkar,

Omer Oralkan, Richard and Lalit.

During my stay at Stanford, my life was made enjoyable by a number of friends but this

space is too small to list all of them.

I would like to acknowledge my wife Anuradha for her love and encouragement. She

read my papers and thesis carefully and corrected grammatical errors.

No amount of thanks are enough for three people. They are my parents and my younger

brother, Ashish. It is due to their love, encouragement and sacrifice, was I able to reach this

milestone. It must have been difficult for them to accommodate me for 17 years and then

let me stay away for next 10 years. This thesis is dedicated to them.

viii

Contents

Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v

Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiv

1 Introduction 1

1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.3 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2 Background 4

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.2 Motivation for 3-D ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2.1 VLSI Performance Limitations due to Interconnects . . . . . . . . 5

2.2.2 Limitations of Cu Interconnects . . . . . . . . . . . . . . . . . . . 6

2.2.3 3-D IC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.3 Performance Comparison of 2-D and 3-D ICs . . . . . . . . . . . . . . . . 9

2.4 Realizing 3-D ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.4.1 Si Recrystallization with Laser Beams . . . . . . . . . . . . . . . . 13

ix

2.4.2 Wafer Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.4.3 Epitaxial Regrowth from Substrate . . . . . . . . . . . . . . . . . . 14

2.4.4 Seeded Crystallization of Silicon . . . . . . . . . . . . . . . . . . . 15

2.5 Low Temperature Crystallization of Silicon . . . . . . . . . . . . . . . . . 16

2.6 Ge Seeding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.7 Metal Induced Crystallization . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.8 Dopant Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.9 Fabrication of MOS Transistor with MIC . . . . . . . . . . . . . . . . . . 20

2.10 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3 A Model for Crystal Growth during Metal Induced Lateral Crystallization of

Amorphous Silicon 22

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.2 Relation between MILC Growth Rate and NiSi2 Thinning Rate . . . . . . . 26

3.3 Diffusion Limited Regime . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.4 Surface Reaction Limited Regime . . . . . . . . . . . . . . . . . . . . . . 33

3.4.1 Surface Reaction Rate Unchanged with Time . . . . . . . . . . . . 34

3.4.2 Surface Reaction Rate Decreases with Time . . . . . . . . . . . . . 35

3.5 Combined Model for MILC Growth Estimation . . . . . . . . . . . . . . . 37

3.5.1 Large Values ofτ1 . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.5.2 Small Values ofτ1 . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.6 Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

4 Crystallization and Dopant Activation with Metal Induced Crystallization 46

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4.2 Experimental Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

x

4.2.1 Dopant Activation . . . . . . . . . . . . . . . . . . . . . . . . . . 48

4.2.2 TEM Study of Crystal Growth During MILC . . . . . . . . . . . . 48


4.3.1 Dopant Activation Results with Spreading Resistance Analysis . . . 50

4.3.2 TEM Results for MILC . . . . . . . . . . . . . . . . . . . . . . . . 50

4.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

5 Nickel Induced Crystallization of α-Si Gate Electrodes at 500C and MOS

Capacitor Reliability 57

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

5.2 Experimental . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58


5.3.1 SIMS and Spreading Resistance Analysis . . . . . . . . . . . . . . 58

5.3.2 TEM Studies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

5.3.3 C-V Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . 63

5.3.4 I-V Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.3.5 Oxide Reliability with QBD Measurements . . . . . . . . . . . . . . 68

5.3.6 Zerbst Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

5.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

6 High Performance Submicron CMOS with Metal Induced Lateral

Crystallization of Amorphous Silicon 73

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

6.2 CMOS Transistor Fabrication . . . . . . . . . . . . . . . . . . . . . . . . . 74


6.3.1 Performance of CMOS with MILC at 500C . . . . . . . . . . . . 76

6.3.2 Performance of CMOS with MILC at 450C . . . . . . . . . . . . 78

xi

6.3.3 Effect of Device Width . . . . . . . . . . . . . . . . . . . . . . . . 81

6.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

7 Conclusions 86

7.1 Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

7.1.1 A Model for MILC . . . . . . . . . . . . . . . . . . . . . . . . . . 86

7.1.2 Metal Induced Crystallization and Dopant Activation . . . . . . . . 87

7.1.3 MIC Dopant Activation and MOS Capacitor Reliability . . . . . . . 87

7.1.4 High Performance CMOS with MILC . . . . . . . . . . . . . . . . 87

7.2 Recommendations for Future Work . . . . . . . . . . . . . . . . . . . . . . 88

Bibliography 89

xii

List of Tables

2.1 A Summary of Metal Induced Crystallization observations. Source: Ob-

tained in part from Konnoet al.[36]. . . . . . . . . . . . . . . . . . . . . . 19

3.1 Lattice constants of some silicides. . . . . . . . . . . . . . . . . . . . . . . 24

5.1 Annealing conditions for crystallization of the gateα-Si on experimental

and control wafers. Wafers B and C do not have any silicide. . . . . . . . . 59

6.1 Performance of submicron MILC transistors. . . . . . . . . . . . . . . . . 78

xiii

List of Figures

2.1 Comparison of gate and interconnect delays (longest global wire) using the

2001 ITRS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2 Schematic of a 3-D IC showing devices on separate Si layers and VILICs.

Source: Derived from Fig. 11 in Banerjeeet al.[3]. . . . . . . . . . . . . . 8

2.3 Schematic of 3-D IC with heterogeneous technologies on different layers.

Source: Derived from Fig. 12 in Banerjeeet al.[3]. . . . . . . . . . . . . . 9

2.4 Wire length distributions for 2-D and 3-D ICs. Source: Banerjeeet al.[3]. . 11

2.5 Wire limited chip area as a function of semi-global pitch for 3-D chip.

Operating frequency is 3 GHz. Source: Banerjeeet al.[3]. . . . . . . . . . 12

2.6 Comparison of 2-D and 3-D ICs with respect to operating frequency. Source:

Banerjeeet al.[3]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.7 Epitaxial lateral overgrowth for 3-D IC. . . . . . . . . . . . . . . . . . . . 15

2.8 Simplified schematic cross section of TFT. Interlayer oxide and metal are

not shown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.1 Molar free energy of a mixture of Ni and Si. Ni has a lower free energy at

the NiSi2/α-Si interface while Si has a lower free energy at the NiSi2/c-Si

interface. Source: Derived from Fig. 14 in Hayzeldenet al.[51]. . . . . . . 24

xiv

3.2 Schematic diagram showing NiSi2 precipitate orientations favorable (〈110〉)

and unfavorable (〈100〉, 〈111〉) for MILC. The 〈100〉 and〈111〉 oriented

precipitates have normals which will intersect either the top or bottom sur-

face. Source: Derived from Fig. 12 in Hayzeldenet al.[51]. . . . . . . . . . 25

3.3 Illustration of MILC starting from a long line of Ni. . . . . . . . . . . . . . 27

3.4 Schematic diagram showing 1-D NiSi2 mediated crystallization ofα-Si. . . 28

3.5 Diagram showing Ni concentrations in different regions during MILC. . . . 31

3.6 Comparison of model and experimental results for MILC length. . . . . . . 41

3.7 Comparison of model and experimental results for MILC rate. The tran-

sitions between diffusion limited and surface reaction limited regimes are

marked by circles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.8 Results of numerical calculations of MILC length for combined model. . . 43

3.9 Results of numerical calculations of MILC growth rate for the combined

model. The transitions between diffusion limited and surface reaction lim-

ited regimes are marked by circles. . . . . . . . . . . . . . . . . . . . . . . 44

4.1 Effects of grain boundaries on transistor performance. Source: Subrama-

nianet al.[29] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

4.2 Schematic of dopant activation experiment. . . . . . . . . . . . . . . . . . 49

4.3 Spreading resistance measurement profiles of the samples for dopant acti-

vation experiment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4.4 (a) Plan view TEM of MILC region; (b) selective area diffraction pattern

of MILC poly-Si; and (c) selective area diffraction pattern ofα-Si. . . . . . 53

4.5 (a) TEM of transistor structure; (b) selective area diffraction pattern; and

(c) boundary ofα-Si and crystallized Si. . . . . . . . . . . . . . . . . . . . 54

4.6 Illustration of MILC growth in wide and narrow channel regions. . . . . . . 55

5.1 Schematic cross section of MIC capacitor. . . . . . . . . . . . . . . . . . . 60

xv

5.2 SIMS profiles: (a) Ni and P in the gate stack; and (b) Ni in the substrate. . . 61

5.3 Spreading resistance profiles in the gate stack. . . . . . . . . . . . . . . . . 62

5.4 Cross section TEM of the gate stack: (a) wafer A; and (b) wafer B. . . . . . 64

5.5 C-V plot overlay: (a) low frequency; and (b) high frequency. . . . . . . . . 65

5.6 I-V characteristics for capacitors: (a) inversion; and (b) accumulation. . . . 67

5.7 QBD for gate and substrate injection of electrons. . . . . . . . . . . . . . . 69

5.8 Schematic band diagrams for wafer A (with Ni) and B (no Ni). . . . . . . . 70

5.9 Zerbst plots for wafers A and B. . . . . . . . . . . . . . . . . . . . . . . . 71

6.1 Schematic 3-D view of transistor channel island before gate electrode de-

position and patterning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

6.2 Schematic cross section of transistor showing MILC process. . . . . . . . . 76

6.3 ID vs. VG for 500C crystallized devices: (a) NMOS; and (b) PMOS. . . . 79

6.4 ID vs. VD for 500C crystallized devices: (a) NMOS; and (b) PMOS. . . . 80

6.5 ID vs. VG for 450C crystallized devices: (a) NMOS; and (b) PMOS. . . . 82

6.6 ID vs. VD for 450C crystallized devices: (a) NMOS; and (b) PMOS. . . . 83

6.7 ION and IOFF as a function of device width for 500C crystallized devices:

(a) NMOS; and (b) PMOS. . . . . . . . . . . . . . . . . . . . . . . . . . . 84

xvi

Chapter 1

Introduction

1.1 Motivation

As transistor scaling progresses more or less as predicted by the International Technology

Roadmap for Semiconductors (ITRS) [1] roadmap, the number and length of interconnects

also increases. Since the scaled down transistors have smaller delays than those of long

interconnect lines, the speed of typical VLSI chips such as microprocessors is currently

limited by interconnect delay. Since there is a practical limit to improving conductivity of

interconnect metals by using new materials like copper, new methods of circumventing this

obstacle are being explored by various research groups.

One of the ways of achieving improved chip speed is by arranging transistors in multiple

layers instead of a conventional single layer. These transistors on different layers are then

connected using short, vertical, interlayer interconnects (VILICs) [2]. As a result of this

arrangement, long interconnects are replaced by shorter interconnects and the chip speed

is improved. Multiple layer integrated circuits (3-D ICs) can be built by wafer bonding or

by fabricating transistors in deposited layers of silicon. In this thesis, the latter approach is

1

2 Chapter 1 : Introduction

explored.

Device fabrication in a 3-D IC may face processing temperature limitations in order to

preserve underlying interconnects and devices. With that in mind, metal induced crystal-

lization (MIC) has been used in this work to reduce the peak processing temperature. In

MIC, a thin layer of amorphous silicon (α-Si) is deposited over already fabricated devices

and interconnects. In order to lower the crystallization temperature, metals like Ni are

deposited in lithographically defined areas ofα-Si films. Upon annealing, crystallization

occurs from these areas. In the crystallized regions, MOS transistors can then be fabricated.

1.2 Objectives

The goals of this thesis are:

1. To gain a theoretical understanding of MIC process and obtain a model for crystal

growth.

2. To study crystallization and dopant activation using MIC.

3. To explore effects of Ni on reliability of MOS capacitors when used to activate

dopants in gate electrode.

4. To fabricate high performance MOS transistors with the help of metal induced lateral

crystallization (MILC) of silicon.

1.3 Thesis Organization

Chapter 2 starts with an introduction to 3-D ICs and also goes into the background work on

low temperature crystallization of amorphous silicon including metal induced crystalliza-

tion. It will give some theoretical basis for the MIC/MILC process. This is then continued

1.3 : Thesis Organization 3

with a physical model for crystal growth during MILC which is proposed in Chapter 3,

based on crystal growth data available in the literature. Crystallization and dopant activa-

tion using nickel induced crystallization are described in Chapter 4. The effects of using Ni

for gate dopant activation on MOS capacitor reliability are presented in Chapter 5. Chap-

ter 6 describes fabrication of submicon CMOS with MILC and the results. Finally, the

conclusions of this work and recommendations for future work are stated in Chapter 7.

Chapter 2

Background

2.1 Introduction

With advancing transistor technology and growth of the electronics industry, there are de-

mands on VLSI chips for increased functionality and reduced power and cost. The delays

of transistors have reduced with scaling but at the same time interconnect delays have

increased rapidly. In addition, a big fraction of chip power is being dissipated in intercon-

nects. Increasing demands for integration of different technologies are being realized with

System-on-Chip (SoC) designs which may become difficult to achieve in a conventional

2-D IC. Recently, it has been shown that 3-D ICs may present a method to alleviate some

of the problems mentioned above [3]. The motivation for 3-D ICs will be discussed in the

beginning of this chapter. After the discussion of different techniques for obtaining 3-D

ICs, background work on low temperature crystallization of silicon and related topics will

be presented.

4

2.2 : Motivation for 3-D ICs 5

2.2 Motivation for 3-D ICs

2.2.1 VLSI Performance Limitations due to Interconnects

With growing demands for increased functionality and complexity of modern VLSI chips,

the area and density of transistors is increasing with every generation. In order to fit more

and more transistors in same area, transistor dimensions are being scaled aggressively.

While this scaling has successfully reduced the gate delays, interconnect performance has

degraded significantly. Due to the reduction in width and height of wires and increased

lengths, the resistance and capacitance of these wires have increased. This has resulted in

a significant increase in RC delay which is much larger than the gate delay. Depending on

the circuit architecture, the performance of VLSI chips may be dominated by interconnects

and it will get even worse in the future. Fig. 2.1 shows a comparison of interconnect RC

delays vs. gate delays based on the 2001 ITRS [1]. The numbers for the gate delay were

taken from the ITRS. The longest interconnect delays were optimized with repeaters. They

were calculated from the following formula given in Banerjeeet al.[3].

τd = 3.24L√

2.4rr0ccNMOS (2.1)

τd is the delay of the interconnect with repeaters.L is the total length of the interconnect.

r andc are the interconnect resistance and capacitance per unit length.cNMOS is the gate

capacitance of the minimum sized NMOS andr0 is its resistance. The calculations for

RC delay in Fig. 2.1 were done assuming ideal Cu resistivity. As explained below, Cu

resistivity and hence the RC delay will be even higher in reality.

6 Chapter 2 : Background

10-4

10-3

10-2

10-1

100

101

20 30 40 50 60 70 80 90

Del

ay (n

s)

Feature Size (nm)

Interconnect RC Delay

Gate Delay

Figure 2.1: Comparison of gate and interconnect delays (longest globalwire) using the 2001 ITRS.

2.2.2 Limitations of Cu Interconnects

Cu with low-κ dielectric was introduced to alleviate the problems of increasing interconnect

RC delays [4–7]. Cu is one of the best conductors available at temperatures close to 100C.

Due to its low resistivity, it can be expected to reduce the RC delays. Limitations for

Cu interconnect result mainly from two factors; (i) increase in the resistivity of Cu with

decreasing wire cross section and (ii) barrier layer thickness [8].

Because of increased electron scattering from interconnect walls, the effective resis-

tivity of Cu will increase as interconnect dimensions shrink. The surface scattering effect

depends on a parameterk which is given byk = d/λmfp whered is the smallest dimension

of the wire andλmfp is the mean free path of electrons. The effect of surface scattering on

2.2 : Motivation for 3-D ICs 7

resistivity was calculated by Campbell [9]

ρs

ρ0=

1

1− 3(1−P )λmfp

2d

∫∞1 ( 1

x3 − 1x5)

1−e−kx

1−Pe−kx dx(2.2)

ρs andρ0 are resistivities with and without surface scattering. ParameterP indicates the

extent of specular scattering from the surface.P lies between 0 and 1. A value of 1

indicates complete specular reflection while a value of 0 indicates diffuse scattering.

The second component which adds to the resistivity is the barrier layer which is put

down to prevent Cu diffusion from interconnects. Since the barrier layer thickness does

not scale rapidly with technology, it occupies a higher and higher fraction of the wire cross

sectional area. IfAb is the area occupied by barrier, AR is the aspect ratio of wire and

W is the width, then the effective resistivityρb can be calculated using a simple resistivity

formula to beρb

ρ0=

AR×W 2

AR×W 2 − Ab=

1

1− AbAR×W 2

(2.3)

As the wire cross section shrinks, Joule heating in wires increases due to the increasing

current density. Due to the two components mentioned above, the resistivity of intercon-

nects will keep increasing with scaling which aggravates the problem of Joule heating. Due

to the temperature increase, the resistance of wires increases further. This problem cannot

simply be solved by having wider wires because it will lead to an increase in the number

of interconnect layers and also increase complexity of design. Therefore, we can see that

conventional 2-D ICs will face serious limitations in the future due to interconnects.

2.2.3 3-D IC Architecture

In a 3-D architecture, a 2-D circuit is divided into many logic and memory blocks. As

shown in fig. 2.2 they are arranged in multiple stacked layers of Si. Each Si layer can


Figure 2.2: Schematic of a 3-D IC showing devices on separate Silayers and VILICs. Source: Derived from Fig. 11 inBanerjeeet al.[3].

have its own interconnect layers and the connections between different layers are made by

VILICs. This 3-D structure offers flexibility in system design and interconnect routing. The

blocks on critical paths can be rearranged into different layers so that RC delay is reduced.

Using this method, some long, global interconnects can be converted to short VILICs to

reduce the negative impact of scaling on interconnect performance.

3-D ICs also offers the possibility of building an SoC with heterogeneous technolo-

gies arranged on different Si layers as illustrated in fig. 2.3. Conventional 2-D SoC chips

2.3 : Performance Comparison of 2-D and 3-D ICs 9

Figure 2.3: Schematic of 3-D IC with heterogeneous technologies ondifferent layers. Source: Derived from Fig. 12 inBanerjeeet al.[3].

will face limitations arising from noise due to interference between analog and digital cir-

cuits [10] as well as from increasing delays and power dissipation due to long wires con-

necting different circuit blocks. Using a 3-D architecture can alleviate these problems by

reducing interconnect lengths (by using VILICs) and by isolating different technologies.

2.3 Performance Comparison of 2-D and 3-D ICs

As seen in the previous section, 3-D ICs can be made by putting some circuit blocks on

a separate Si layers and connecting two or more layers with VILICs. Depending on the


configuration this can result in different advantages in chip performance. It is assumed that

wire width is half of the pitch.

1. Due to VILICs, the 3-D architecture reduces the number of long wires as well as the

total wiring requirement. Fig. 2.4 shows wire length distributions of 2-D and 3-D ICs

which have the same number of gates. The interconnect density functioni(l) shown

in Fig. 2.4 indicates the number of wires of lengthl. Herel is expressed in terms of

gate pitches. The cumulative interconnect density functionI(l) shown below gives

the number of interconnects with lengths equal to or less thanl.

I(l) =

∫ l

1

i(x)dx (2.4)

LSemi-global and LLocal are the lengths of the longest wires on semi-global and local

tiers respectively.

2. If the operating frequency of the chip is to be kept the same, then the area of a

3-D chip optimized for wiring pitches and total wiring length, with two Si layers

is smaller than conventional 2-D chip. This reduction in area results from reduced

global/semi-global pitch and reduced wiring requirement. In the example shown in

fig. 2.5, the 3-D chip has gates equally divided between two Si layers. The optimum

3-D chip has 35% smaller area than 2-D for operating frequency of 3 GHz [3].

3. In addition to a reduction in area, interconnect delays can be reduced by increasing

the pitch of global/semi-global wires. Increasing the pitch reduces resistance as well

as line-to-line capacitance. In fig. 2.6, a 2-D chip with operating frequency of 3 GHz

is compared with 3-D chip with increasing semi-global pitch. It can be noticed that

optimum 3-D chip area increases with operating frequency but it remains less than

that of 2-D case even when the frequency for 3-D is 4 GHz.

2.4 : Realizing 3-D ICs 11

Figure 2.4: Wire length distributions for 2-D and 3-D ICs. Source:Banerjeeet al.[3].

4. Using simulations, van Hijningenet al.[10] have shown two orders of magnitude

reduction in noise when a mixed signal chip is converted from 2-D to 3-D.

2.4 Realizing 3-D ICs

So far we have seen that a 3-D architecture promises to alleviate interconnect problems

that are going to be faced by conventional 2-D IC technology. Now we discuss methods for

fabricating these structures. If a 3-D IC is to be built layer by layer, the maximum process

temperature must be limited in order to preserve prefabricated device/interconnect layers.

This limitation of temperature arises from at least three components: (a) interconnect met-

als such as Al can melt or react with other materials and those like Cu can diffuse through

barriers and eventually reach device regions where they will cause traps, (b) the interlayer


Figure 2.5: Wire limited chip area as a function of semi-global pitch for3-D chip. Operating frequency is 3 GHz. Source:Banerjeeet al.[3].

dielectrics and gate dielectrics may fail, and (c) the dopants in already fabricated devices

may diffuse excessively causing punchthroughs or deeper junctions. The maximum allow-

able temperature will be different based on the materials used during fabrication. An 8 nm

thick TaN barrier has been shown to be good enough to prevent Cu diffusion for 30 minutes

during a 600C anneal [11] and approximately 64 hours during a 450C anneal [12]. The

interlayer dielectric can be stable for temperatures of 400C or higher [13] depending on

the material used while high-κ gate dielectrics such as HfO2 have been shown to be stable

up to 600C [14, 15]. Dopant diffusion in Si will typically occur at temperatures exceed-

ing 600C. So a good process for building devices for 3-D ICs should have a maximum

temperature close to 500C or even lower.


Figure 2.6: Comparison of 2-D and 3-D ICs with respect to operatingfrequency. Source: Banerjeeet al.[3].

2.4.1 Si Recrystallization with Laser Beams

During the early 1980’s several research groups [16–21] fabricated 3-D IC structures in

polycrystalline silicon (poly-Si) layers which was recrystallized using laser beams. Cir-

cuits, especially for imaging and A/D conversion were reported. Laser beam crystalliza-

tion works by melting Si locally and regrowing crystals but it is a serial process and takes

a long time. Also, the laser process raises the temperature of the chip so there is a risk

of damaging the lower layers of devices. Many of the reports cited above used a layer of

poly-Si to prevent damage from heating and some of them also used WSix based intercon-

nects for thermal stability. Since current ICs are using Cu interconnects, heating due to a


laser is likely to be unacceptable and also adding a poly-Si buffer will complicate process-

ing. Also, there can be grain boundaries in devices which can lead to statistical variation

in device properties [22]. This variation results from the number as well as position of

grain boundaries in the channel, especially when the grain size is comparable to transistor

dimensions [23].

2.4.2 Wafer Bonding

In wafer bonding, full circuits with interconnects are fabricated in different Si substrates.

Then a fewµm thick surface layer containing devices from one of the wafers is separated

from the bulk and bonded to the second wafer. This way high quality transistors can be

obtained for both Si layers and high performance can be expected. However, alignment

accuracy with which the two chips are bonded may be a problem. In a wire pitch limited

chip, one cannot afford to waste too much space in order to allow for alignment errors.

Recently, applications related to imaging were reported using wafer bonded 3-D ICs [24,

25].

2.4.3 Epitaxial Regrowth from Substrate

In this method, after one device layer is complete, an insulator like SiO2 is deposited and

trenches are made which reach the Si substrate. Using selective epitaxy, Si is epitaxially

grown starting from the trench and continuing laterally in adjacent areas over the oxide

where devices are built [26]. The epitaxy conditions are such that Si does not deposit on

the oxide. While epitaxial regrowth yields good crystal quality, the temperatures needed

are often close to 900C which is much higher than acceptable for interconnects. As a

result, it may be used only for chips where there are no interconnects between the two Si

layers and is therefore limited in its application. An illustration of epitaxial regrowth is


SiO

c−Si Substrate

Selective EpitaxialGrowth of Si

2

c−Si IslandSi Seed forNext SEG Layer

c−Si Substrate

AfterCMP

Figure 2.7: Epitaxial lateral overgrowth for 3-D IC.

shown in fig. 2.7.

2.4.4 Seeded Crystallization of Silicon

In seeded crystallization, the idea is to build the circuit layer by layer. So after the first

device layer is complete, the Si film is deposited in amorphous form. Using crystallization

agents like Ge [27] or Ni [28] to reduce the crystallization temperature, poly-Si is obtained

in desired areas and devices are made followed by their own interconnect layers and VIL-

ICs. This process can be repeated to build further layers of devices. The main problem is


that the device quality is not as good as in bulk-Si devices. However, for chips like micro-

processors which are limited by wires, only a small fraction of the chip area is occupied

by devices. So in the upper layers, it is possible to use bigger devices for more current and

place them without increasing the wiring pitch and hence the chip area. The devices in the

upper layer have potential applications like repeaters for long interconnects. If the repeaters

are instead placed in the lowermost layer, interconnects to which they are connected must

be brought down to the lowermost layer. This will cause obstacles for the intermediate lay-

ers and reduce their density. As a result of the reduced density, the chip area will increase

in order to accommodate all the wires.

For building a true 3-D IC architecture, reduction in processing temperature is abso-

lutely necessary. High temperatures can cause problems such as interconnect melting,

diffusion of metals like Cu through barriers into devices, instability of low-κ or high-κ

materials etc. High temperatures can also ruin devices in the lower Si layers due to excess

diffusion of dopants. So the maximum process temperature should be limited to approxi-

mately 500C. This limit is somewhat arbitrary and a lower limit will work better.

Due to the advantages of seeded crystallization like low temperature, the ability to

achieve good alignment for devices in different layers and the flexibility it offers in terms

of placement of devices, seeded crystallization of silicon can be used in order to fabricate

transistors with low processing temperatures.

2.5 Low Temperature Crystallization of Silicon

In order to fabricate MOS devices at low temperatures in the upper layers of a circuit,

silicon needs to be deposited and crystallized at low temperatures. Polysilicon deposition

usually occurs at high temperature (≥ 550 C) and results in rough films. Therefore, it is

preferable to deposit Si in amorphous form and crystallize it. Two important methods for

2.6 : Ge Seeding 17

crystallization are solid phase crystallization and seeded crystallization. In thermal solid

phase crystallization (SPC),α-Si is annealed in a furnace and the film is crystallized with

processes of nucleation and crystal growth. Using this method, the crystal size obtained is

roughly on the order of the Si film thickness. The nuclei usually form first at the interface

of theα-Si film and the substrate and dominate crystal growth.

Large crystals can be obtained if unwanted nucleation is kept at a minimum during

crystal growth. Fortunately, for silicon, the nucleation activation energy is higher than the

crystallization energy. In other words, a high temperature is needed to form nuclei while

a lower temperature is sufficient to cause their growth into a crystal. So keeping a low

number of nuclei during a low temperature anneal allows crystal growth but suppresses

additional homogeneous nucleation and nucleation at theα-Si/substrate interface. External

agents like Ge or metals can be used to cause nucleation at controlled locations using low

temperature. This process is known as seeding.

2.6 Ge Seeding

In an attempt to reduce nucleation temperature and achieve control of nuclei locations,

Subramanianet al.[27, 29] introduced Ge seeding.α-Si films were deposited at 500C on

an insulating substrate. Oxide was deposited as a mask and seeding holes were opened. Ge

was deposited in these seeding holes using selective LPCVD. The films were annealed at

550C to form nuclei in the seeding holes. After this, the crystallization was continued at

500C. Thin Film Transistors (TFTs) fabricated in these seeded poly-Si films were shown

to have good I-V characteristics. However, temperatures used in the process were still

higher than desired.


2.7 Metal Induced Crystallization

In MIC of α-Si, certain metals are used to lower the crystallization temperature below what

would otherwise be required. In 1970, Bosnellet al.[30] observed MIC ofα-Si at 180C.

Since then many researchers have reported crystallization ofα-Si with Al, Au and Ag. All

of these metals form a eutectic with Si. Liuet al.[31] reported selective area crystallization

of α-Si with Pd. In their experiment,α-Si was deposited on top of a thin and discontinuous

Pd layer. Pd2Si formed where Pd and Si came in contact andα-Si started crystallizing

using the Pd2Si template. In 1987, Cammarataet al.[32] implantedα-Si films with Ni and

annealed them at 400C. They observed that octahedral precipitates of NiSi2 formed inside

the film.

In 1992, Hayzeldenet al.[33] formed NiSi2 by a Ni implant and 400C anneal. Upon

further annealing of films at 500C, they observed a silicide mediated phase transforma-

tion of amorphous to crystalline silicon (c-Si). NiSi2 precipitates migrated through the

α-Si leaving a trail of c-Si and growth occurred parallel to the〈111〉 direction. The crys-

tals obtained with this method were long along the direction of growth but quite narrow

in directions perpendicular to it. This was the first observation of MILC. Following this

observation, Leeet al.[34] started crystallization ofα-Si using a patterned thin film of Pd

on top. At 500C, crystals started growing from the edges of the Pd pattern. The crystals

were tens of microns long and about a micron wide. Similar to Ni MILC observations, the

growth direction was〈111〉. MILC using Co has been reported by Parket al.[35].

A summary of various MIC experiments from previous research is given in Table 2.1

2.8 : Dopant Activation 19

Table 2.1: A Summary of Metal Induced Crystallization observations.Source: Obtained in part from Konnoet al.[36].

System Crystallization Analysis Referencetemperature (C) technique

α-Si/Al 180 ED [30]325–350 RBS [37]

355 P-TEM [38]200 C-TEM [39]157 P-TEM,AES [40, 41]167 C-TEM [42]

180–220 C-TEM,DSC,XRD [43]α-Si/Ag 300 ED [30]

540 P-TEM [38]400 RBS [44–46]410 DSC,C-TEM [36]

α-Si/Au 100 ED [30]68–124 P-TEM [47]

250 P-TEM [48]175 P-TEM [49]

α-Si/In 535 P-TEM [50]α-Si/Ni 500–600 P-TEM [33, 51]α-Si/Co 500 P-TEM [35]α-Si/Pd 500–700 P-TEM [31]

2.8 Dopant Activation

Dopant activation is an important component of CMOS fabrication processes. In order to

obtain high on-currents, it is important to have good dopant activation in the source/drain

as well as the channel. Conventional methods of dopant activation in Si typically require

temperatures in excess of 800C. For a low temperature CMOS fabrication process, the

temperature at which this activation takes place is limited and poses a significant challenge.


Dopant activation during MILC was first demonstrated by Leeet al.[52]. They doped

α-Si films with varying doses of phosphorus ion implants and then used Ni to crystallize

theα-Si. It was observed that approximately 10% of the dopant atoms were activated at

500 C upon annealing for 5 hours. Additionally, the sheet resistivity dropped as a larger

and larger fraction of the Si film became crystalline. They used this dopant activation in

the channel as well as gate electrode of a TFT.

2.9 Fabrication of MOS Transistor with MIC

MILC provides two key components viz. crystallization and dopant activation, for MOS

transistor fabrication at low (≤ 500 C) temperature. Putting these two factors together

gives a good MOS TFT but in order to improve further, more work was needed. This is

where a significant part of this thesis comes in. Based on a TEM study of crystal growth in

MILC, transistor design was improved to gain performance.

In a typical TFT (shown schematically in fig. 2.8), poly-Si is deposited over a glass

substrate at temperatures lower than 600C and a MOS transistor is fabricated in this Si

layer. The doping is done by ion implantation and processing steps like dopant activation

are completed at or below 600C so that the substrate is not damaged. A typical application

of TFTs has been active matrix liquid crystal displays (AMLCD). However, good quality

thin film CMOS device have potential application in 3-D ICs as well.

In 1993, Liu et al.[53] deposited thinα-Si films on a layer of Pd and crystallized it

using Pd induced crystallization [31]. For the first time, transistors were built in this layer

of MIC Si. However, in these devices, Pd was present all over the film and since Pd was

the lowermost layer, there was a possibility of source/drain shorts within a device as well

as between different devices. So this method had to be improved. Leeet al.[34] used Pd

induced lateral crystallization to crystallizeα-Si thin films and fabricated a TFT for the first

2.10 : Summary 21

DrainSource

Substrate

Channel

Gate

Gate Oxide

Figure 2.8: Simplified schematic cross section of TFT. Interlayer oxideand metal are not shown.

time using MILC. Later on TFTs were reported with MILC using Ni [28, 54] and Co [35].

Wanget al.[55] used Ni-MILC at 560C which yielded poly-Si film with a grain length

of about 1µm and a width smaller than 1µm. Then they annealed the samples at 900C in

order to increase the crystal size to about 10µm in length as well as width. The quality of

c-Si also improved due to the 900C annealing. Transistors fabricated in this film showed

performance close to that of SOI transistors of similar dimensions.

2.10 Summary

In this chapter, we gave a brief introduction to 3-D ICs and their relevance to IC technology

as transistor scaling progresses aggressively. An overview of different technologies which

are used to make devices for 3-D ICs was presented. Metal induced crystallization is a

promising technology for 3-D IC, with an advantage of low temperature of fabrication. In

the following chapter, a model for estimating crystal growth with MILC will be presented

in detail along with a theory for the MIC process.

Chapter 3

A Model for Crystal Growth during

Metal Induced Lateral Crystallization of

Amorphous Silicon

3.1 Introduction

Amorphous silicon has a higher free energy than crystalline silicon. As a result,α-Si

will be converted to more stable c-Si or poly-Si upon annealing. This is the driving force

behind the crystallization ofα-Si. Upon annealingα-Si, small organized clusters of atoms

known as nuclei start forming. This process is known as nucleation. The nuclei can grow

into crystals upon further annealing. In silicon, the activation energy for nucleation is

larger than that for crystallization. If low temperature annealing is used for crystal growth,

nucleation can be kept low and crystal growth can be started from the existing nuclei.

Since number of nuclei is small, large grains of c-Si can be obtained. For metals like Au

or Ag which form a eutectic with Si, the mechanism of crystallization involves lowering

22

3.1 : Introduction 23

the nucleation activation energy. The metal atoms weaken the bonds in Si and makeα-Si

more unstable [42]. As a result, its conversion to poly-Si or c-Si is more favorable. So

with the use of metals, heterogeneous nuclei can be formed at low temperature where the

homogeneous nucleation rate is small. These nuclei can then be grown into crystals at a

low temperature without significant increase in nucleation. In addition to increasing grain

size, it is also important to start nucleation at controlled locations. So a seeding agent like

Ge, Al or Au should be limited to certain areas of device like contact holes.

Metals which form silicides such as Ni, Co or Pd also cause a reduction of the crys-

tallization temperature. The silicide acts as a medium for the transport of atoms. Using

a system ofα-Si/Pd2Si/c-Si, Tuet al.[56] showed that dissociation of Pd2Si occurs at its

interface with c-Si and Pd diffuses through Pd2Si towardsα-Si. A similar mechanism was

suggested by Hayzeldenet al.[51] for NiSi2 mediated growth.

Kawazuet al.[57] suggested that at least in the case of Ni, the silicide which forms on

α-Si acts as a nucleus for Si crystallization. The lattice constants of different silicides are

indicated in Table 3.1. Growth of c-Si can occur using the silicide as a template. It can

be seen that Pd2Si does not have a good lattice match with silicon but Pd still enhances

crystallization. NiSi2 has a 0.4% and CoSi2 has a 1.2% lattice mismatch compared to c-Si.

So NiSi2 will be the best template for MILC and will yield the best quality of c-Si. After

inital work in Pd, almost all recent reports on MILC have used Ni.

The exact driving force behind MILC is not clear. Using the free energy diagram for a

mixture of Ni and Si shown in Fig. 3.1, Hayzeldenet al.[51] suggested that the chemical

potential of Ni is lower at the NiSi2/α-Si interface, whereas the chemical potential of Si

atoms is lower at the NiSi2/c-Si interface. So there is a driving force for Ni to move toward

α-Si to reduce its free energy. This Ni moving forward in turn reacts withα-Si to form new

NiSi2 and the process repeats. The Si atoms remaining behind attach to the NiSi2 template

to form c-Si since their chemical potential is lower at the NiSi2/c-Si interface.

24 Chapter 3 : A Model for Crystal Growth during MILC

Table 3.1: Lattice constants of some silicides.

Silicide Structure Latticeconstant (A)

CoSi2 Fluorite 5.364NiSi2 Fluorite 5.406Pd2Si Hexagonal 6.493

Si Diamond 5.430

0 20 40 60 80 100

Mol

ar F

ree

Ene

rgy

Percentage of Si(in Ni/Si Mixture)

← µNiNiSi2/c-Si

← µNiNiSi2/α-Si

µSiNiSi2/α-Si

µSiNiSi2/c-Si

(Ni) (Si)

NiSi2

Figure 3.1: Molar free energy of a mixture of Ni and Si. Ni has a lowerfree energy at the NiSi2/α-Si interface while Si has a lowerfree energy at the NiSi2/c-Si interface. Source: Derivedfrom Fig. 14 in Hayzeldenet al.[51].


[111][100] [110]

α−Si

NiSi Precipitates2

Figure 3.2: Schematic diagram showing NiSi2 precipitate orientationsfavorable (〈110〉) and unfavorable (〈100〉, 〈111〉) for MILC.The〈100〉 and〈111〉 oriented precipitates have normalswhich will intersect either the top or bottom surface.Source: Derived from Fig. 12 in Hayzeldenet al.[51].

Hayzeldenet al.[51] showed that octahedral NiSi2 precipitates form after Ni implanta-

tion in α-Si film and annealing at 400C for 3 hours. Upon further annealing at 500C,

c-Si nucleates on one or more faces of the octahedral NiSi2. Migration of these NiSi2 pre-

cipitates leads to growth of needles of c-Si which are parallel to〈111〉 directions. Fig. 3.2

shows NiSi2 precipitates oriented in〈100〉, 〈110〉 and〈111〉 in anα-Si film bounded only

by upper and lower surfaces. The shaded area in each represents the face on which MILC

starts and the arrow indicates the normal to the face which is also the direction along which

crystal growth takes place. So it can be seen that for the〈100〉 and 〈111〉 oriented pre-

cipitates, all of the face normals are such that crystal growth which starts on them will be

stopped soon because of either the upper or lower surface of the film. However, the〈110〉

oriented precipitate will have a better chance of causing extensive c-Si growth because four

of the111 planes exhibit normals within the plane of film.

The observations by Hayzeldenet al.[51] showed that c-Si needles often fan out with


a consequent reduction in NiSi2 thickness and increase in growth velocity. They showed

that the growth velocity is inversely proportional to the NiSi2 thickness which agrees with

diffusion limited growth. However, observations by Jinet al.[58] showed that the MILC

rate decreases with time which apparently does not match with diffusion-limited growth.

In this chapter we present a model to predict MILC crystal growth as a function of time. It

also reconciles the two observations by Hayzeldenet al.and Jinet al.

For 3-D integrated circuits where the thermal budget and maximum process temperature

are constrained to keep underlying interconnects and devices intact, this model will be

helpful in choosing a proper annealing temperature and time. If the maximum length of

transistors to be fabricated is known, the crystallization length need not exceed that length

and the time required for MILC can be calculated with the model.

In a typical MILC process used for making TFTs,α-Si is deposited on SiO2 surface

and covered with SiO2 deposited at a low temperature. After gate electrode deposition and

definition, a low temperature oxide is deposited as an interlayer dielectric. Contact holes

are opened over the source/drain and Ni is deposited. Upon annealing at a temperature

close to 400C, NiSi2 forms in the contact holes. Ni induced crystallization occurs when

theα-Si film is annealed at 500C as part of the original NiSi2 moves towardα-Si in the

channel leaving behind a trail of c-Si. While the NiSi2 front moves intoα-Si, about 0.02

atomic % Ni is left behind in the crystallized silicon [59].

3.2 Relation between MILC Growth Rate and NiSi2

Thinning Rate

The shape of crystals observed by Hayzeldenet al.[51] and Jinet al.[58] is needle-like.

Hayzeldenet al. made observations on isolated crystals of Si obtained with MILC where

3.2 : Relation between MILC Growth Rate and NiSi2 Thinning Rate 27

X

Y

Line of Ni

Needle−like Crystals

MILC Front

Figure 3.3: Illustration of MILC starting from a long line of Ni.

the growth can be essentially considered 1-D. In samples considered by Jinet al., when

MILC starts from a Ni covered region, Ni will go downward as well as sideways. Since

the sample is a thin film ofα-Si, we can ignore the downward movement of Ni. That

leaves us two dimensions to consider in the plane of the film. The lateral growth starts

out from a line of Ni with many needle-like crystals growing side by side and continues

uniformly into surroundingα-Si regions. As illustrated in Fig. 3.3 the resultant MILC front

is a straight line parallel to the starting line of Ni. Since there is no variation in the direction

perpendicular to crystal growth, we are again left with the 1-D case.

For simplifying calculations, throughout this model we have assumed that the initial

NiSi2 in the contact holes has been removed after a short anneal at a temperature close to

500 C. This short annealing will move the NiSi2 front away from the contact hole. With


ΓL1

NiSi2

2c−Siα

t

−SiΓ

t1 2

Figure 3.4: Schematic diagram showing 1-D NiSi2 mediatedcrystallization ofα-Si.

the initial NiSi2 removed, the Ni concentration in the c-Si region (Cc-Si) comes entirely from

the NiSi2 front. Therefore,

Cc-Si = 2× 10−4 × 5× 1022 = 1× 1019/cm3 (3.1)

Assume that the NiSi2 layer is of thicknessΓ1 at time t1 which has moved a distanceL

and has thicknessΓ2 at timet2 as shown in Fig. 3.4. The concentration of Ni (CNiSi2)in the

NiSi2 layer is approximately,

CNiSi2 = 2.5× 1022/cm3 (3.2)

Since theCc-Si in newly crystallized region of lengthL must come from the portion of

3.2 : Relation between MILC Growth Rate and NiSi2 Thinning Rate 29

NiSi2 front which was lost,

(Γ1 − Γ2)CNiSi2 = LCc-Si (3.3)

This equation also gives us the maximum crystal growth,Lmax. The maximum growth will

be reached when the NiSi2 thickness goes to zero. If we start with initial NiSi2 thickness

of Γ0 at timet = 0, Lmax is

Lmax = Γ0CNiSi2

Cc-Si(3.4)

For convenience, we defineη as the ratio of Ni concentration in NiSi2 and that in newly

formed c-Si.

η =CNiSi2

Cc-Si(3.5)

From Wonget al.[59], c-Si left behind is 0.02 atomic % (Cc-Si ≈ 1× 1019/cm3). In this

caseη is close to 2500. However, variation is possible in this value since it is derived using

a rough estimate of Ni concentration in c-Si. Another variable in the determination ofη is

the sample preparation and the condition in which crystal growth is carried out. To get a

feel for someLmax values, we can assumeΓ0 to be 10 nm which givesLmax value of 25µm.

This is about a factor of 2 smaller than the observed MILC length in Jinet al.[58]. So we

will adopt a value of 5000 for all calculations to get better estimates of crystal length and

growth rate.

Differentiating equation (3.3) with respect to time gives

−dΓ

dtCNiSi2 =

dL

dtCc-Si (3.6)

Denoting the growth rate byν, we rewrite the equation above as

ν = −dΓ

dt

CNiSi2

Cc-Si= −η

dΓ

dt≈ −5× 103 dΓ

dt(3.7)


From experimental observations [51, 58],ν ≈ 1 µm/hr so thatdΓ/dt ≈ −0.2 nm/hr which

makes sense given that the NiSi2 layer is a few nm thick.

Equations (3.3)–(3.7) apply regardless of the mechanism of c-Si growth but they are

not enough to predict how far the crystals will grow at a timet. In order to do that, we

need to consider how Ni atoms are moving and what is the growth limiting process. We

propose that the migration of the NiSi2 front in α-Si has two regimes depending on its

thickness. The first regime is diffusion limited growth when NiSi2 is thick at the beginning.

The second regime is reaction limited growth where the reaction of Ni andα-Si forms new

NiSi2. Both of these regimes are considered in separate sections that follow.

3.3 Diffusion Limited Regime

When the c-Si begins to grow behind the moving NiSi2 precipitate, it has been observed that

in the initial period of growth, the rate of growth is inversely proportional to the thickness

of the NiSi2 layer, which suggests a diffusion limited growth regime [51]. In this regime,

growth is limited by the diffusion flux of Ni and whatever amount of Ni reaches theα-Si,

reacts with it. We start by assuming the diffusivity,D, of Ni in NiSi2, a concentration

difference,∆C (= Cback−Cfront), between the back and front surfaces of the NiSi2 front as

shown in Fig. 3.5. It is also assumed thatD and∆C are constant during the process. With

a thickness of NiSi2 layer,Γ, the diffusion flux is

F1 =D∆C

Γ(3.8)

3.3 : Diffusion Limited Regime 31

NiSi2

∆C

Γ

α−Si c−Si

C c−Si

CC front

back

Cα −Si

C NiSi2

Figure 3.5: Diagram showing Ni concentrations in different regionsduring MILC.

This flux is responsible for the growth of new NiSi2 near theα-Si interface. IfN (=

2.5× 1022/cm3) is the number of Ni atoms needed to grow a unit volume of NiSi2 andν is

the crystal growth rate, we can write

F1 =D∆C

Γ= Nν = −Nη

dΓ

dt(3.9)

−D∆C

Nηdt = ΓdΓ (3.10)


Integration of equation (3.10) with respect to time gives

Γ(t) =

√2D∆C

Nη(τ0 − t) (3.11)

where,

τ0 =Γ2

0Nη

2D∆C(3.12)

Therefore, the crystal growth rate is

ν(t) = −ηdΓ

dt=

√D∆Cη

2N(τ0 − t)(3.13)

The growth at timet can be estimated by integratingν with time and usingΓ(0) = Γ0.

L(t) =

∫ t

0ν(t) dt = −η

∫ Γ(t)

Γ(0)

dΓ = η (Γ0 − Γ(t)) = ηΓ0

(1−

√1− t

τ0

)(3.14)

We can put some numbers in the equation above and see howL(t) behaves. Hayzeldenet

al. [51] have calculated the effective diffusivity (= D∆C/N ) to be 2.5× 10−14 cm2/s at

507 C. In another study by Hayzeldenet al.[33], the initial NiSi2 precipitate thickness

was 10 nm att = 0. Also Jinet al.[58] have used 5 nm thick Ni which is expected to give

close to 10–15 nm thick NiSi2. So we can assume the initial thickness to beΓ0 = 10 nm.

Therefore,

τ0 =Γ2

0Nη

2D∆C= 1× 105 s = 27.78 hr (3.15)

Γ(t) =

√2D∆C

Nη(τ0 − t) = 1× 10−6

√(1− 10−5t) cm (3.16)

ν(t) =

√D∆Cη

2N(τ0 − t)=

2.5× 10−8√(1− 10−5t)

cm/s (3.17)

3.4 : Surface Reaction Limited Regime 33

and

L(t) = ηΓ0

(1−

√1− t

τ0

)= 5× 10−3(1−

√1− 10−5t) cm (3.18)

3.4 Surface Reaction Limited Regime

As the NiSi2 layer thins down, the diffusion flux through it increases and after a point is

no longer a limiting factor. Now the growth is limited by the surface reaction between Ni

andα-Si. If the reaction rate constant isks and the Ni concentration at the interface isCα-Si

then we can write the reaction flux as

F2 = ksCα-Si = Nν (3.19)

and by expressingν in terms ofΓ,

ksCα-Si = −NηdΓ

dt(3.20)

Here we will consider two cases depending onks variation with time. In the first one,

the surface reaction rate is assumed to be constant while the second one considers it to be

exponentially decreasing with time. Another kind of time dependence may exist in which

case the equations can be solved in the same way as here. At this point it is not known

which one of these cases is physically correct. The proper choice ofks dependence on time

may depend on experimental conditions.


3.4.1 Surface Reaction Rate Unchanged with Time

Using the fluxF2,

−ksCα-Sidt = NηdΓ (3.21)

which, upon integration gives

Γ(t) =ksCα-Si

Nη(τ2 − t) (3.22)

and the growth rate (fort < τ2) as

ν =ksCα-Si

N(3.23)

Equation (3.22) indicates that the NiSi2 thickness will go to zero at a timeτ2 and crystal

growth will stop. The transition between the diffusion limited and surface reaction limited

regimes will occur at timettr when the crystal growth velocities of the two regimes match.

√D∆Cη

2N(τ0 − ttr)=

ksCα-Si

N(3.24)

ttr = τ0 −D∆Cη

2N

(ksCα-Si

N

)−2

(3.25)

Since the NiSi2 thicknesses must also match atttr,

Γ(ttr) = Γtr =

√2D∆C

Nη(τ0 − ttr) =

D∆C

N

(ksCα-Si

N

)−1

=ksCα-Si

Nη(τ2 − ttr) (3.26)

From equations (3.25) and (3.26),

τ2 = τ0 +D∆Cη

2N

(ksCα-Si

N

)−2

(3.27)

3.4 : Surface Reaction Limited Regime 35

Using equations (3.14) and (3.22), the crystal growth at timet can be calculated.

L(t) = η (Γ0 − Γ(t)) = η

(Γ0 −

D∆C

2N

(ksCα-Si

N

)−1

+ksCα-Si

Nη(t− τ0)

)(3.28)

At this point we can put some numbers in this equation and get values ofτ2, ttr and

crystal growth. From Hayzeldenet al.[51], at 507C,

D∆C

N= Γν = 2.5× 10−14 cm2/s (3.29)

and from Jinet al.[58], at 500C,

ksCα-Si

N= ν ≈ 1.5µm/hr = 4.17× 10−8 cm/s (3.30)

ttr = τ0 −D∆Cη

2N

(ksCα-Si

N

)−2

= 6.4× 104 s = 17.89 hr (3.31)

τ2 = τ0 +D∆Cη

2N

(ksCα-Si

N

)−2

= 1.36× 105 s = 37.8 hr (3.32)

Γ(t) =ksCα-Si

Nη(τ2 − t) = 1.13× 10−6(1− 7.35× 10−6t) cm (3.33)

L(t) = η (Γ0 − Γ(t)) = −6.71× 10−4 + 4.17× 10−8t cm (3.34)

Equations (3.33) and (3.34) are valid forttr < t < τ2.

3.4.2 Surface Reaction Rate Decreases with Time

Jin et al.[58] reported that the rate of MILC growth goes down significantly with an an-

nealing time of 70 hours at 500C and the primary reason they gave was rearrangement

of atoms inα-Si film. Sinceα-Si has a higher free energy than c-Si, it will convert to


more stable c-Si upon annealing. This process of conversion starts with the formation of

small clusters of atoms known as nuclei which grow into crystals on further annealing. So

the rearrangement of atoms suggested by Jinet al. can be considered as progress towards

homogeneous nucleation in the Si film. This will exponentially reduce the amount ofα-Si

available for reaction with Ni. Kosteret al.[60] indicated that the nucleation rate is ex-

ponential with time. Jinet al. also state that the rearrangement of atoms can reduce the

driving force for reaction between Ni andα-Si atoms in order to go fromα-Si to c-Si. As

far as this model is concerned, both of these effects can be included by considering aks(t)

exponentially decreasing with time.

ks(t) = ks0e−t/τ1 (3.35)

−ks0Cα-Sie−t/τ1dt = NηdΓ (3.36)

Integrating equation (3.36) gives the dependence ofΓ on time. Also considering thatΓ is

zero att = ∞,

Γ(t) =ks0Cα-Si

Nητ1e

−t/τ1 (3.37)

and growth rate is

ν(t) =ks0Cα-Si

Ne−t/τ1 (3.38)

L(t) = η (Γ0 − Γ(t)) = η

(Γ0 −

ks0Cα-Si

Nητ1e

−t/τ1

)(3.39)

When the transition occurs from diffusion limited growth to surface reaction limited

growth at timettr, the crystal length and growth velocities must match. So

√D∆Cη

2N(τ0 − ttr)=

ks0Cα-Si

Ne−ttr/τ1 (3.40)

3.5 : Combined Model for MILC Growth Estimation 37

Γ(ttr) = Γtr =

√2D∆C

Nη(τ0 − ttr) =

D∆C

N

(ks0Cα-Si

N

)−1

ettr/τ1 =ks0Cα-Si

Nητ1e

−ttr/τ1

(3.41)

Using equations (3.40) and (3.41),

τ1e−2ttr/τ1 =

D∆Cη

N

(ks0Cα-Si

N

)−2

(3.42)

τ1 = 2(τ0 − ttr) (3.43)

Starting with equations (3.29) and (3.30) we can obtain values forτ1, ttr andL(t). Solving

equations (3.42) and (3.43) iteratively,

τ1 = 1.28× 105 s = 35.56 hr (3.44)

ttr = 3.6× 104 s = 10 hr (3.45)

ν(t) =ks0Cα-Si

Ne−t/τ1 = 4.17× 10−8e−7.8×10−6t cm/s (3.46)

Γ(t) =ks0Cα-Si

Nητ1e

−t/τ1 = 1.07× 10−6e−7.8×10−6t cm (3.47)

L(t) = η(Γ0 − Γ(t)) = 5× 10−3 − 5.33× 10−3e−7.8×10−6t cm (3.48)

3.5 Combined Model for MILC Growth Estimation

The two cases discussed so far can be described by a combined model which takes into

account a certain range ofτ1 values. It can be further expanded toτ1 values not considered

earlier. In the following two subsections we describe each case.


3.5.1 Large Values ofτ 1

We start with the same equation (3.36) as before but include a negative constant of integra-

tion. So new expression ofΓ(t) is

Γ(t) =ks0Cα-Si

Nητ1e

−t/τ1 − β (3.49)

The expression for the growth rate will remain as in equation (3.38).β can be rewritten as

β =ks0Cα-Si

Nητ1e

−τ2/τ1 (3.50)

whereτ2 is the time at which the NiSi2 front thickness will go to zero and MILC will stop.

τ2 will depend onτ1 but the value has to be obtained by numerical calculations. In order to

getτ2 numerically, we make the following rearrangement of equations.

At t = ttr, NiSi2 thickness is

Γtr =D∆C

N

(ks0Cα-Si

N

)−1

ettr/τ1 =ks0Cα-Si

Nητ1(e

−ttr/τ1 − e−τ2/τ1) (3.51)

which gives

1− e−(τ2−ttr)/τ1 =D∆C

N

(ks0Cα-Si

N

)−2η

τ1e2ttr/τ1 (3.52)

From the growth rate equation (3.40), we can obtainttr and also simplify equation (3.52)

as

1− e−(τ2−ttr)/τ1 =2(τ0 − ttr)

τ1(3.53)

So

τ2 = ttr − τ1 ln

[1− 2(τ0 − ttr)

τ1

](3.54)

Γ(t) andL(t) = η(Γ0 − Γ(t)) can be obtained fromτ2.

3.5 : Combined Model for MILC Growth Estimation 39

It is easy to see that whenτ1 →∞,

τ2 = ttr − τ1

[−2(τ0 − ttr)

τ1

]= 2τ0 − ttr (3.55)

which agrees with the case of constant surface reaction rate in section 3.4.1. On the other

hand, asτ1 → 2(τ0 − ttr), τ2 → ∞ which agrees with the case of an exponentially de-

creasing surface reaction rate as discussed in section 3.4.2. So both the cases discussed in

section 3.4 are extreme cases of this general case.

3.5.2 Small Values ofτ 1

If τ1 < 2(τ0 − ttr), the earlier discussion does not apply. We have to start with equa-

tion (3.36) and use a positive constant of integration.

Γ(t) =ks0Cα-Si

Nητ1e

−t/τ1 + β (3.56)

Physically,β now represents the final thickness of NiSi2. As a result, not all of the Ni can

be used for MILC and the maximum extent of crystallization is now given by

Lmax = η(Γ0 − β) (3.57)

At t = ttr, the NiSi2 thickness is given by

Γtr =D∆C

N

(ks0Cα-Si

N

)−1

ettr/τ1 =ks0Cα-Si

Nητ1e

−ttr/τ1 + β (3.58)

β =ks0Cα-Si

Nητ1

(D∆C

N

(ks0Cα-Si

N

)−2η

τ1e2ttr/τ1 − 1

)e−ttr/τ1 (3.59)


ttr can be obtained from equation (3.40) and equation (3.59) can be simplified to

β =ks0Cα-Si

Nητ1

(2(τ0 − ttr)

τ1− 1

)e−ttr/τ1 (3.60)

Upon calculatingβ, Γ(t) andL(t) can be obtained. Asτ1 → 2(τ0 − ttr), β → 0 which

is same as theτ2 → ∞ case discussed in the section on largeτ1. At the other extreme, as

τ1 → 0, ν → 0, ttr → 0 andβ → Γ0 which means that MILC does not occur at all.

3.6 Results and Discussion

In order to see how the model compares with experimental data, the predictions of our

model in section 3.4 were plotted along with data from Jinet al.[58]. Fig. 3.6 and 3.7 show

the length of the crystallized region and MILC rate respectively at 500C as a function

of time. The transition between diffusion limited and surface reaction limited regimes is

marked by circles. Fig. 3.7 shows a diffusion limited growth regime at smaller times as

observed by Hayzeldenet al.[51]. Unfortunately, they only state that growth rate increases

with time but apart from a mention of 5A/s (1.8µm/hr) average growth rate, no details

of its increase with time were found. It can be noted that rate of 1.8µm/hr is somewhat

higher than our model predicts. This is probably due to a higher value ofη (owing to

lower levels of Ni in c-Si) in the sample. After a period of 10 to 18 hours, growth becomes

surface reaction limited. The differences between the model and experiment may have

arisen because in the experiment by Jinet al.[58], the initial NiSi2 was removed after a

3 hour anneal at 500C. This short anneal may have introduced more Ni into the c-Si region

than assumed by our model. The agreement between experimental data and exponentially

decreasing reaction rate is better than that with constant reaction rate.

3.6 : Results and Discussion 41

0

10

20

30

40

50

60

70

80

0 10 20 30 40 50 60 70 80

MIL

C L

engt

h (µ

m)

Annealing Time (hr)

Data from Jin et al. [58]

Reaction rate is constantReaction rate exponentially decreasing

Figure 3.6: Comparison of model and experimental results for MILClength.

The concept of decreasing reaction rate constant,ks, with time was adopted to con-

sider the reduction in the amount ofα-Si available for reaction with Ni due to competing

processes of nucleation and crystallization. Another factor which may contribute is the re-

duction of driving force due to atomic rearrangement inα-Si after extended annealing [58].

The model was then expanded to consider cases of differentτ1 values. Theτ1 value indi-

cates how fast homogeneous nucleation of theα-Si film is occurring or how fast the driving

force for reaction is decreasing. At any temperature there is a competition between MILC

and SPC. Forτ1 > 2(τ0−ttr), it was shown that the MILC growth will occur until all of the

Ni from the NiSi2 front is consumed. At low temperatures (about 500C or below), homo-

geneous nucleation and crystallization ofα-Si is quite slow and MILC wins against SPC.

So τ1 and the extent of crystallization,Lmax are expected to be large. Ifτ1 < 2(τ0 − ttr),


0

0.5

1

1.5

2

0 10 20 30 40 50 60 70 80

MIL

C R

ate

(µm

/hr)

Annealing Time (hr)


Reaction rate is constant

Reaction rate exponentially decreasing


Reaction rate is constantReaction rate exponentially decreasing

Regime transition point

Figure 3.7: Comparison of model and experimental results for MILCrate. The transitions between diffusion limited and surfacereaction limited regimes are marked by circles.

MILC growth will stop before all of the Ni from the NiSi2 front is consumed indicating

that SPC is getting faster. This is expected to occur at high temperatures where the ho-

mogeneous nucleation and crystallization ofα-Si is rapid. At very high temperatures,τ1

will go to zero, indicating no MILC growth. The plots in Fig. 3.8 and 3.9 show the re-

sults of numerical calculations at 500C for the combined model for small as well as large

values ofτ1. It can be seen that a reasonable match with MILC growth and MILC rate

data is obtained withτ1 = 41.7 hr. The time constant obtained by extrapolating data in

Kosteret al.[60] is about 694 hours at 500C. The discrepancy arises because the time

dependence we assumed may not be exact. The choice of time dependence found in the lit-

erature [60–62] varies with the method of Si film deposition and later processing. Also, our


0

10

20

30

40

50

60

70

80

0 10 20 30 40 50 60 70 80

MIL

C L

engt

h (µ

m)

Annealing Time (hr)

τ1 = ∞

τ1 = 41.7 hr

τ1 = 27.8 hrτ1 = 13.9 hr


Large τ1 caseSmall τ1 case

Figure 3.8: Results of numerical calculations of MILC length forcombined model.

simple model does not take into account all factors affecting nucleation and crystallization

processes as well as the presence of impurities.

The model is able to predict the results of MILC growth at 500C when the initial

supply or NiSi2 seed for MILC has been removed. Due to the lack of the data at temper-

atures other than 500C, the model could not be verified for those temperatures. It has

been assumed that the concentration difference∆C in the NiSi2 moving front remains un-

changed during diffusion limited growth and its magnitude is not known. Similarly,Cα-Si

is not known. Based on the data of Ni diffusivity in silicon [63] at 500C we can take

D ≈ 1× 10−11 cm2/s. Then we find∆C = 6.25× 1019/cm3. This excess∆C is small

compared to the amount of Ni in the NiSi2 and may be due to the segregation coefficient

between silicon and NiSi2.


0

0.5

1

1.5

2

0 10 20 30 40 50 60 70 80

MIL

C R

ate

(µm

/hr)

Annealing Time (hr)

τ1 = ∞

τ1 = 41.7 hr

τ1 = 27.8 hr

τ1 = 13.9 hr


Large τ1 caseSmall τ1 case

Regime transition point

Figure 3.9: Results of numerical calculations of MILC growth rate forthe combined model. The transitions between diffusionlimited and surface reaction limited regimes are marked bycircles.

When it comes to predicting MILC rates for the cases where the original Ni source is

not removed, this model faces difficulties explaining the higher observed growth rates [58].

However, we can suggest a qualitative explanation. Since the Ni source also supplies Ni to

the newly formed c-Si, the Ni loss from NiSi2 moving front is expected to be smaller which

will give us a higher value ofη. Another reason may be that due to an additional flux of Ni

from the original Ni source, levels of Ni concentrationCα-Si, Cc-Si, Cback andCfront may all

rise and provide an increased Ni flux for reaction withα-Si.

3.7 : Summary 45

3.7 Summary

We have proposed a comprehensive, physical model for predicting MILC growth as a func-

tion of time with the initial Ni seed removed and compared with experimental data. This

model incorporates competition between MILC and SPC through a time-varying reaction

rate constant.

L(t) obtained from the case of a surface reaction rate decreasing exponentially has a

better match with the experimental data than the constant reaction rate case. As long as

the surface reaction rate is decreasing slowly (largeτ1), MILC will dominate and with the

initial NiSi2 removed, the maximum MILC growth is going to be the same regardless of

the surface reaction rate. However, the time needed to reach the final growth will depend

on surface reaction rate. If the surface reaction rate is decreasing rapidly (smallτ1), as it

is typically at high temperatures due to homogeneous nucleation, MILC does not achieve

its maximum growth. Since the model enables us to find outL(t), the time and the ther-

mal budget for a crystallization anneal can be estimated based on the dimensions of the

transistor to be fabricated.

In the next chapter, we will describe experiments for the study of dopant activation

and crystal growth during the MIC process. Understanding of both of these processes is

important for good quality CMOS devices.

Chapter 4

Crystallization and Dopant Activation

with Metal Induced Crystallization

4.1 Introduction

The presence of grain boundaries in MOS transistor channels can cause the following ef-

fects (a) reduction in on-current, (b) degradation of subthreshold slope, and (c) an increase

in leakage current. All of these are illustrated in fig. 4.1. As the number of grain bound-

aries increased from 0 to 1 or more, the on-current of the device shown in fig. 4.1 reduced

by more than a factor of 10 and the subthreshold slope decreased. Also, for more than 4

grain boundaries, the leakage current increased. For fabricating a good CMOS transistor,

therefore, grain boundaries inside the transistor channel need to be avoided. This means

that the method of crystallization used should yield large grains of Si. Since MILC occurs

at low temperatures there is a possibility that large crystals can be obtained without causing

excess homogeneous nucleation. In this chapter, we are going to study different methods

for starting MILC and see which method is better for eliminating the grain boundaries from

46


Figure 4.1: Effects of grain boundaries on transistor performance.Source: Subramanianet al.[29]

the channel.

Dopant activation is crucial for obtaining high performance transistors. Since series

resistance in transistors is one of the major hurdles in improving drive current, demands

on dopant activation to obtain low sheet resistance and contact resistivity will be more

severe as scaling continues more or less as predicted by ITRS [1]. Conventional thermal

activation of dopant requires high temperatures. Using MIC for dopant activation is one of

the ways to achieve dopant activation at low temperature [52, 64] where it is a byproduct of

crystallization. Here we present a comparison of nickel induced dopant activation and high

temperature activation along with some thought on the mechanism of activation during the

MIC process.

48 Chapter 4 : Crystallization and Dopant Activation with MIC

4.2 Experimental Details

4.2.1 Dopant Activation

For our dopant activation experiments, about 350 nm thickα-Si layers were deposited on

thermally oxidized Si wafers using silane LPCVD at 500C. Some films were implanted

with boron (32 keV, 2×1015 /cm2 + 80 keV, 2×1015 /cm2), some with phosphorus (70 keV,

2× 1015 /cm2 + 160 keV, 3× 1015 /cm2) and others were left undoped. 25 nm thick nickel

was sputter deposited on one film of each kind and annealed at 400C for 4 hours in N2 to

form nickel silicide. After the unreacted nickel was removed by etching in H2SO4+H2O2,

the samples were annealed at 450C for 24 hours in N2 to crystallize theα-Si film and

activate the dopant. Fig. 4.2 shows the schematic cross section of the samples. These

samples were analyzed with the spreading resistance measurement technique as a function

of depth inside the samples. Some wafers without Ni which had the same dopant implants

were annealed in an N2 ambient at 800C for 2 hours. They served as the control samples

for comparison.

4.2.2 TEM Study of Crystal Growth During MILC

Samples for plan view TEM of wide areaα-Si films crystallized with Ni-MILC were pre-

pared in order to study the grain size. 1µm SiO2 was grown on Si wafers and 100 nm thick

α-Si was deposited on it using LPCVD at 500C. After coating the wafers with photore-

sist, long seeding holes were opened photolithographically. 5 nm thick Ni was deposited

and patterned using photoresist liftoff. The wafers were annealed at 500C for 24 hours in

N2+H2 and diced in 3 mm×3 mm pieces. These pieces were immersed in concentrated HF

to dissolve the 1µm thermal oxide. After the oxide etching, portions of the Si films floated

to the surface of the HF. After diluting the HF with large amounts of water, the floating Si

4.2 : Experimental Details 49

α

Thermal SiO

c−Si Substrate

2

−Silicon FilmBefore Annealing

Nickel Layer

Silicon Atom

Dopant Atom

450 C Anneal

2

c−Si Substrate

Thermal SiO

α−Silicon Crystallized

Grains

and Activated with Nickel

Figure 4.2: Schematic of dopant activation experiment.

films were captured with a copper grid for mounting in TEM sample holders for plan-view

observation.

A study of crystal growth during the MILC process in submicron features was per-

formed using the cross-section TEM sample preparation method developed by Choet

al. [65]. Similar to our transistor structure, 1µm SiO2 was grown over Si substrates and

100 nm thickα-Si films were deposited by LPCVD. A layer of low temperature oxide

(LTO) was deposited and seeding holes were opened. 25 nm Ni was deposited and the

wafers were annealed at 400C to form the silicide. After wet etching of unreacted Ni,

100 µm long and 140 nm wide lines were patterned with electron beam lithography be-

tween seeding holes. Using plasma etching, mesas of 0.4µm height were formed in order

to facilitate side-view TEM observation of crystal growth. After mesa formation, samples

were annealed at 500C for 24 hours in N2+H2 to crystallize the lines ofα-Si with MILC.



4.3.1 Dopant Activation Results with Spreading Resistance Analysis

Dopant activation at 800C without Ni and at 450C with Ni was compared. Fig. 4.3 shows

the resistivity measured by spreading resistance analysis as a function of depth inside the

crystallized poly-Si film. There are seven curves shown in the figure. Three of them are for

phosphorus doped films, three for boron doped films and one for an undoped film. It can

be noticed that for doped samples, the poly-Si resistivities are similar for 800C 2 hour

anneal without Ni and 450C 24 hour anneal with Ni. Samples without Ni show 6 orders

of magnitude higher resistivity than samples with Ni for the same 450C 24 hour anneal.

The Ni-crystallized undoped film also shows 6 orders of magnitude higher resistivity than

Ni-crystallized doped films after 450C 24 hour anneal. This shows that Ni is activating

dopants and the difference between resistivities of Ni-crystallized undoped and doped films

is caused by dopant activation.

The dopant activation during MIC is related to the crystallization process which is simi-

lar to the dopant activation which occurs during pure thermal SPC. We have already seen in

Chapter 3 that MIC occurs as a result of Ni moving towardsα-Si in order to reduce the free

energy and Si atoms fromα-Si attach to the NiSi2 template. While this process is going

on, dopant atoms can get placed on lattice sites and therefore get activated.

4.3.2 TEM Results for MILC

Top-view TEM images of MILC structures for wide areaα-Si are shown in fig. 4.4(a). The

crystal growth started from the bottom part of figure and theα-Si/poly-Si boundary is near

the top. It can be seen that some of the crystals are over 2µm wide but many are narrower

than 1µm. Near the starting point of MILC, the average width of grains was estimated


10-4

10-3

10-2

10-1

100

101

102

103

104

105

106

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4

Res

istiv

ity (

Ω-c

m)

Depth Inside Poly-Si Film (µm)

B-doped, no Ni (450°C)P-doped, no Ni (450°C)B-doped, with Ni (450°C)P-doped, with Ni (450°C)B-doped, no Ni (800°C)P-doped, no Ni (800°C)

Undoped, with Ni (450°C)

Figure 4.3: Spreading resistance measurement profiles of the samplesfor dopant activation experiment.

to be 0.6µm by observing changes in selective area diffraction (SAD) patterns. The SAD

of MILC poly-Si andα-Si regions are shown in fig. 4.4(b) and 4.4(c) respectively. The

MILC region is composed of several crystals of different orientation as seen from the SAD

pattern. The amorphous region SAD shows just diffused rings.

Fig. 4.5(a) shows side-view TEM images of a transistor structure with a width of

140 nm. Here the MILC was initiated from a region of size 2µm×2 µm, surrounding

the seeding hole and continued in the 140 nm wideα-Si line. Unlike the wide area TEM

images mentioned above, the MILC in 140 nm wideα-Si line produces a single crystal.

A SAD pattern of the MILC region is shown in fig. 4.5(b). The dots in the SAD image

confirm that the MILC region is a single crystal. The diffused rings in the SAD result from

the SiO2 underneath which is amorphous. The TEM also indicates that the single crystal Si


obtained from the MILC has many defects and is not as good as bulk-Si crystal. Along the

length of the structure, the crystal orientation changed every few microns but the silicon

remained single crystal. The length of each single crystal region is well over 1µm and it is

not possible to capture it in one TEM photograph. Silicon far away from the seeding point

stayed amorphous after the 500C 24 hour anneal. Fig. 4.5(c) shows the boundary between

the MILC and amorphous regions which is several tens ofµm away from the starting point

of MILC.

Our observations agree with TEM observations of MILC in submicron lines by Guet

al. [66]. They observed that a single crystal results for MILC for linewidths between 50 nm

and 200 nm but at higher widths competitive grain growth can occur in the beginning

of lateral crystallization. The difference between MILC for wide and narrow regions is

schematically shown in fig 4.6. If the region to be crystallized is wide, multiple grains can

grow side by side leaving one or more grain boundaries in the region. In narrow regions,

there is a higher probability that only one of those grains will grow and occupy the entire

channel region. Therefore, it is desirable to use narrow devices.

It is seen from TEMs that crystals grown with MILC in 140 nm lines are larger than the

CMOS transistors withWdrawn = L = 0.1µm. So these transistors should essentially be in

single crystal Si and should have high performance.


(a)

(b) (c)

Figure 4.4: (a) Plan view TEM of MILC region; (b) selective areadiffraction pattern of MILC poly-Si; and (c) selective areadiffraction pattern ofα-Si.


(a)

(b)

(c)

Figure 4.5: (a) TEM of transistor structure; (b) selective area diffractionpattern; and (c) boundary ofα-Si and crystallized Si.

4.4 : Summary 55

Seeding Hole

Narrow Channel

Wide Channel

Grain Boundary

Figure 4.6: Illustration of MILC growth in wide and narrow channelregions.

4.4 Summary

In this chapter, we saw how crystallization and dopant activation take place when MIC is

used. TEM studies show that MILC in wide area yields a poly-Si film with lots of grain

boundaries but in narrow structures (140 nm) it yields single crystals well over aµm in

length. These are long enough to contain a single MOS transistor.

Dopant activation with nickel at 450C for 24 hours was found to be comparable to

thermal activation without nickel at 800C for 2 hours. This activation is good for the

source/drain and gate electrode during low temperature fabrication of CMOS. The mecha-

nism of dopant activation can be related to rearrangement of Si and dopant atoms as they


attach to the template left behind by NiSi2 in silicide-mediated crystal growth driven by

free energy difference between Ni/α-Si and Ni/c-Si. The next chapter will discuss reliabil-

ity issues of MOS capacitors when MIC is used for dopant activation in the gate electrode.

Chapter 5

Nickel Induced Crystallization of α-Si

Gate Electrodes at 500C and MOS

Capacitor Reliability

5.1 Introduction

We have seen in the previous chapter that MIC with Ni can be used to activate dopants.

For a low temperature process, it gives a nice way to activate dopants in gate electrodes or

source/drain regions which would otherwise require high temperatures. This will be helpful

especially for devices in the upper layers of 3-D IC or devices which cannot tolerate high

temperatures due to reliability concerns about new materials such as high-κ gate dielectric.

Ni is a fast diffuser [67] and a deep trap [68] in silicon. Therefore, if Ni is used to activate

dopants in gate electrodes, it is important to study the effects of Ni MIC on gate oxide and

overall capacitor reliability. In this chapter, we report details of materials analysis as well

as electrical measurements such as C-V, I-V and QBD for capacitors with and without Ni.

57

58 Chapter 5 : MIC for Gate Electrodes and MOS Capacitor Reliability

5.2 Experimental

PMOS capacitors were fabricated on (100) oriented n-type crystalline Si substrates with a

dopant concentration of 1015/cm3. Standard LOCOS was used for isolation. The gate di-

electric was 10 nm thick SiO2 thermally grown at 1000C in an ambient of 70% O2+30% N2.

Immediately after oxide growth,in-situ phosphorus dopedα-Si was deposited at 550C

by LPCVD. The thickness of theα-Si layer was 150 nm and the dopant was not activated.

The gateα-Si was patterned using plasma etching. LTO was deposited by LPCVD over the

patterned gate electrodes and spacers were formed on the sidewalls using anisotropic SiO2

plasma etching.

On an experimental wafer A, a 5 nm thick Ni layer was deposited and the samples were

annealed in N2+H2 at 400C for 4 hours to form silicide over theα-Si gate electrode.

No silicide was formed on the sidewalls because they were protected by SiO2 spacers.

Unreacted Ni was etched in a mixture of H2SO4+H2O2. Crystallization anneal conditions

for wafer A and control wafers B and C are shown in Table 5.1. A schematic cross section

of a capacitor on wafer A is shown in Fig. 5.1. Capacitor structures for wafers B and C

were similar but they did not have any Ni. Capacitors of size 100µm×100µm were used

for all electrical measurements except for Zerbst plots.


5.3.1 SIMS and Spreading Resistance Analysis

Since Ni is a midband trap in Si, any Ni going through the gate oxide into the channel

region will degrade the performance of devices. Therefore, it is important to find out the

amount of Ni in the gate electrode and in the channel. Secondary ion mass spectroscopy

(SIMS) was performed on wafers A, B and C to obtain the concentrations of Ni and P. From


Table 5.1: Annealing conditions for crystallization of the gateα-Si onexperimental and control wafers. Wafers B and C do nothave any silicide.

Crystallization AnnealWafer Ni Temperature Time Ambient

(C) (hours)A Yes 500 24 N2+H2

800 2 N2

B No FOLLOWED BY500 24 N2+H2

C No 500 24 N2+H2

Fig. 5.2(a), the concentration of Ni is in excess of 1021/cm3 in the gate electrode for wafer

A near the top and bottom surfaces of the poly-Si. This high concentration of Ni at the

interface of poly-Si and oxide comes from the NiSi2 front moving inα-Si during MIC [33]

and stopping upon reaching the gate oxide. The SIMS analysis was again performed on

wafer A after removing the poly-Si gate electrode and the gate oxide. The SIMS profile

in Fig. 5.2(b) shows only a very small amount of Ni in the substrate which is not different

from the background level for Ni during SIMS measurements. The profile in Fig. 5.2(b)

resulted from the surface Ni which got redeposited from the etching chemicals. In order

to obtain a more reliable result, one of the samples was polished from the backside and

thinned down to 2 micron. Then a Ni profile was obtained with SIMS starting from the

back surface. No distinguishable Ni signal was found.

From the SIMS profile in Fig. 5.2(a), the concentration of P in the gate electrode is

approximately 1021/cm3 for all wafers. In order to find out the active dopant concentration,

resistivity profiles for wafers A, B and C were obtained by spreading resistance measure-

ments. The resistivity as a function of depth in the gate electrodes is plotted in Fig. 5.3. It


Amorphous Silicon GateSiO Spacer2(n−type)

Thermal SiO 2

Ni

Crystallization Anneal

Gate Electrode Crystallized

10 nm

c−Si Substrate(n−type)

using Nickel MIC

and Ni Wet Etch

500 C 24 hour

Figure 5.1: Schematic cross section of MIC capacitor.

can be seen that the dopant on wafer C did not get activated with a 500C 24 hour anneal in

the absence of Ni. Therefore, it was excluded from further electrical measurements. On the

other hand, the active dopant concentration obtained from spreading resistance on wafers

A and B is approximately 1020/cm3 (10%) and 5× 1019/cm3 (5%), respectively.


1018

1019

1020

1021

1022

0 20 40 60 80 100 120 140

Con

cent

ratio

n (a

tom

s/cm

3 )

Depth In Poly-Si Gate Electrode (nm)

Ni profile: Wafer A (Ni)

P profile: Wafer A (Ni)

P profile: Wafer B (no Ni, 800°C)

P profile: Wafer C (no Ni, 500°C)

Poly-Si/SiO2 Interface →

(a)

1016

1017

1018

0 5 10 15 20 25 30 35 40

Con

cent

ratio

n (a

tom

s/cm

3 )

Depth In Substrate (nm)

Ni profile in substrate: Wafer A (Ni)

← SiO2/Si Interface

(b)

Figure 5.2: SIMS profiles: (a) Ni and P in the gate stack; and (b) Ni inthe substrate.


10-4

10-3

10-2

10-1

100

101

102

103

104

0 20 40 60 80 100 120 140

Res

istiv

ity (

Ω-c

m)

Depth In Poly-Si Gate Electrode (nm)

Wafer A (Ni)Wafer B (no Ni, 800°C)Wafer C (no Ni, 500°C)

Poly-Si/SiO2 Interface →

Figure 5.3: Spreading resistance profiles in the gate stack.

5.3.2 TEM Studies

The cross section transmission electron micrographs of the gate stack for wafers A and B

are shown in Fig. 5.4(a) and 5.4(b), respectively. It can be seen that wafer B has colum-

nar grains in the poly-Si with a grain size close to 0.15µm. The grains on wafer A are

somewhat smaller and are not columnar. They appear to be split in different layers. Energy

dispersive spectroscopy (EDS) analysis on the wafer A poly-Si cross section showed about

30 atomic % Ni near the top of the film and also at the interface of the poly-Si and gate

oxide which suggests NiSi2 at these locations. The top NiSi2 is formed after a 400C sili-

cidation anneal and the interface NiSi2 is a result of MIC. Unlike SIMS, the EDS analysis

did not show any Ni in the middle of the poly-Si film or in the substrate.

The discrepancy between the SIMS results and EDS observations can be explained as


follows. EDS is a local measurement and is helpful in finding out the Ni concentration

in small areas, for example, near the interface of the poly-Si and the gate oxide. The

measurement obtained with EDS has an accuracy of about 1 atomic % which is worse than

that of SIMS. During the SIMS analysis which starts from the top surface of the poly-Si,

the Ni present at the top surface gets pushed inside due to collisions with the incident ion

beam. This results in a higher than actual value at the center of the poly-Si film. In other

words, the Ni profile obtained with SIMS is smeared out.

5.3.3 C-V Measurements

C-V plots for 100µm×100µm size capacitors on wafers A and B were obtained at low

frequency (quasi-static) with a ramp rate of 0.05 V/s and also at a high frequency (10 kHz).

The results are shown in Fig. 5.5(a) and 5.5(b), respectively. Each of the plots represents an

average of measurements performed on 10 identical capacitors. Devices on wafer A show

a positive VFB shift of about 0.1 V which indicates 0.1 eV increase in the gate electrode

workfunction. The VFB shift is not from fixed charge. The fixed charge is positive and

would have caused a negative flat band shift. In our Ni samples, the shift is in the positive

direction. So we are left with the gate electrode workfunction as the cause of flat band

shift. The positive shift of 0.1 V in the VFB is due to a 0.1 eV increase in the gate elec-

trode workfunction. This indicates that theφms and the barrier height for electrons (φb) are

higher by 0.1 eV for the MIC devices. The slope of the C-V curve in the transition region

between accumulation and inversion is lower for wafer A. This degradation of slope is due

to interface traps which are close to 5× 1011/cm2-eV. These traps are probably due to the

lack of a high temperature (800C) anneal.

The change of gate workfunction may be useful for modern short channel devices with

undoped channels which rely on the gate workfunction for adjustment of threshold voltage.


(a)

(b)

Figure 5.4: Cross section TEM of the gate stack: (a) wafer A; and (b)wafer B.

This change is caused by the presence of about 30 atomic % Ni at the gate electrode-oxide

interface.


0

5

10

15

20

25

30

35

40

-3 -2 -1 0 1 2 3

Low

Fre

quen

cy C

apac

itanc

e (p

F)

VG (V)

100 µm X 100 µm, Tox=10 nm

Wafer A (Ni)

Wafer B (no Ni)

(a)

0

5

10

15

20

25

30

35

40

-3 -2 -1 0 1 2 3

Hig

h F

requ

ency

Cap

acita

nce

(pF

)

VG (V)

100 µm X 100 µm, Tox=10 nm

Wafer A (Ni)

Wafer B (no Ni)

(b)

Figure 5.5: C-V plot overlay: (a) low frequency; and (b) highfrequency.


5.3.4 I-V Measurements

I-V characteristics for these capacitors were measured in accumulation as well as in in-

version. Since there are no source/drain regions to obtain inversion charge, it takes a very

long time for it to be generated. In order to get carriers for inversion, illumination with

visible light was used during the measurements. Capacitor I-V characteristics in inversion

and accumulation are shown in Fig. 5.6(a) and 5.6(b), respectively. Each plot is an average

of measurements on 30 identical capacitors.

The positive shifts in I-V plots for wafer A are about 0.1 V and 0.2 V for inversion and

accumulation, respectively and also indicate a change in the flat band voltage. The shift in

accumulation is due to the lower electric field in the oxide of wafer A for a given positive

VG, since its VFB is higher by 0.1 V than wafer B. The positive shift in inversion is explained

as follows. Since theφms for Ni devices is higher by about 0.1 eV, for the same negative

VG applied, it will have a higher|VG−VFB| which means higher band bending. However,

since the band bending in the substrate is fixed due to inversion, rest of the voltage will

be dropped across the oxide. This means that for a given negative VG, the wafer with Ni

will have a higher electric field in the oxide. Since the difference between theφb of Ni

and non-Ni devices is only 0.1 eV, current will be decided by the electric field. Therefore,

higher current will be obtained in the Ni device with the same negative VG applied. In other

words, we need to apply a lower VG to obtain the same current.


10-14

10-13

10-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

-10 -8 -6 -4 -2 0

I G (

A)

VG (V)

100 µm X 100 µm, Tox=10 nm

Wafer A (Ni)

Wafer B(no Ni)

(a)

10-14

10-13

10-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

0 2 4 6 8 10

I G (

A)

VG (V)

100 µm X 100 µm, Tox=10 nm

Wafer A (Ni)

Wafer B (no Ni)

(b)

Figure 5.6: I-V characteristics for capacitors: (a) inversion; and (b)accumulation.


5.3.5 Oxide Reliability with QBD Measurements

QBD was measured under a constant current density of 100 mA/cm2 for substrate (VG+)

and gate (VG−) injection of electrons. Fig. 5.7 shows the cumulative failure plots of QBD.

Wafer A shows a lower QBD for gate injection than wafer B. This can be explained using the

Fowler-Nordheim tunneling model and schematic band diagrams in Fig. 5.8.φbA and EA

are the barrier height and the oxide electric field on wafer A, respectively. They are defined

on wafer B in a similar fashion. The C-V measurements described earlier show that Ni

causes an increase of approximately 0.1 eV in the gate electrode workfunction. Therefore,

the φb for electrons on wafer A increases by 0.1 eV. Under the same current injection in

Fowler-Nordheim tunneling regime, device on wafer A, with higherφb for electrons will

experience higher oxide electric field and consequently lower QBD of gate oxide. Yanget

al. [69] have shown that during gate injection of electrons, the devices with p+ gates show

much lower QBD than those with n+ gates owing to the higherφb of p+ poly-Si. Our results

are in agreement with those of Yanget al.

In the case of substrate injection, the substrate and hence theφb for electrons is the

same. So the higher QBD for wafer A can be attributed to the change in material properties

due to a large amount of Ni (close to 30 atomic %) at the gate electrode-oxide interface.

5.3.6 Zerbst Plots

High frequency (10 kHz) capacitance versus time measurements were performed in order

to estimate the minority carrier generation lifetime and surface generation velocity. In

order to get better measurement accuracy, larger capacitors of size 300µm×300µm were

used. The capacitors were rapidly switched from accumulation (VG = +3 V) to deep

depletion (VG = −3 V). It takes a finite time for inversion layer charge to develop since the

source/drain regions are absent. By measuring the capacitance as a function of time, one


0

10

20

30

40

50

60

70

80

90

100

1 10 100

Cum

ulat

ive

Fai

lure

(%

)

QBD (C/cm2)

J = 100 mA/cm2

100 µm X 100 µm

Wafer A (Ni) - VG+Wafer B - VG+Wafer A (Ni) - VG-Wafer B - VG-

Tox=10 nm

Figure 5.7: QBD for gate and substrate injection of electrons.

can obtain the following relation between the capacitance, generation lifetime,τg,eff and

surface generation velocity,Seff [70].

− d

dt

(Cox

C(t)

)2

=2ni

τg,effND

Cox

Cf

(Cf

C(t)− 1

)+

εSiO2

εSi

2niSeff

toxND

= a

(Cf

C(t)− 1

)+ b (5.1)

τg,eff =2ni

aND

Cox

Cf(5.2)

Seff =εSi

εSiO2

toxNDb

2ni

(5.3)

Cox andCf are the oxide capacitance and capacitance at infinite time (after inversion layer


With NiNo Ni

Gate GateSubSub

<B EA

EB EA

E

0.1 eV

φ bB φ bA

Figure 5.8: Schematic band diagrams for wafer A (with Ni) and B (noNi).

formation), respectively.tox is the gate oxide thickness andND is the doping in the sub-

strate. In our large capacitors,Cox ≈ 310 pF andCf ≈ 9 pF. Fig. 5.9 shows the Zerbst plots

of d/dt(Cox/C(t))2 as a function of(Cf/C(t)− 1) for wafers A and B. The data points

are plotted along with a linear approximation using the least squares fit. From the slope,a

and y-intercept,b, of the fitted line in the Zerbst plot, the generation times were estimated.

They were found to be 5 ms and 1 ms for wafer A and B, respectively. The devices in wafer

A showed a significantly higher value of the surface generation velocity (0.57 cm/s) com-

pared to that on wafer B (0.06 cm/s). The difference between the generation lifetimes on

5.4 : Summary 71

0

0.5

1

1.5

2

2.5

3

3.5

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

d/dt

(Cox

/C(t

))2

Cf/C(t)-1

300 µm X 300 µm

Wafer A (Ni)

Wafer B (no Ni)

Figure 5.9: Zerbst plots for wafers A and B.

wafers A and B is a result of wafer to wafer variation. The generation lifetime of the order

of a millisecond in bulk silicon indicates that it is not degraded during MIC. The increased

surface generation velocity on wafer A may be due to interface traps resulting from the lack

of an 800C anneal. Though the MIC samples as well as control samples were annealed in

forming gas at 500C for 24 hours, it seems that the interface traps were not annealed out

in the MIC samples.

5.4 Summary

We have fabricated capacitors using Ni MIC for dopant activation in the gate electrode and

studied their reliability using materials analysis as well as electrical measurements. With a

500C - 24 hour MIC, approximately 10% of the phosphorus is activated which is higher


than that for a pure thermal anneal of 800C for 2 hours.

In the MIC process, there is a NiSi2 front between c-Si andα-Si and it will be present

wherever MIC ends. From the EDS observations, the Ni concentration at the top and

bottom surfaces of the MIC gate electrode was close to 30 atomic % indicating the presence

of NiSi2 at both surfaces. This high concentration of Ni at the gate electrode-oxide interface

is responsible for the changes in electrical properties of the capacitors. Since this method

enables us to obtain a high concentration of Ni near the gate/oxide interface, the problem

of conventional poly-Si gate depletion may be alleviated if this Ni makes the gate electrode

more metallic. While the concentration of Ni is high in the gate, it is not detectable with

SIMS in the substrate.

One of the most important effects is the increase of about 0.1 eV in the gate electrode

workfunction which was confirmed through C-V, I-V and QBD measurements. It may be

useful in modern device applications where adjustment of gate workfunction is needed.

Increase in theφb for electrons and reduction in the gate injection QBD result from the

0.1 eV increase in gate electrode workfunction. The presence of 30 atomic % Ni at the gate

electrode-oxide interface increased substrate injection QBD.

The degradation of the C-V curve slope and increase in the surface generation velocity

are due to interface traps which probably result from the lack of a high temperature anneal

for the MIC wafer. Ni MIC in the gate electrode does not degrade the overall capacitor

reliability.

Chapter 6

High Performance Submicron CMOS

with Metal Induced Lateral

Crystallization of Amorphous Silicon

6.1 Introduction

Thin Film Transistors (TFTs) fabricated on laterally crystallized amorphous silicon films

have been reported in the past few years. Forα-Si films on transparent substrates, pat-

terned light absorption masks [71] make use of light to raise the temperature of silicon film

in lithographically defined areas. Nucleation occurs preferentially at these sites and during

subsequent furnace annealing these nuclei grow before significant homogeneous nucleation

can occur in other parts of the film. As a result, larger grains are obtained in poly-Si films.

Similar results have been demonstrated by depositing germanium on small areas over a

silicon film [72] and annealing the samples at a low temperature (500C). Transistors with

MILC using nickel were first reported by Leeet al. [28]. Subsequently, Kimet al. [73] and

73

74 Chapter 6 : High Performance Submicron CMOS with MILC

Bhatet al. [74] also demonstrated MILC for TFT fabrication. When Ni is used for MILC,

the mechanism of crystallization has been shown to be silicide-mediated [51]. Other metals

like Pd [53] and Co [35] have also been used for thin film transistor fabrication with MIC.

In most of the work reported so far, long channel TFTs aimed at display applications were

described. However, such devices may not be suitable for 3-D integrated circuit applica-

tions where multiple levels of high quality transistors may be built on top of interconnect

layers.

In this chapter, details of 0.1µm CMOS transistors fabricated using the Ni-MILC pro-

cess are presented. This work is aimed at fabrication of transistors at low temperature for

3-D integrated circuits [2]. In such applications it is critical to maintain low processing

temperatures in order to ensure that already fabricated devices, dielectrics and metal inter-

connects perform as desired. This means that all fabrication processes must be completed

at or below 500C and may be even lower temperatures depending on the materials used

for dielectrics and interconnects.

6.2 CMOS Transistor Fabrication

For transistor fabrication, thermally oxidized Si wafers were used as substrates. 0.1µm

thick undopedα-Si was deposited using silane LPCVD at 500C and 1 torr and patterned

into active area islands. A typical channel island is depicted in Fig. 6.1. The shaded region

in the figure shows the area which will be covered by the gate electrode. Since the channel

is present on the top surface as well as the sidewalls of island,Weff = Wdrawn+ 0.2µm.

Fig. 6.2 shows a schematic cross section of a transistor structure illustrating the MILC

process. In order to reduce DIBL, the channel region of the PMOS devices was ion implant

doped with phosphorus to about 2.5× 1017/cm3 and that of NMOS with boron to about

2 × 1017/cm3. The gate oxide was 12 nm thick SiO2 deposited by LPCVD at 450C.

6.2 : CMOS Transistor Fabrication 75

Drain

Overlapped by Gate Electrode

L

H

Source W

Area of Channel Island

drawn

Figure 6.1: Schematic 3-D view of transistor channel island before gateelectrode deposition and patterning.

150 nm thick,in-situ boron doped LPCVD poly-Si0.6Ge0.4 was used as the gate electrode.

The poly-SiGe gate had a sheet resistance of 1 kΩ/. The source/drain regions were

separated from the gate by 0.05µm using SiO2 spacers. The source and drain regions were

implanted with 15 keV boron for the PMOS devices and 35 keV phosphorus for the NMOS

devices to give an implanted dopant concentration of 3× 1020/cm3. An LDD-implant was

not used in order to reduce device complexity. The heavy dopant implant for source/drain

had enough lateral straggle [75] to dope the region under the spacers so that there is some

overlap between the source/drain regions and the gate. Electron beam lithography was used

for patterning the submicron features for active islands and gate electrodes. Devices were

fabricated with drawn widths of 0.1µm and 0.4µm in order to see the effect of width on

transistor performance. After an SiO2 passivation layer was deposited at 400C, seeding

holes of size 1µm×1 µm were opened either on the source or the drain and about 25 nm

thick layer of Ni was sputter deposited. The wafers were annealed at 400C for 4 hours to

form nickel silicide in the seeding holes. Unreacted Ni was etched in H2SO4+H2O2. The

wafers were then annealed in N2 at 500C for 24 hours or 450C 144 hours to enable Ni-

MILC starting from the seeding holes into the channel and source/drain regions. Dopants


α−Silicon Crystallized with Nickel

SiO Spacer

SiO Passivation Layer

2

2

−Silicon Filmα

Gate Oxide

Contact / SeedingHole

Poly−SiGe Gate

Thermal SiO 2

c−Si Substrate

Figure 6.2: Schematic cross section of transistor showing MILCprocess.

in these region were also activated during this MILC step. After crystallization, contact

holes were opened on the source/drain and poly-SiGe gate electrode. The seeding holes

also served as contact holes. Al was used for interconnects and contact pads. Finally, the

devices were annealed in forming gas at 400C for 1 hour.


6.3.1 Performance of CMOS with MILC at 500 C

Fig. 6.3(a) and 6.3(b) illustrate ID-VG curves for NMOS and PMOS transistors, respec-

tively. These transistors were fabricated with MILC at 500C. The subthreshold slope,

S, ION and IOFF were calculated from these ID-VG plots at|VD| = 2 V and the threshold

voltage, VTH, is defined as gate voltage which gives 10 nA×WeffL

for |VD| = 2 V. The IOFF is

defined as the lowest current obtained with|VD| = 2 V. ID-VD characteristics of the same


transistors are shown in Fig. 6.4(a) and 6.4(b). It can be seen that the NMOS and PMOS on

currents are approximately 150µA/µm and 100µA/µm, respectively. The extracted device

parameters are summarized in Table 6.1. The mobility values have been calculated from

ID-VG plots with a|VD| of 0.05 V. The mobility values are listed Table 6.1. The mobility for

the 500C devices is somewhat lower as compared to other observations for MILC CMOS

devices [28, 54]. Part of this mobility degradation is due to the series resistance of the re-

gions under the spacers. Another reason for the degradation is the use of a deposited gate

oxide which does not have a good interface with the channel. Since these CMOS transistors

fabricated in recrystallized Si are for 3-D integrated circuits, their performance should be

compared to that of bulk-Si CMOS. Ghaniet al.[76] demonstrated CMOS with a 100 nm

effective gate length and a 3 nm gate oxide. With a VDD of 1.2 V, they obtained 760µA/µm

and 310µA/µm for NMOS and PMOS, respectively. By reducing the gate oxide thickness

in our CMOS to 3 nm, an increase in the drive current by factor of 4 is expected. However,

a reduction in VDD from 2 V to 1.2 V will decrease ID by about a factor of 2. So with 3 nm

gate oxide and VDD of 1.2 V, we can expect to get a drive current close to 300µA/µm and

200µA/µm from our NMOS and PMOS, respectively.

P-type SiGe would normally cause low VTH for PMOS and high VTH for NMOS. The

observed values of VTH are high for PMOS and low for NMOS. This difference can be

caused by fixed oxide charge or interface trapped charge since we used an LPCVD gate

oxide on an imperfect Si crystal. The subthreshold slope of 100 mV/dec is one of the best

for MIC devices but still far from ideal because of defects and traps in the recrystallized Si

and a somewhat thick gate oxide. In order to improve the subthreshold slope and DIBL,

the channel Si film can be made thinner to make the device fully depleted and less prone

to short channel effects. Also, the interface between the gate oxide and channel can be

improved by using a better gate oxide. Series resistance can be reduced by having good

silicided contacts.


Table 6.1: Performance of submicron MILC transistors.

Device 500C PMOS 500C NMOS 450C PMOS 450C NMOSVTH (V) −0.25 0.12 −2.41 −0.12S (mV/dec) −200 100 −343 291IOFF (pA/µm) −19.2 3.4 −790 4000ION (µA/µm) −103 150 −40 (VG = −5 V) 145ION/IOFF 5.3× 106 4.7× 107 5× 104 4× 104

µ (cm2/V-s) 42 67 7 38

6.3.2 Performance of CMOS with MILC at 450 C

Fig. 6.5(a) and 6.5(b) show the ID-VG characteristics for the NMOS and PMOS transistors

with MILC at 450C. S, ION, IOFF and VTH for these transistors have been extracted by the

same method which was used for 500C devices and are summarized in Table 6.1. For the

PMOS, ION was obtained at VG = −5 V. The reason for the crossover (lack of DIBL) in the

450 C PMOS is not clear. It probably results from a high concentration of defects or Ni

in the channel. For the PMOS, the extracted mobility is quite poor. It indicates that there

is a lot of scattering in the channel or that the crystallization in the channel is not good.

Fig. 6.6(a) and 6.6(b) show ID-VD curves for the same devices. The 450C crystallized

devices show good on currents but worse leakage and subthreshold slope than the 500C

crystallized devices, probably owing to worse crystal quality. In these transistors, only the

α-Si channel and SiGe gate electrode deposition were performed at 500C. All other steps

in the fabrication were at or below 450C. By changing the deposition chemistry to Si2H6,

the α-Si deposition can be done at or below 450C to obtain good quality amorphous

silicon film [77]. As mentioned earlier in this chapter, dopant activation with MIC can be

easily achieved at 450C and used for dopant activation in the gate electrode. In Chapter 5,


10-13

10-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

-2 -1.5 -1 -0.5 0 0.5 1 1.5 2

I D (

A/µ

m)

VG (V)

Weff=0.3 µmLgate=0.1 µm

VD=2 V

VD=0.05 V

(a)

10-13

10-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

-2 -1.5 -1 -0.5 0 0.5 1 1.5 2

-ID

(A

/µm

)

VG (V)


VD=-2 V

VD=-0.05 V

(b)

Figure 6.3: ID vs. VG for 500C crystallized devices: (a) NMOS; and(b) PMOS.


0

20

40

60

80

100

120

140

160

180

0 0.5 1 1.5 2

I D (

µA/µ

m)

VD (V)

Weff=0.3 µmLgate=0.1 µm VG=2 V

VG=1.5 V

VG=1 V

VG=0.5 V

(a)

0

10

20

30

40

50

60

70

80

-2 -1.5 -1 -0.5 0

-ID

(µA

/µm

)

VD (V)

Weff=0.3 µmLgate=0.1 µmVG=-2 V

VG=-1.5 V

VG=-1 V

(b)

Figure 6.4: ID vs. VD for 500C crystallized devices: (a) NMOS; and(b) PMOS.


we reported a comparison of Ni-MIC at 500C and pure thermal activation of dopants at

800 C for use in gate electrode where we showed that Ni-MIC can be used for dopant

activation in the gate without causing serious reliability concerns.

6.3.3 Effect of Device Width

Fig. 6.7 shows cumulative plots of IOFF and ION for 500 C MILC transistors of effective

widths 0.3µm and 0.6µm (Wdrawn of 0.1µm and 0.4µm, respectively). It can be observed

that for both the NMOS and PMOS devices, the mean value of IOFF increases by several

orders of magnitude when going from 0.3µm to 0.6µm but the ION does not show sig-

nificant change. The IOFF scales neither withWeff nor with Wdrawn. It is quite likely that

such a drastic increase in IOFF is due to inclusion of a longitudinal grain boundary in the

channel [78] forWdrawn of 0.4µm. As illustrated in Fig. 4.6, the 0.4µm wide devices are

much more likely to have a grain boundary in the channel than 0.1µm wide devices. The

ION in our devices does not change with width because the grain boundaries are likely to be

more or less longitudinal and do not present a barrier to current flow. Therefore, in order to

improve transistor performance, it should be fitted in single grain of recrystallized Si. One

approach is to use high temperature grain growth [55] where the grain size was increased

to accommodate a transistor. Our approach is shrinking a transistor to submicron size so

that it fits in an elongated grain of Si which is obtained through processes like MILC at

temperatures of about 500C. In this chapter, we have demonstrated CMOS transistors

using the latter. The advantage of our method is that it can be completed with a maximum

process temperature of 500C. Therefore, it may be more suitable for 3-D integrated circuit

applications than the high temperature grain enhancement method [55].


10-13

10-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

-2 -1.5 -1 -0.5 0 0.5 1 1.5 2

I D (

A/µ

m)

VG (V)


VD=2 V

VD=0.05 V

(a)

10-13

10-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

-5 -4 -3 -2 -1 0 1 2

-ID

(A

/µm

)

VG (V)


VD=-2 V

VD=-0.05 V

(b)

Figure 6.5: ID vs. VG for 450C crystallized devices: (a) NMOS; and(b) PMOS.


0

20

40

60

80

100

120

140

160

0 0.5 1 1.5 2

I D (

µA/µ

m)

VD (V)


VG=2 V

VG=1.5 V

VG=1 V

VG=0.5 V

(a)

0

5

10

15

20

25

30

35

40

-2 -1.5 -1 -0.5 0

-ID

(µA

/µm

)

VD (V)


VG=-4.5 V

VG=-5 V

VG=-4 V

VG=-3.5 V

VG=-3 V

(b)

Figure 6.6: ID vs. VD for 450C crystallized devices: (a) NMOS; and(b) PMOS.


0

10

20

30

40

50

60

70

80

90

100

10-6 10-5 10-4 10-3 10-2 10-1 100 101 102 103

Cum

ulat

ive

Per

cent

age

NMOS ID (µA/µm)

IOFF ION

Lgate=0.1 µmWeff

0.3 µm0.6 µm

(a)

0

10

20

30

40

50

60

70

80

90

100

10-6 10-5 10-4 10-3 10-2 10-1 100 101 102 103

Cum

ulat

ive

Per

cent

age

PMOS ID (µA/µm)

IOFF ION

Lgate=0.1 µmWeff

0.3 µm0.6 µm

(b)

Figure 6.7: ION and IOFF as a function of device width for 500Ccrystallized devices: (a) NMOS; and (b) PMOS.

6.4 : Summary 85

6.4 Summary

The processes of crystallization and dopant activation with MIC were combined to obtain

a high performance CMOS devices using a peak process temperature of 500C. It is im-

portant to avoid grain boundaries in the channel in order to improve device performance

and it made possible because MILC yields single crystal in 140 nm or narrower lines of

α-Si. This process also activates dopants in the source/drain and channel regions at a low

temperature.

0.1µm high performance CMOS transistors have been fabricated using the MILC pro-

cess. As shown with the TEM study, these transistors are contained in a single grain of

silicon. NMOS and PMOS devices show on-currents of 150µA/µm and 100µA/µm,

respectively. Upon changing gate dielectric thicknesses to 3 nm and VDD to 1.2 V , the cur-

rents can be estimated to increase to 300µA/µm and 200µA/µm for NMOS and PMOS,

respectively. Other improvements in fabrication and device structure like thin body and

silicidation should further improve the device performance in terms of short channel ef-

fects and subthreshold slope, making them more suitable for 3-D integrated circuits where

high quality CMOS devices in recrystallized Si are needed with a constraint of a 500C

peak process temperature.

Severe degradation of IOFF was observed from cumulative plots upon increasingWdrawn

from 0.1µm to 0.4µm which is very likely caused by inclusion of a grain boundary in the

channel. So in order to get high performance, it is crucial to keepWdrawn low. If higher

current is desired, several narrow transistors should be combined in parallel instead of a

single wide transistor.

Chapter 7

Conclusions

In this thesis, issues pertaining to CMOS fabrication using MILC were discussed. The

important contributions from this work are listed below.

7.1 Contributions

7.1.1 A Model for MILC

• The rate of crystal growth is shown to be related to the rate of NiSi2 thinning.

• Crystal growth during MILC is explained using a two-regime model. The first regime

is diffusion limited where the diffusion flux of Ni atoms through thin NiSi2 is smaller

than the surface reaction flux. The second regime is surface reaction limited where

the diffusion flux of Ni atoms exceeds the surface reaction flux.

• The model brings out the competition between MIC and SPC through use of a time-

varying surface reaction rate constant.

86

7.1 : Contributions 87

7.1.2 Metal Induced Crystallization and Dopant Activation

• Dopant activation with Ni at 500C was shown to be comparable to that without Ni

at 800C.

• It was shown that MILC gives poly-Si films when wide areas are crystallized but

causes single crystals in narrow lines of width 140 nm.

7.1.3 MIC Dopant Activation and MOS Capacitor Reliability

• It was shown that close to 30 atomic % Ni resides at the interface between the gate

electrode and oxide when MILC is used in the gate electrode. This indicates the

presence of NiSi2 and also causes changes in the electrical properties.

• Through C-V, I-V and QBD measurements it has been demonstrated that the gate

electrode workfunction increases by about 0.1 eV.

• The presence of interface traps in MIC devices is indicated by a degradation in the

slope of C-V curves and an increase in the surface generation velocity of minority

carriers in the substrate.

7.1.4 High Performance CMOS with MILC

• Dopant activation and single crystal formation due to MILC were utilized to demon-

strate fabrication of high performance CMOS devices with a peak fabrication tem-

perature of 500C.

• It was shown that narrow transistors have much lower leakage current than wider

transistors. This shows that in order to obtain higher effective width, several transis-

tors need to be combined in parallel.

88 Chapter 7 : Conclusions

7.2 Recommendations for Future Work

Though this thesis covered fabrication of high performance CMOS with low processing

temperatures, a lot of work needs to be done in order to bring device performance close to

that of bulk-Si devices. For a channel length of 100 nm, the gate oxide used in this work

is quite thick. It needs to be reduced to the dimensions used by current CMOS technol-

ogy. Also, in order to reduce the gate leakage, high-κ materials will be needed. One of the

biggest challenges is lowering the peak process temperature to 450C or less. We demon-

strated a possibility of 450C fabrication but device yields were quite low and performance

was somewhat poor. Methods to make MILC faster must be explored in order to reduce

process times. It has been observed by several researchers that Ni moves towardsα-Si dur-

ing MIC. This property can find possible use in novel thin body double-gate devices. The

Ni remaining at the initial and final points can serve as contacts.

Another interesting extension of this thesis would be to explore the change of work-

function due to Ni MIC. It could be useful in setting gate workfunctions of future short

channel devices. In this work only n-type Si was used for the gate electrode. It would be

interesting to see the results for p-type Si. Also, it would be interesting to see if the amount

of workfunction change depends on process temperature and thickness of the initial Ni

layer. It also needs to be seen if the high concentration of Ni helps in reducing gate deple-

tion. This is important for short channel devices where poly-Si gate depletion contributes

significantly to the effective gate dielectric thickness.

Our model for MILC can be extended to consider the condition when the initial supply

of Ni is not removed. With more data for growth rates at different temperatures, the pa-

rameters used in the model can be estimated with better accuracy. A study of the atomistic

level movements using Ni or Si isotopes may be helpful in understanding the mechanism

of the MILC process.

Bibliography

[1] International Technology Roadmap for Semiconductors. [On-line],

http://public.itrs.net, International SEMATECH, 2001.

[2] S. J. Souri, K. Banerjee, A. Mehrotra, and K. C. Saraswat, “Multiple Si Layer ICs:

Motivation, Performance Performance and Design Implications,” in37th Design Au-

tomation Conference Proceedings, Los Angeles, CA, June 2000, pp. 213–220.

[3] K. Banerjee, S. J. Souri, P. Kapur, and K. C. Saraswat, “3-D ICs: A Novel Chip

Design for Improving Deep-Submicrometer Interconnect Performance and Systems-

on-Chip Integration,” Proceedings of the IEEE, vol. 89, no. 5, pp. 602–633, May

2001.

[4] D. Edelstein, J. Heidenreich, R. Goldblatt, W. Cote, C. Uzoh, N. Lustig, P. Roper,

T. McDevitt, W. Motsiff, A. Simon, J. Dukovic, R. Wachnik, H. Rathore, R. Schulz,

L. Su, S. Luce, and J. Slattery, “Full Copper Wiring in a Sub-0.25µm CMOS ULSI

Technology,” in1997 International Electron Devices Meeting Technical Digest, 1997,

pp. 773–776.

[5] S. Venkatesan, A. V. Gelatos, S. Hisra, B. Smith, R. Islam, J. Cope, B. Wilson,

D. Tuttle, R. Cardwell, S. Anderson, M. Angyal, R. Bajaj, C. Capasso, P. Crabtree,

S. Das, J. Farkas, S. Filipiak, B. Fiordalice, M. Freeman, and P. V. Gilbert, “A High

89

90 Bibliography

Performance 1.8 V, 0.20µm CMOS Technology with Copper Metallization,” in1997

International Electron Devices Meeting Technical Digest, 1997, pp. 769–772.

[6] E. M. Zielinski, S. W. Russell, R. S. List, A. M. Wilson, C. Jin, K. J. Newton, J. P. Lu,

T. Hurd, W. Y. Hsu, V. Cordasco, M. Gopikanth, V. Korthuis, W. Lee, G. Cerny, N. M.

Russell, P. B. Smith, S. O’Brien, and R. H. Havemann, “Damascene Integration of

Copper and Ultra-Low-k Xerogel for High Performance Interconnects,” in1997 In-

ternational Electron Devices Meeting Technical Digest, Washington, DC, Dec. 1997,

pp. 936–938.

[7] B. Zhao, D. Feiler, V. Ramanathan, Q. Z. Liu, M. Brongo, J. Wu, H. Zhang, J. C. Kuei,

D. Young, J. Brown, C. Vo, W. Xia, C. Chu, J. Zhou, C. Nguyen, L. Tsau, D. Dornish,

L. Camilletti, P. Ding, G. Lai, B. Chin, M. Johnson, J. Turner, T. Ritzdorf, G. Wu, and

L. Cook, “A Cu/low-κ Dual Damascene Interconnect for High Performance and Low

Cost Integrated Circuits,” in1998 Symposium on VLSI Technology Technical Digest,

1998, pp. 28–29.

[8] P. Kapur, J. P. McVittie, and K. C. Saraswat, “Technology and Reliability Constrained

Future Copper Interconnects Part I: Resistance Modeling,”IEEE Transactions on

Electron Devices, vol. 49, no. 4, pp. 590–597, Apr. 2002.

[9] D. S. Campbell, “The Electrical Properties of Single-Crystal Metal Films,” inThe

Use of Thin Films in Physical Investigations, J. C. Anderson, Ed. 1966, pp. 299–318,

Academic Press, London.

[10] M. van Heijningen, M. Badaroglu, S. Donnay, G. G. E. Gielen, and H. J. De Man,

“Substrate Noise Generation in Complex Digital Systems: Efficient Modeling and

Simulation Methodology and Experimental Verification,”IEEE Journal of Solid-State

Circuits, vol. 37, no. 8, pp. 1065–1072, Aug. 2002.

Bibliography 91

[11] T. Oku, H. Mori, and M. Murakami, “Diffusion Barriers for Copper Interconnects,”

in 1998 Solid-State and Integrated Circuit Technology Proceedings, Beijing, China,

Oct. 1998, pp. 238–241.

[12] T. Kawanoue, T. Iijima, T. Matsuda, Y. Yamada, M. Morikado, K. Sugimae,

T. Kajiyama, H. Maekawa, T. Hamamoto, J. Kumagai, H. Kaneko, and N. Hayasaka,

“Quantitative Analysis on Cu Diffusion through TaN Barrier Metal and the Device

Degradation by using Two-Level Cu-Interconnects Implemented 0.25µm-256 Mbit

DRAMs,” in 2000 International Interconnect Technology Conference Proceedings,

Burlingame, CA, June 2000, pp. 199–201.

[13] N. M. Rutherford, T. A. Baldwin, and S. K. Gupta, “A New Low Dielectric Con-

stant Planarization Dielectric,” in1991 International VLSI Multilevel Interconnection

Conference Proceedings, Santa Clara, CA, June 1991, pp. 448–450.

[14] B. H. Lee, L. Kang, W. J. Qi, R. Nieh, Y. Jeon, K. Onishi, and J. C. Lee, “Ultra-

thin Hafnium Oxide with Low Leakage and Excellent Reliability for Alternative Gate

Dielectric Application,” in1999 International Electron Devices Meeting Technical

Digest, Washington, DC, Dec. 1999, pp. 133–136.

[15] R. Choi, K. Onishi, C. S. Kang, S. Gopalan, R. Nieh, Y. H. Kim, J. H. Han,

S. Krishnan, H. J. Cho, A. Shahriar, and J. C. Lee, “Fabrication of High Quality

Ultra-Thin HfO2 Gate Dielectric MOSFETs Using Deuterium Anneal,” in2002 Inter-

national Electron Devices Meeting Technical Digest, San Francisco, CA, Dec. 2002,

pp. 613–616.

[16] S. Kawamura, N. Sasaki, T. Iwai, M. Nakano, and M. Takagi, “Three-Dimensional

CMOS ICs Fabricated by Using Beam Recrystallization,”IEEE Electron Device Let-

ters, vol. 4, no. 10, pp. 366–368, Oct. 1983.

92 Bibliography

[17] S. Akiyama, S. Ogawa, M. Yoneda, N. Yoshii, and Y. Terui, “Multilayer CMOS

Device Fabricated on Laser Recrystallized Silicon Islands,” in1983 International

Electron Devices Meeting Technical Digest, Washington, DC, Dec. 1983, pp. 352–

355.

[18] M. Nakano, “3-D SOI/CMOS,” in1984 International Electron Devices Meeting

Technical Digest, San Francisco, CA, Dec. 1984, pp. 792–795.

[19] K. Sugahara, T. Nishimura, S. Kusunoki, Y. Akasaka, and H. Nakata, “SOI/SOI/Bulk-

Si Triple-Level Structure for Three-Dimensional Devices,”IEEE Electron Device

Letters, vol. 7, no. 3, pp. 193–195, Mar. 1986.

[20] Y. Akasaka and T. Nishimura, “Concept and Basic Technologies for 3-D IC Struc-

ture,” in1986 International Electron Devices Meeting Technical Digest, Los Angeles,

CA, Dec. 1986, pp. 488–491.

[21] T. Nishimura, Y. Inoue, K. Sugahara, S. Kusunoki, T. Kumamoto, S. Nakagawa,

M. Nakaya, Y. Horiba, and Y. Akasaka, “Three Dimension IC for High Performance

Image Signal Processor,” in1987 International Electron Devices Meeting Technical

Digest, Washington, DC, Dec. 1987, pp. 111–114.

[22] K. C. Saraswat, S. J. Souri, V. Subramanian, A. R. Joshi, and A. W. Wang, “Novel

3-D Structures,” inProceedings of 1999 IEEE International SOI Conference, Rohnert

Park, CA, Oct. 1999, pp. 54–55.

[23] A. W. Wang and K. C. Saraswat, “Modeling of Grain Size Variation Effects in Poly-

crystalline Thin Film Transistors,” in1998 International Electron Devices Meeting

Technical Digest, San Francisco, CA, Dec. 1998, pp. 277–280.

Bibliography 93

[24] J. Burns, L. McIlrath, C. Keast, C. Lewis, A. Loomis, K. Warner, and P. Wyatt,

“Three-Dimensional Integrated Circuits for Low-Power, High-Bandwidth Systems on

a Chip,” in2001 International Solid-State Circuits Conference Digest, San Francisco,

CA, Feb. 2001, pp. 268–269.

[25] M. Koyanagi, Y. Nakagawa, K. W. Lee, T. Nakamura, Y. Yamada, K. Inamura,

K. T. Park, and H. Kurino, “Neuromorphic Vision Chip Fabricated Using Three-

Dimensional Integration Technology,” in2001 International Solid-State Circuits Con-

ference Digest, San Francisco, CA, Feb. 2001, pp. 270–271.

[26] G. W. Neudeck, S. Pae, J. P. Denton, and T. C. Su, “Multiple Layers of Silicon-on-

Insulator for Nanostructure Devices,”Journal of Vacuum Science and Technology B,

vol. 17, no. 3, pp. 994–998, May 1999.

[27] V. Subramanian and K. C. Saraswat, “High-Performance Germanium-Seeded Later-

ally Crystallized TFTs for Vertical Device Integration,”IEEE Transactions on Elec-

tron Devices, vol. 45, no. 9, pp. 1934–1939, Sept. 1998.

[28] S. W. Lee and S. K. Joo, “Low Temperature Poly-Si Thin-Film Transistor Fabrication

by Metal-Induced Lateral Crystallization,”IEEE Electron Device Letters, vol. 17, no.

4, pp. 160–162, Apr. 1996.

[29] V. Subramanian, M. Toita, N. R. Ibrahim, S. J. Souri, and K. C. Saraswat, “Low-

Leakage Germanium-Seeded Laterally-Crystallized Single-Grain 100-nm TFTs for

Vertical Integration Applications,”IEEE Electron Device Letters, vol. 20, no. 7, pp.

341–343, July 1999.

[30] J. R. Bosnell and U. C. Voisey, “The Influence of Contact Materials on the Conduc-

tion Crystallization Temperature and Electrical Properties of Amorphous Germanium,

Silicon and Boron Films,”Thin Solid Films, vol. 6, no. 3, pp. 161–166, Sept. 1970.

94 Bibliography

[31] G. Liu and S. J. Fonash, “Selective Area Crystallization of Amorphous Silicon Thin

Films by Low-Temperature Rapid Thermal Annealing,”Applied Physics Letters, vol.

55, no. 7, pp. 660–662, Aug. 1989.

[32] R. C. Cammarata, C. V. Thmopson, and K. N. Tu, “NiSi2 Precipitation in Nickel-

Implanted Silicon Films,”Applied Physics Letters, vol. 51, no. 14, pp. 1106–1108,

Oct. 1987.

[33] C. Hayzelden, J. L. Batstone, and R. C. Cammarata, “In Situ Transmission Electron

Microscopy Studies of Silicide-Mediated Crystallization of Amorphous-Silicon,”Ap-

plied Physics Letters, vol. 60, no. 2, pp. 225–227, Jan. 1992.

[34] S. W. Lee, Y. C. Jeon, and S. K. Joo, “Pd Induced Lateral Crystallization of Amor-

phous Silicon Thin Films at Low Temperature,” inThin Film Transistor Technologies

II , Y. Kuo, D. G. Ast, M. Hack, M. Matsumura, M. Le Contellec, and E. Lueder, Eds.

1994, pp. 115–125, The Electrochemical Society Inc., Pennington, NJ.

[35] J. K. Park, S. H. Kim, W. S. Shon, S. J. Park, J. Jang, S. Y. Yoon, and C. O. Kim,

“Polycrystalline Silicon Thin Film transistor Using Co Induced MIC,” inThin Film

Transistor Technologies IV, Y. Cuo, Ed. 1998, pp. 84–91, The Electrochemical Soci-

ety Inc., Pennington, NJ.

[36] T. J. Konno and R. Sinclair, “Metal-Contact-Induced Crystallization of Semiconduc-

tors,” Materials Science and Engineering, vol. A179-A180, pp. 426–432, May 1994.

[37] D. H. Lee, R. R. Hart, and O. J. Marsh, “Effects of Al Films on Ion-Implanted Si,”

Applied Physics Letters, vol. 20, no. 2, pp. 73–75, Jan. 1972.

[38] S. R. Herd, P. Chaudhari, and M. H. Brodsky, “Metal Contact Induced Crystallization

Bibliography 95

in Films of Amorphous Silicon and Germanium,”Journal of Non-Crystalline Solids,

vol. 7, no. 4, pp. 309–327, May 1972.

[39] L. S. Hung, S. H. Chen, and J. W. Mayer, “Interaction of Al Films of Single Crystal Si

Substrates Induced by Ion Irradiation and Post-Anneal,” inThin Films and Interfaces

II , J. E. E. Baglin, D. R. Campbell, and W. K. Chu, Eds. 1984, pp. 253–258, Elsevier

Science Publishing Co., New York, NY.

[40] H. T. G. Hentzell, A. Robertsson, L. Hultman, G. Shaofang, S. E. Hornstrom, and

P. A. Psaras, “Formation of Aluminum Silicide Between Two Layers of Amorphous

Ailicon,” Applied Physics Letters, vol. 50, no. 14, pp. 933–934, Apr. 1987.

[41] S. F. Gong, H. T. G. Hentzell, A. E. Robertsson, L. Hultman, S. E. Hornstrom, and

G. Radnoczi, “Al-Doped and Sb-Doped Polycrystalline Silicon Obtained by Means

of Metal-Induced Crystallization,”Journal of Applied Physics, vol. 62, no. 9, pp.

3726–3732, Nov. 1987.

[42] G. Radnoczi, A. Robertson, H. T. G. Hentzell, S. F. Gong, and M. A. Hasan, “Al

Induced Crystallization of a-Si,”Journal of Applied Physics, vol. 69, no. 9, pp. 6394–

6399, May 1991.

[43] T. J. Konno and R. Sinclair, “Crystallization of Silicon in Aluminum/Amorphous-

Silicon Multilayers,” Philosophical Magazine B, vol. 66, no. 6, pp. 749–765, Dec.

1992.

[44] D. Sigurd, G. Ottaviani, V. Marrello, J. W. Mayer, and J. O. McCaldin, “Crystalliza-

tion of Evaporated Si/Ag and Ge/Al Films,”Journal of Non-Crystalline Solids, vol.

12, no. 1, pp. 135–139, May 1973.

96 Bibliography

[45] G. Ottaviani, V. Marrello, D. Sigurd, J. W. Mayer, and J. O. McCaldin, “Crystalliza-

tion of Ge and Si in Metal Films. I,”Journal of Applied Physics, vol. 45, no. 4, pp.

1730–1739, Apr. 1974.

[46] D. Sigurd, G. Ottaviani, H. J. Arnal, and J. W. Mayer, “Crystallization of Ge and Si

in Metal Films. II,” Journal of Applied Physics, vol. 45, no. 4, pp. 1740–1745, Apr.

1974.

[47] U. Koster, D. R. Campbell, and K. N. Tu, “Contact Reactions Between Amorphous

Silicon and Single-Crystal Metallic Films,”Thin Solid Films, vol. 53, no. 2, pp. 129–

134, Sept. 1978.

[48] M. J. Thompson, R. J. Nemanich, and C. C. Tsai, “Schottky Barrier Amorphous-

Crystalline Interface Formation,”Surface Science, vol. 132, no. 1-3, pp. 250–263,

Sept. 1983.

[49] L. Hultman, A. E. Robertsson, H. T. G. Hentzell, I. Engstrom, and P. A. Psaras, “Al-

Doped and Sb-Doped Polycrystalline Silicon Obtained by Means of Metal-Induced

Crystallization,” Journal of Applied Physics, vol. 62, no. 9, pp. 3647–3655, Nov.

1987.

[50] E. Nygren, A. P. Pogany, K. T. Short, J. S. Williams, R. G. Elliman, and J. M. Poate,

“Impurity-Stimulated Crystallization and Diffusion in Amorphous Silicon,”Applied

Physics Letters, vol. 52, no. 6, pp. 439–441, Feb. 1988.

[51] C. Hayzelden and J. L. Batstone, “Silicide Formation and Silicide-Mediated Crys-

tallization of Nickel Implanted Amorphous Silicon Thin Films,”Journal of Applied

Physics, vol. 73, no. 12, pp. 8279–8289, June 1993.

Bibliography 97

[52] S. W. Lee, T. H. Ihn, and S. K. Joo, “Low Temperature Dopant Activation and its

Application to Polysilicon Thin Film Transistors,”Applied Physics Letters, vol. 69,

no. 3, pp. 380–382, July 1996.

[53] G. Liu and S. J. Fonash, “Polycrystalline Silicon Thin Film Transistors on Corning

7059 Glass Substrates Using Short Time, Low-Temperature Processing,”Applied

Physics Letters, vol. 62, no. 20, pp. 2554–2556, May 1993.

[54] S. W. Lee, T. H. Ihn, and S. K. Joo, “Fabrication of High-Mobility P-Channel Poly-Si

Thin Film Transistors by Self-Aligned Metal-Induced Lateral Crystallization,”IEEE

Electron Device Letters, vol. 17, no. 8, pp. 407–409, Aug. 1996.

[55] H. Wang, M. Chan, S. Jagar, V. M. C. Poon, M. Qin, Y. Wang, and P. K. Ko, “Su-

per Thin-Film Transistor with SOI CMOS Performance Formed by a Novel Grain

Enhancement Method,”IEEE Transactions on Electron Devices, vol. 47, no. 8, pp.

1580–1586, Aug. 2000.

[56] K. N. Tu, J. W. Mayer, and L. C. Feldman,Electronic Thin Film Science for Electrical

Engineers and Materials Scientists, p. 274, Macmillan Publishing Company, New

York, NY, 1992.

[57] Y. Kawazu, H. Kudo, S. Onari, and T. Arai, “Low-Temperature Crystallization of

Hydrogenated Amorphous Silicon Induced by Nickel Silicide Formation,”Japanese

Journal of Applied Physics, vol. 29, no. 12, pp. 2698–2704, Dec. 1990.

[58] Z. Jin, K. Moulding, H. S. Kwok, and M. Wong, “The Effects of Extended Heat

Treatment on Ni Induced Lateral Crystallization of Amorphous Silicon Thin Films,”

IEEE Transactions on Electron Devices, vol. 46, no. 1, pp. 78–82, Jan. 1999.

98 Bibliography

[59] M. Wong, Z. Jin, G. A. Bhat, P. C. Wong, and H. S. Kwok, “Characterization of the

MIC/MILC Interface and its Effects on the Performance of MILC Thin-Film Transis-

tors,” IEEE Transactions on Electron Devices, vol. 47, no. 5, pp. 1061–1067, May

2000.

[60] U. Koster, “Crystallization of Amorphous Silicon Films,”Physica Status Solidi A,

vol. 48, no. 2, pp. 313–321, Aug. 1978.

[61] K. Zellama, P. Germain, S. Squelard, J. C. Bourgoin, and P. A. Thomas, “Crys-

tallization in Amorphous Silicon,”Journal of Applied Physics, vol. 50, no. 11, pp.

6995–7000, Nov. 1979.

[62] R. B. Iverson and R. Reif, “Recrystallization of Amorphized Polycrystalline Silicon

Films on SiO2: Temperature Dependence of the Crystallization Parameters,”Journal

of Applied Physics, vol. 62, no. 5, pp. 1675–1681, Sept. 1987.

[63] W. Moffatt, The Handbook of Binary Phase Diagrams, vol. V, Genium Publishing

Corp., Schenectady, NY, 1984.

[64] T. H. Ihn, J. W. Shin, B. I. Lee, and S. K. Joo, “Low Temperature Activation of

Dopants by Metal Induced Crystallization,”Journal of the Korean Institute of Telem-

atics and Electronics, vol. 34D, no. 5, pp. 45–51, May 1997.

[65] H. J. Cho, P. B. Griffin, and J. D. Plummer, “Cross-Sectional TEM Sample Prepa-

ration Using E-beam Lithography and Reactive Ion Etching,” in1997 MRS Spring

Meeting, San Francisco, CA, Apr. 1997, p. abstract Z2.18.

[66] J. Gu, S. Y. Chou, N. Yao, H. Zandbergen, and J. K. Farrer, “Single-Crystal Si Formed

on Amorphous Substrate At Low Temperature by Lithography Constrained Single

Bibliography 99

Seeding in Nickel Induced Lateral Crystallization,” in2002 MRS Spring Meeting,

San Francisco, CA, Apr. 2002, p. abstract A22.4.

[67] R. M. Burger and R. P. Donovan,Fundamentals of Silicon Integrated Device Tech-

nology, vol. 1, pp. 232–233, Prentice Hall, Englewood Cliffs, NJ, 1967.

[68] S. M. Sze,Physics of Semiconductor Devices, p. 21, John Wiley & Sons, New York,

NY, 1981.

[69] T. C. Yang, P. Sachdev, and K. C. Saraswat, “Dependence of Fermi Level Positions at

Gate and Substrate on the Reliability of Ultrathin MOS Gate Oxides,”IEEE Trans-

actions on Electron Devices, vol. 46, no. 7, pp. 1457–1463, July 1999.

[70] O. Evrard, P. Burger, F. Broz, L. Van Buul, M. Keters, and J. Verplancke, “MOS

Transient: A Powerful Analysis Technique for In-Process Monitoring of Nuclear De-

tectors,”Nuovo Cimento A, vol. 112A, no. 11, pp. 1293–1306, Nov. 1999.

[71] V. Subramanian and K. C. Saraswat, “Laterally Crystallized Polysilicon TFTs Using

Patterned Light Absorption Masks,” in55th Device Research Conference Digest, Fort

Collins, CO, June 1997, pp. 54–55.

[72] V. Subramanian and K. C. Saraswat, “A Novel Technique for 3-D Integration: Ge

Seeded Laterally Crystallized TFTs,” in1997 Symposium on VLSI Technology Digest,

Kyoto, Japan, June 1997, pp. 97–98.

[73] H. Kim, J. G. Couillard, and D. G. Ast, “Kinetics of Silicide-Induced Crystallization

of Polysilicon Thin-Film Transistors Fabricated from Amorphous Chemical-Vapor

Deposition Silicon,”Applied Physics Letters, vol. 72, no. 7, pp. 803–805, Feb. 1998.

100 Bibliography

[74] G. A. Bhat, Z. H. Jin, H. S. Kwok, and M. Wong, “The Effects of the MILC/MIC

Interface on the Performance of MILC-TFTs,” in56th Device Research Conference

Digest, Charlottesville, VA, June 1998, pp. 110–111.

[75] S. M. Sze,Physics of Semiconductor Devices, p. 71, John Wiley & Sons, New York,

NY, 1981.

[76] T. Ghani, S. Ahmed, P. Aminzade, J. Bielefeld, P. Charvat, C. Chu, M. Harper,

P. Jacob, C. Jan, J. Kavalieros, C. Kenyon, R. Nagisetty, P. Packan, J. Sebastian,

M. Taylor, J. Tsai, S. Tyagi, S. Yang, and M. Bohr, “100 nm Gate Length High Per-

formance/Low Power CMOS Transistor Structure,” in1999 International Electron

Devices Meeting Technical Digest, Washington, DC, Dec. 1999, pp. 415–418.

[77] K. Nakazawa, “Recrystallization of Amorphous Silicon Films Deposited by Low-

Pressure Chemical Vapor Deposition from Si2H6 Gas,” Journal of Applied Physics,

vol. 69, no. 3, pp. 1703–1706, Feb. 1991.

[78] K. R. Olasupo and M. K. Hatalis, “Leakage Current Mechanism in Sub-micron

Polysilicon Thin Film Transistors,” IEEE Transactions on Electron Devices, vol.

43, no. 8, pp. 1218–1223, Aug. 1996.

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