40 High Frequency Electronics

High Frequency Design

CLASS-E AMPLIFIERS

Design of Input MatchingNetworks for Class-E RF Power Amplifiers

Firas Mohammed Ali Al-RaieThe Polytechnic Higher Institute

Class-E power amp-lifiers have highefficiency, which

makes them attractive inmodern wireless mobilecommunication systems.There are several tech-niques and approachesdeveloped solely to design

the output load networks of such amplifiers toshape the RF power device’s output voltageand current for minimum power loss.However, little attention is brought to thedesign of the input matching network and tothe device bias conditions, with their effects onthe overall circuit performance. This paperattempts to discuss these topics through a sys-tematic design and simulation approach for atypical 5 watt class-E power amplifier operat-ing at 150 MHz.

IntroductionSeveral methods have been developed for

the design of the load network for class-E RFpower amplifier. Among those are the shuntcapacitance [1], shunt inductance [2], finiteDC feed inductance [3], and parallel circuit [4]techniques. The most popular configuration isthe shunt capacitance technique due to itssimplicity and designability, which meansthat when the amplifier is built as designed, itworks as expected [1].

The schematic diagram of the class-Epower amplifier with shunt capacitance con-figuration is presented in Figure 1. In this cir-cuit LG and LD represent the gate and drainbias RF chokes respectively, CB is a DC block-ing capacitor, Cb1 and Cb2 are bypass capaci-tors, VGG is the gate bias voltage, VDD is the

drain supply voltage, C is the capacitor shunt-ing the active device Q1, Lo and Co constitutea series resonant circuit tuned at the operat-ing frequency, and R is the optimum resis-tance seen by the load network for therequired output power. The active device Q1(power MOSFET in this case) operates as anON/OFF switch.

In class-E power amplifier circuit, efficien-cy is maximized by minimizing power dissipa-tion in the active device, while providing thedesired output power. The circuit can bearranged so that high drain voltage and highdrain current don’t exist at the same time.

For idealized class-E power amplifier oper-ation, it is necessary to provide the followingoptimum conditions for the drain voltage vD(t)across the power MOSFET just prior to thestart of the device’s ON state at the momentt = T, where T is the period of the input driv-ing signal [5]:

(1)V tD t T( ) == 0

Class-E power ampliferdesign usually emphasizesoutput network design, but

this article examines ampli-fier performance when anuntuned input is replacedwith a matching network

Figure 1 · Typical class-E power amplifierwith shunt capacitance configuration.

From January 2011 High Frequency ElectronicsCopyright © 2011 Summit Technical Media, LLC

42 High Frequency Electronics

High Frequency Design

CLASS-E AMPLIFIERS

(2)

Equations (1) and (2) state that the drain voltageshould be zero at the turn-on moment, and that the slopeof this waveform is zero at the same moment.

Load Network Design EquationsThe load network of class-E power amplifier is not

intended to provide a conjugate match to the transistoroutput impedance. Design equations for the load networkelements (C, C0, L0, and R) can be derived by writing timedomain equations for the voltage vD(t) at the drain of theRF power MOSFET when it is OFF, and the current iD(t)passing through the RF device when it is ON. A set ofsimultaneous differential equations can be formedaccording to the necessary conditions (1) and (2) andsolved to determine the network elements [6].

Nathan Sokal, the inventor of this amplifier, hasdeveloped explicit form equations to calculate the valuesof the network elements at any output power and loadedquality factor QL.

These equations are formulated as [7]:

(3)

(4)

(5)

(6)

where Pout is the required output power, and ω is theoperating frequency.

The value of QL can be selected based on a trade-offbetween operating bandwidth and harmonic distortion ofthe output signal.

Typical Class-E Power Amplifier DesignFor the clarification of the goals of this paper, a power

amplifier circuit has been designed and simulated usinga commercial microwave CAD program. Design specifica-tions of the amplifier are to achieve an output RF powerof 5 W from an input driving level of 0.5 W, and drain effi-ciency of more than 65% at an operating frequency of150 MHz.

The following sections describe a step-by-step designprocedure with the simulated results obtained from theAgilent’s ADS microwave circuit analysis program.

RF Power Device Selection and CharacterizationThe first step of the amplifier design procedure is the

selection of the RF power transistor. For this design, theMotorola’s power MOSFET MRF134 has been chosen.This device is capable of delivering 5 W at 400 MHz witha typical power gain of more than 10 dB. It operates froma 28 VDC supply and has a typical drain-to-source break-down voltage of 65 V. The RF transistor library of thecomputer program ADS contains a SPICE model for thistransistor which simplifies the simulation process. Thesimulated input DC characteristic (ID versus VGS) of thepower MOSFET is shown in Figure 2 with VDS = 28 V. Itcan be shown from this curve that the gate threshold volt-age VGS(th) = 3 V. On the other hand, Figure 3 presents thesimulated output DC characteristic (ID versus VDS) atseveral gate voltages. The drain ON resistance RD(on) canbe estimated from Figure 3 as 12.5 Ω. This relativelylarge value of RD(on) will cause a reduction in amplifier’sefficiency due to the dissipated power at the drain duringthe ON period of the power device.

Calculation of the Load Network ElementsThe design procedure begins by calculating the com-

ponent values of the load network using equations (3) to(6). For output power Pout = 5 W, operating frequency f =

LQ R

oL= .ω

CR Q Q Lo

L L D

=−

⎛

⎝⎜

⎞

⎠⎟ +

−⎛

⎝⎜

⎞

⎠⎟ −1 1

0 1048231

1 014681 7879

0 22ω ω.

..

.

CR Q Q LL L D

= + −⎛

⎝⎜

⎞

⎠⎟ +1

5 446581

0 91424 1 03175 0 62 2.

. . ..ω ω

RVP Q Q

DD

out L L

=⎛

⎝⎜

⎞

⎠⎟ ⋅ − −

⎛

⎝⎜

⎞

⎠⎟0 5768 1

0 451759 0 4024442

2.. .

dv tdtD

t T

( ) ==

0

Figure 2 · ID versus VGS for theMRF134 power MOSFET.

Figure 3 · Simulated drain DC char-acteristics of the MRF134 powerMOSFET.

Figure 4 · Configuration of the out-put matching network.

44 High Frequency Electronics

High Frequency Design

CLASS-E AMPLIFIERS

150 MHz, loaded quality factor QL = 5, and drain powersupply VDD = 28 V, the calculated values of the elementsof the load network are:

R = 80 Ω, C = 3 pF, C0 = 3 pF, and L0 = 430 nH.

The output capacitance of the RF device, Cout, is mea-sured as 9.7 pF from the device data sheet. This meansthat it is greater than the required value of the shuntcapacitance. The excess value of 6.3 pF should be tunedout by part of the drain bias RF choke.

Design of the Output Matching NetworkAn output matching network is needed to transform

the 50 Ω amplifier impedance into the required load resis-tance, which is set to be 80 Ω. This network has beendesigned with the aid of an immittance Smith chart, andis implemented in a T-section configuration, as shown inFigure 4.

In addition to the transformation function of the out-put matching network, it also can be used to reduce theharmonic content of the output RF signal. Figure 5 showsthe simulated input return loss of this network, while

Figure 6 presents its insertion lossversus frequency.

Design of the Biasing NetworkThe biasing network consists of

the drain and gate RF chokes, bypasscapacitors, DC blocking capacitors, inaddition to the gate and drain biasvoltages. For 50% duty cycle opera-

tion, the transistor is biased at the threshold point, whichmeans that VGG = VGS(th) = 3 V. This bias point actuallycorresponds to class-B mode.

Based upon the previous calculations, the schematicdiagram of the amplifier circuit is shown in Figure 7.

Amplifier Performance SimulationThe designed amplifier circuit has been simulated

using ADS 2006A. With a single tone input signal of 0.5 Wpower level and an operating frequency of 150 MHz, theRF device’s drain voltage and current are sketched asdepicted in Figure 8. As shown from this plot, the peakvalues of drain voltage and current don’t exist simultane-ously which minimizes the device’s power loss. However,at the ON time of the RF signal, the drain voltage is about3.5V due to the ON resistance at the drain, RD(on). Thismay degrade the overall efficiency of the circuit. Duringthe OFF interval of the RF signal, a negative currentflows through the power MOSFET’s output capacitanceCout.

In Figure 9 the output signal waveform is plotted,while its spectrum is displayed in Figure 10. It is obviousthat harmonics are reduced to acceptable levels due to the

Figure 5 · Input return loss of theoutput matching network.

Figure 6 · Insertion loss of the out-put matching network.

Figure 8 · Simulated drain voltageand current waveforms of thepower MOSFET.

Figure 7 · The designed class-E power amplifier without the input match-ing network.

filtering effect of the load and matching networks.In order to display the power amplifier’s performance

characteristics, a sweep of the input power level has beencarried out from 10 to 30 dBm at the operating frequency.Figure 11 shows a sketch of the output power versusinput power. The output power is obtained from:

(7)

where VL and IL are the peak values of the fundamentalcomponents of load voltage and current respectively. Theoutput power is about 36 dBm at an input level of27 dBm.

Figure 12 presents the operating power gain of theamplifier, Gp, versus input power. The power gain is cal-culated from:

(8)

Notice that the power gain is about 9.0 dB at an inputpower level of 27 dBm.

Finally, Figure 13 displays a plot of the amplifier’s DCto RF efficiency with input power. The amplifier efficien-cy is about 71.1% at an input power of 27 dBm.

The efficiency of the amplifier circuit has been evalu-ated from:

(9)

where Pdc is the DC power consumed by the RF deviceand is obtained from:

η = PP

out

dc

G dB P dBm P dBmp out in( ) = ( ) − ( )

P real V Iout L L= ( )0 5. . *

Figure 9 · Simulated waveform ofthe load voltage.

Figure 10 · Power spectrum of theoutput signal.

Figure 11 · Amplifier output powerversus input power.

Figure 12 · Power gain versus inputpower.

Figure 13 · Simulated efficiencyversus input power.

Figure 14 · Variation of the largesignal MOSFET input impedancewith input signal level.

46 High Frequency Electronics

High Frequency Design

CLASS-E AMPLIFIERS

(10)

where IDD is the DC component of thedrain current.

Input Matching Network DesignThe input matching network can

be designed to match the large signalinput impedance of the RF powerdevice with the 50 Ω sourceimpedance. Therefore, the large sig-nal input impedance of the RF tran-sistor should be estimated at thenominal input power, operating fre-quency, and bias voltages with theexistence of the load and outputmatching networks.

The large signal input impedanceof the power transistor consists of twoparts, resistance Rin and reactanceXin:

(11)

Rin and Xin can be estimated from:

(12)

(13)

where Vin is the fundamental compo-nent of the input voltage at the gateof the MOSFET, and Iin is the funda-mental component of the currententering the gate of the transistor. Iincan be estimated using a currentprobe with the aid of ADS simulationcapabilities. Figure 14 shows a sketchof the large signal input impedance ofthe power device versus input power.

As shown from the plot in Figure14, the input impedance is capacitive.

At an input power of 27 dBm (0.5 W),the input impedance is approximate-ly 12 –j45 Ω. The input matching net-work can thus be designed to matchthis value with the 50 Ω sourceimpedance. An immittance Smithchart has been used to construct anL-section matching network graphi-cally. Figure 15 presents the finalpower amplifier circuit after incorpo-rating the input matching network.

There is no doubt that the inputmatching network improves the netinput power delivered to the RFdevice. The amplifier circuit was sim-ulated again after adding the inputmatching circuit using ADS. The out-put power of the circuit is displayedin Figure 16 with a sweep of inputpower from 10 to 30 dBm. As shownfrom Figure 16, there is a slightincrease in output power being

X imag V Iin in in= ( )/

R real V Iin in in= ( )/

Z R jXin in in= +P V Idc DD DD= .

Figure 15 · The designed class E power amplifier after adding the input matching network.

Figure 16 · The simulated outputpower versus input power for thefinal amplifier.

Figure 17 · Operating power gainversus input power.

Figure 18 · Amplifier efficiency ver-sus input power.

48 High Frequency Electronics

High Frequency Design

CLASS-E AMPLIFIERS

38.8 dBm for an input power of27 dBm. The power gain is plotted inFigure 17, and becomes equal to9.8 dB at the nominal input power.The DC to RF efficiency is sketchedin Figure 18 versus input power. Theefficiency becomes 71.8% at an inputpower level of 27 dBm. However, noattempts have been made to optimizethe component values of the inputmatching network for better perfor-mance characteristics.

Table 1 summarizes the perfor-mance of the amplifier before andafter adding the input network.

ConclusionThe performance of Class E RF

power amplifier with a traditionalshunt capacitance load network hasbeen studied thoroughly. It wasshown that the high efficiency opera-tion of such amplifiers is determinedmainly by the output load network.However, with an accurate and prop-er design of the input matching net-work, the performance characteris-tics of the amplifier can be improved.This article has presented and dis-cussed the main guidelines for syn-thesizing the input matching circuitsfor this type of RF amplifier toachieve the improved performance.

AcknowledgementI would like to express my deep

gratitude to Dr. Andrei Grebennikovfor his continuous advice and usefulsuggestions in high efficiency poweramplifier analysis, and also for pro-viding me with some technicalpapers and e-books in the field of RFpower amplifiers.

References1. N.O. Sokal and A.D. Sokal,

“Class E- A New Class of High-Efficiency Tuned Single-EndedSwitching Power Amplifiers,” IEEEJ. Solid-State Circuits, Vol. SC-10,June 1975, pp. 168-176.

2. M.K. Kazimierczuk, “Class ETuned Power Amplifier with ShuntInductor,” IEEE J. Solid-State

Circuit, Vol. SC-16, February 1981,pp. 2-7.

3. R.E. Zulinski and J.W.Steadman, “Class E Power Amplifiersand Frequency Multipliers withFinite DC-Feed Inductance,” IEEETrans. Circuits and Systems, Vol.CAS-34, September 1987, pp. 1074-1087.

4. A. Grebennikov, “Switched-Mode RF and Microwave Parallel-Circuit Class E Power Amplifiers,”Int. J. RF and Microwave Computer-Aided Eng., Vol. 14, Jan/Feb 2004, pp.21-35.

5. A. Grebennikov, “Load NetworkDesign Techniques for Class E RFand Microwave Amplifiers,” HighFrequency Electronics, Vol. 3, July2004, pp. 18-32.

6. A. Grebennikov and N.O. Sokal,Switchmode RF Power Amplifiers,Elsevier Inc., 2007, Chapter 5.

7. N.O. Sokal, “Class-E RF PowerAmplifiers,” QEX, Jan/Feb 2001, pp.9-19.

Author InformationFiras Mohammed Ali Al-Raie is

an RF engineer in the Department ofElectronic Engineer at The Polytech-nic Higher Institute of Yefren, Libya.He has also worked as a consultantengineer and as lecturer at theUniversity of Al-Jabal Al-Gharbi,Jado, Libya. He has a BSc Degree inElectrical Engineering and an MScDegree in Electrical Engineering/Electronics and Communication fromthe University of Baghdad.

He can be reached by e-mail atfiras@ieee.org

Engineers:

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Before After

Output Power 36 dBm 36.8 dBm

Power Gain 9.0 dB 9.8 dB

Efficiency 71.1% 71.8%

Pin = 0.5W (27 dBm), f0 = 150 MHz

Table 1 · Performance comparisonbefore and after adding the inputmatching network.