20477704 Hardware Description Language HDL Introduction to HDL
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HDL Lab Dept. of Instumentation Technology
R.Y.M.E.C, BLY Page 1
BY
SIDDALINGESH.G
LECTURER, RYMEC, BELLARY
PART-A
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HDL Lab Dept. of Instumentation Technology
R.Y.M.E.C, BLY Page 2
Experiment No. 1
Aim: Write VHDL and verilog codes to realize all the logic gates.
VHDL Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity gates is
port ( ain, bin : in std_logic;
op_not, op_and, op_or : out std_logic;
op_nand, op_nor : out std_logic;
op_xor, op_xnor: out std_logic );
end gates;
architecture logic_gates of gates is
begin
op_not<= not ain;
op_and<= ain and bin;
op_or<= ain or bin;
op_nand<= ain nand bin;
op_nor<= ain nor bin;
op_xor<= ain xor bin;
op_xnor<= ain xnor bin;
end logic_gates;
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HDL Lab Dept. of Instumentation Technology
R.Y.M.E.C, BLY Page 3
BASIC GATES
Logic diagram
AND: Y= AB OR: Y=A+B
NOT: Y= A’ NAND: Y= (AB)’=A’+B’
NOR: Y= (A+B)’= A’+B’ EXCLUSIVE OR: Y=AӨB
EXCLUSIVE NOR: Y=AOB
TRUTH TABLE
INPUTS OUTPUTS
A B NOT(A) AND NAND OR NOR EXOR EXNOR
0 0 1 0 1 1 0 0 1
AND2
12
3
AY
B AY
B
OR2
12
3
YA
INV
B
NAND2
12
3
AY
YB
NOR2
12
3
AY
XOR2
12
3
A
B
A
B
XNOR2
12
3
Y
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HDL Lab Dept. of Instumentation Technology
R.Y.M.E.C, BLY Page 4
0 1 1 0 1 0 1 1 0
1 0 0 0 1 0 1 1 0
1 1 0 1 0 0 1 0 1
Verilog Code
module (ain, bin, op_or, op_and, op_not, op_xor, op-xnor, op_nand, op_nor);
input ain, bin;
output op_or, op_and, op_not, op_xor, op-xnor, op_nand, op_nor;
assign op_or = ain|bin;
assign op_and = ain & bin;
assign op_not = ~ ain
assign op_xor = (ain ^ bin);
assign op_xnor = ~ (ain ^ bin);
assign op_nand = ~ (ain & bin);
assign op_nor =~ (ain | bin);
endmodule
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HDL Lab Dept. of Instumentation Technology
R.Y.M.E.C, BLY Page 5
Experiment No. 2
Aim: Write VHDL and verilog codes for the following combinational designs.
a.VHDL code for 2 to 4 decoder.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity DECODER is
Port ( DIN : in std_logic_vector(1 downto 0);
DOUT : out std_logic_vector(3 downto 0));
end DECODER;
architecture Behavioral of DECODER is
begin
process(DIN)
begin
case DIN is
when "00" => DOUT <= "0001";
when "01" => DOUT <= "0010";
when "10" => DOUT <= "0100";
when "11" => DOUT <= "1000";
when others => null;
end case;
end process;
end Behavioral;
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HDL Lab Dept. of Instumentation Technology
R.Y.M.E.C, BLY Page 6
2 TO 4 DECODER
Block Diagram of Decoder
Logic Diagram of 2:4 Decoder
TRUTH TABLE
EN Inputs Output
Sel(1) Sel(0) D
1 X X 0
0 0 0 D0
0 0 1 D1
0 1 0 D2
D3
U6
NAND3
1234
D0
D2
EN
U5
NAND3
1234
SEL(1)
INST1
INV
D1
SEL(0)
INST2
INV
U8
NAND3
1234
U7
NAND3
1234
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HDL Lab Dept. of Instumentation Technology
R.Y.M.E.C, BLY Page 7
a.Verilog Code for 2 to 4 decoder.
module decode_24(DIN,DOUT);
input [1:0] DIN;
output [3:0] DOUT;
reg [3:0] DOUT;
always @(DIN)
begin
case (DIN)
2'b00 : DOUT=4'b0001;
2'b01 : DOUT=4'b0010;
2'b10 : DOUT=4'b0100;
default: DOUT=4'b1000;
endcase
end
endmodule
0 1 1 D3
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HDL Lab Dept. of Instumentation Technology
R.Y.M.E.C, BLY Page 8
b.VHDL code for 8 to 3 encoder with priority.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity enwp is
port ( din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(2 downto 0));
end enwp;
architecture enwp_arch of enwp is
begin
process(din)
begin
case din is
when "00000001" => dout<="000";
when "00000010" => dout<="001";
when "00000100" => dout<="010";
when "00001000" => dout<="011";
when "00010000" => dout<="100";
when "00100000" => dout<="101";
when "01000000" => dout<="110";
when "10000000" => dout<="111";
when others => dout<="zzz";
end case;
end process;
end enwp_arch;
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HDL Lab Dept. of Instumentation Technology
R.Y.M.E.C, BLY Page 9
8 TO 3 ENCODER
Block Diagram of priority encoder
TRUTH TABLE(WITH PRIORITY)
E X(7) X(6) X(5) X(4) X(3) X(2) X(1) X(0) GS EO Y(2) Y(1) Y(0)
1 X X X X X X X X 1 1 1 1 1
0 1 1 1 1 1 1 1 1 1 0 1 1 1
Y(2 0 )
GS
EO
X( 7 0)
8:3
Encoder
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HDL Lab Dept. of Instumentation Technology
R.Y.M.E.C, BLY Page 10
b.Verilog code for 8 to 3 encoder with priority.
module ENCODE (DIN, DOUT);
input [7:0] DIN;
output [2:0] DOUT;
reg [2:0] DOUT;
always @ ( DIN )
begin
casex ( DIN )
8'b00000001 : DOUT = 3'b000;
8'b0000001x : DOUT = 3'b001;
8'b000001xx : DOUT = 3'b010;
8'b00001xxx : DOUT = 3'b011;
8'b0001xxxx : DOUT = 3'b100;
8'b001xxxxx : DOUT = 3'b101;
8'b01xxxxxx : DOUT = 3'b110;
8'b1xxxxxxx : DOUT = 3'b111;
endcase
end
endmodule
0 1 1 1 1 1 1 1 0 0 1 1 1 1
0 1 1 1 1 1 1 0 X 0 1 1 1 0
0 1 1 1 1 1 0 X X 0 1 1 0 1
0 1 1 1 1 0 X X X 0 1 1 0 0
0 1 1 1 0 X X X X 0 1 0 1 1
0 1 1 0 X X X X X 0 1 0 1 0
0 1 0 X X X X X X 0 1 0 0 1
0 0 X X X X X X X 0 1 0 0 0
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HDL Lab Dept. of Instumentation Technology
R.Y.M.E.C, BLY Page 11
b. VHDL code for 8 to 3 encoder without priority.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity encwopri is
port (d_in: in std_logic_vector (7 downto 0) ;
d_out: out std_logic_vector (2 downto 0));
end entity encwopri;
architecture encwopri_arch of encwopri is
begin
process(d_in)
begin
if d_in= "00000001" then
d_out<= "000";
elsif d_in=”00000010” then
d_out<= "001";
elsif d_in=”00000100” then
d_out<= "010";
elsif d_in=”00001000” then
d_out<= "011";
elsif d_in=”00010000” then
d_out<= "100";
elsif d_in=”00100000” then
d_out<= "101";
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HDL Lab Dept. of Instumentation Technology
R.Y.M.E.C, BLY Page 12
elsif d_in=”01000000” then
d_out<= "110";
else d_out<=”111”;
end if;
end process;
end architecture encwopri_arch;
TRUTH TABLE(WITHOUT PRIORITY)
E X(7) X(6) X(5) X(4) X(3) X(2) X(1) X(0) GS EO Y(2) Y(1) Y(0)
1 X X X X X X X X 1 1 1 1 1
0 1 1 1 1 1 1 1 1 1 0 1 1 1
0 1 1 1 1 1 1 1 0 0 1 1 1 1
0 1 1 1 1 1 1 0 1 0 1 1 1 0
0 1 1 1 1 1 0 1 1 0 1 1 0 1
0 1 1 1 1 0 1 1 1 0 1 1 0 0
0 1 1 1 0 1 1 1 1 0 1 0 1 1
0 1 1 0 1 1 1 1 1 0 1 0 1 0
0 1 0 1 1 1 1 1 1 0 1 0 0 1
0 0 1 1 1 1 1 1 1 0 1 0 0 0
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HDL Lab Dept. of Instumentation Technology
R.Y.M.E.C, BLY Page 13
b.Verilog code for 8 to 3 encoder without priority.
module ENCODE(DIN,DOUT);
input [7:0] DIN;
output [2:0] DOUT;
reg [2:0] DOUT;
always @(DIN)
begin
case (DIN)
8'b00000001 : DOUT = 3'b000;
8'b00000010 : DOUT = 3'b001;
8'b00000100 : DOUT = 3'b010;
8'b00001000 : DOUT = 3'b011;
8'b00010000 : DOUT = 3'b100;
8'b00100000 : DOUT = 3'b101;
8'b01000000 : DOUT = 3'b110;
8'b10000000 : DOUT = 3'b111;
endcase
end
endmodule
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HDL Lab Dept. of Instumentation Technology
R.Y.M.E.C, BLY Page 14
c. VHDL code for 8 to 1 Multiplexer.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux_81 is
Port ( inp : in std_logic_vector(7 downto 0);
sel : in std_logic_vector(2 downto 0);
outp: out std_logic);
end mux_81;
architecture mux_arch of mux_81 is
begin
process (inp,sel)
begin
case sel is
when "000" => outp <= inp(0);
when "001" => outp <= inp(1);
when "010" => outp <= inp(2);
when "011" => outp <= inp(3);
when "100" => outp <= inp(4);
when "101" => outp <= inp(5);
when "110" => outp <= inp(6);
when others => outp <= inp(7);
end case;
end process;
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HDL Lab Dept. of Instumentation Technology
R.Y.M.E.C, BLY Page 15
end mux_arch;
8 TO 1 MUX
Block Diagram of 8:1 Mux logic diagram
TRUTH TABLE
U7
AND5
1
23456
SEL(0)
D0
U1
AND5
1
23456
SEL(1)
D7
Y
EN
D3
INV1
D5
U2
AND5
1
23456
U8
AND5
1
23456
U3
AND5
1
23456
U5
AND5
1
23456
U4
AND5
1
23456
INV3
D2
D1
D4
D6
U9
OR8
1
2345
6789
U6
AND5
1
23456
INV2
SEL(2)
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HDL Lab Dept. of Instumentation Technology
R.Y.M.E.C, BLY Page 16
EN CONTROL INPUTS OUTPUT(Y)
(Selected
Inputs)
SEL(3) SEL(3) SEL(3)
0 0 0 0 D0
1 0 0 1 D1
1 0 1 0 D2
1 0 1 1 D3
1 1 0 0 D4
1 1 0 1 D5
1 1 1 0 D6
1 1 1 1 D7
c. Verilog code for 8 to 1 Multiplexer.
module mux_81(inp,sel,outp);
input [7:0] inp;
input [2:0] sel;
output outp;
reg outp;
always @ (sel,inp)
begin
case(sel)
3'b000 : outp = inp[0];
3'b001 : outp = inp[1];
3'b010 : outp = inp[2];
3'b011 : outp = inp[3];
3'b100 : outp = inp[4];
3'b101 : outp = inp[5];
3'b110 : outp = inp[6];
default : outp = inp[7];
endcase
end
endmodule
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HDL Lab Dept. of Instumentation Technology
R.Y.M.E.C, BLY Page 17
d.VHDL code for 4-bit Binary to Gray code converter.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bin_to_gry is
Port ( b3,b2,b1,b0 : in std_logic;
g3,g2,g1,g0 : out std_logic);
end bin_to_gry;
architecture Behavioral of bin_to_gry is
begin
g3<=b3;
g2<=b2 xor b3;
g1<=b1 xor b2;
g0<=b0 xor b1;
end Behavioral;
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HDL Lab Dept. of Instumentation Technology
R.Y.M.E.C, BLY Page 18
BINARY TO GRAY
TRUTH TABLE
Decimal Binary B3B2B1B0
Gray G3G2G1G0
0 0000 0000
1 0001 0001
2 0010 0011
B0
G3
G0
B2
G1
G2
U2
XOR2
12
3
U1
XOR2
12
3
B1
B3U3
XOR2
12
3
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HDL Lab Dept. of Instumentation Technology
R.Y.M.E.C, BLY Page 19
3 0011 0010
4 0100 0110
5 0101 0111
6 0110 0101
7 0111 0100
8 1000 1100
9 1001 1101
10 1010 1111
11 1011 1110
12 1100 1010
13 1101 1011
14 1110 1001
15 1111 1000
d.Verilog code for 4-bit Binary to Gray code converter.
module bin_to_gry(b,g);
input [3:0]b;
output [3:0]g;
assign g[3]=b[3];
assign g[2]=b[3]^b[2];
assign g[1]=b[2]^b[1];
assign g[0]=b[1]^b[0];
endmodule
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HDL Lab Dept. of Instumentation Technology
R.Y.M.E.C, BLY Page 20
e. VHDL code for 1 to 8 Demultiplexer.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity dmux_18 is
Port ( din : in std_logic;
sel : in std_logic_vector(2 downto 0);
dout : out std_logic_vector(7 downto 0));
end dmux_18;
architecture Behavioral of dmux_18 is
begin
process (din,sel)
begin
case sel is
when "000" => dout(0)<=din;
when "001" => dout(1)<=din;
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HDL Lab Dept. of Instumentation Technology
R.Y.M.E.C, BLY Page 21
when "010" => dout(2)<=din;
when "011" => dout(3)<=din;
when "100" => dout(4)<=din;
when "101" => dout(5)<=din;
when "110" => dout(6)<=din;
when others => dout(7)<=din;
end case;
end process;
end Behavioral;
1 TO 8 DEMUX
TRUTH TABLE
SEL(2)
D7
U5
AND5
1
23456
U4
AND5
1
23456
U2
AND5
1
23456
EN
D4
D5
INV3
SEL(0)
U7
AND5
1
23456
SEL(1)
Y
U3
AND5
1
23456
D6
U1
AND5
1
23456
D0
D1
U6
AND5
1
23456
D2
INV2
D3
INV1
U8
AND5
1
23456
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HDL Lab Dept. of Instumentation Technology
R.Y.M.E.C, BLY Page 22
LOGIC DIAGRAM
EN CONTROL INPUTS OUTPUTS
SEL(3) SEL(3) SEL(3)
0 X X X 0
1 0 0 0 D0=Y
1 0 0 1 D1=Y
1 0 1 0 D2=Y
1 0 1 1 D3=Y
1 1 0 0 D4=Y
1 1 0 1 D5=Y
1 1 1 0 D6=Y
1 1 1 1 D7=Y
e. Verilog code for 1 to 8 Demultiplexer.
module dmux_18(din,sel,dout);
input din;
input [2:0] sel;
output [7:0] dout;
reg [7:0] dout;
always @(sel,din)
begin
case (sel)
3'b000 : dout[0]=din;
3'b001 : dout[1]=din;
3'b010 : dout[2]=din;
3'b011 : dout[3]=din;
3'b100 : dout[4]=din;
3'b101 : dout[5]=din;
3'b110 : dout[6]=din;
default : dout[7]=din;
endcase
end
endmodule
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HDL Lab Dept. of Instumentation Technology
R.Y.M.E.C, BLY Page 23
f. VHDL code for 1 bit comparator.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity comparator is
Port ( a,b : in std_logic;
lt, gt,eq:out std_logic);
end comparator;
architecture comp_arch of comparator is
begin
eq <= (a xnor b);
lt <= (not a)and b;
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HDL Lab Dept. of Instumentation Technology
R.Y.M.E.C, BLY Page 24
gt <= a and (not b);
end comp_arch;
4- BIT COMPARATOR
1- BIT COMPARATOR
Logic Diagram
TRUTH TABLE
INV2
AB\Y(A<B)
INV1
A U1
AND2
12
3
A\B
Y(A>B)U2
AND2
12
3
Y(A=B)
B
U3
NOR2
12
3
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HDL Lab Dept. of Instumentation Technology
R.Y.M.E.C, BLY Page 25
Comparing
inputs
Outputs
A B Y=(A>B) Y=(A<B) Y=(A=B)
0 0 0 0 1
0 1 0 1 0
1 0 1 0 0
1 1 0 0 1
f. Verilog code for 1 bit comparator.
module comp(a,b,gt,lt,eq);
input a,b;
output gt,lt,eq;
reg gt,lt,eq;
always @(a,b)
begin
eq = ~(a ^ b);
lt = (~a) & b;
gt = a & (~b);
end
endmodule
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HDL Lab Dept. of Instumentation Technology
R.Y.M.E.C, BLY Page 26
g. VHDL code for 4 bit comparator.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity comparator is
Port ( a,b : in std_logic_vector(3 downto 0);
x,y,z : out std_logic);
end comparator;
architecture Behavioral of comparator is
begin
process (a,b)
begin
x<='0';
y<='0';
z<='0';
if(a<b)then
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HDL Lab Dept. of Instumentation Technology
R.Y.M.E.C, BLY Page 27
x<='1';
elsif (a=b)then
y<='1';
elsif (a>b)then
z<='1';
end if;
end process;
end Behavioral;
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g. Verilog code for 4 bit comparator.
module comparator(a,b,x,y,z);
input [3:0] a,b;
output x,y,z;
reg x,y,z;
always @ (a,b)
begin
4-BIT COMPARATOR
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x = 1'b0;
y = 1'b0;
z = 1'b0;
if ( a<b)
x = 1'b1;
else if (a==b)
y = 1'b1;
else if (a>b)
z = 1'b1;
end
endmodule
Experiment No.3Aim: To write a VHDL and Verilog code to describe the functions of a Full adder using
three modeling styles.
Data flow model
Behavioral model
Structural model
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a.VHDL Code for Full adder using Data Flow model.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FA is
Port ( A,B,CIN : in std_logic;
COUT,SUM : out std_logic);
end FA;
architecture FA_DTFL of FA is
begin
SUM <= (A xor B xor CIN);
COUT <= (A and B) or (B and CIN) or (A and CIN);
end FA_DTFL;
a.Verilog Code for Full adder using Data Flow model.
module FA_DF (A,B,CIN,COUT,SUM);
input A,B,CIN;
output COUT,SUM;
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assign SUM = (A ^ B ^ CIN);
assign COUT = (A & B) | (B & CIN) | (A & CIN);
endmodule
FULL ADDER HALF ADDER
B
U2
AND2
12
3
A(+)BA(+)B(+)C
CARRYU11
AND2
12
3
A
CARRY
SUM
A.B
A
A.B + B.Cin + A.Cin
U3
AND2
12
3
U10
XOR2
12
3SUM
Cin
U5
OR3
1234
U1
XOR3
1234
B
U4
AND2
12
3
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Logic Diagram
TRUTH TABLE
INPUTS OUTPUTS
A B Cin SUM CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
b.VHDL code for full adder using Behavioral model.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FA is
Port (A,B,CIN : in std_logic;
COUT,SUM : out std_logic);
end FA;
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architecture FA_BEHAVE of FA is
begin
process(A,B,CIN)
begin
SUM <= (A xor B xor CIN);
COUT <= (A and B) or (B and CIN) or (A and CIN);
end process;
end FA_BEHAVE;
b.Verilog code for full adder using Behavioral model.
module FA_BEHAVE (A,B,CIN,COUT,SUM);
input A,B,CIN;
output SUM, COUT;
reg SUM,COUT;
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always @(A,B,CIN)
begin
SUM = (A ^ B ^ CIN);
COUT = (A & B) | (B & CIN) | (A & CIN);
end;
endmodule
c.VHDL code for Full adder using structural model.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FULL_ADD is
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Port (A,B,CIN: in std_logic;
SUM,COUT: out std_logic);
end FULL_ADD;
architecture STRUCT_ARCH of FULL_ADD is
component HALF_ADD is
port(A,B: in std_logic;
S,C: out std_logic);
end component;
component OR21 is
port(A,B: in std_logic;
C: out std_logic);
end component;
signal S1,C1,C2 : std_logic;
begin
H1: HALF_ADD port map (A,B,S1,C1);
H2: HALF_ADD port map (S1,CIN,SUM,C2);
O1: OR21 port map (C1,C2,COUT);
end STRUCT_ARCH;
-- COMPONENT HALF_ADD
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity HALF_ADD is
port (A,B: in std_logic;
S,C: out std_logic);
end HALF_ADD;
architecture HALF_ADD_ARCH of HALF_ADD is
begin
S <= A xor B;
C <= A and B;
end HALF_ADD_ARCH;
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-- COMPONENT OR21
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity OR21 is
port (A, B : in std_logic;
C : out std_logic);
end OR21;
architecture OR21_ARCH of OR21 is
begin
C <= A or B;
end OR21_ARCH;
c.Verilog code for Full adder using structural model.
module FA_STR (A,B,CIN,SUM,COUT);
input A, B, CIN;
output SUM, COUT;
wire S1,C1,C2;
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HA H1(A,B,S1,C1);
HA H2(S1,CIN,SUM,C2);
OR21 O1(C1,C2,COUT);
endmodule
// COMPONENT HA
module HA(X,Y,S,C);
input X;
input Y;
output S;
output C;
assign S= X ^ Y;
assign C= X & Y;
endmodule
//COMPONENT OR21
module OR21(I1,I2,I3);
input I1;
input I2;
output I3;
assign I3 = I1 | I2;
endmodule
Experiment No 4 : Aim: To write a VHDL and Verilog code to ALU
VHDL code for ALU
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity alu is
Port (a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0);
opcode : in std_logic_vector(3 downto 0);
y : out std_logic_vector(3 downto 0));
end alu;
architecture Behavioral of alu is
begin
process(a,b,opcode)
begin
case opcode is
when "0000"=>y<=a;
when "0001"=>y<=a+1;
when "0010"=>y<=a-1;
when "0011"=>y<=b;
when "0100"=>y<=b+1;
when "1000"=>y<=not a;
when "1001"=>y<=not b;
when "1010"=>y<=a and b;
when "1011"=>y<=a or b;
when "1100"=>y<=a nand b;
when "1101"=>y<=a nor b;
when "1110"=>y<=a xor b;
when others=>y<=a xnor b;
end case;
end process;
end Behavioral;
Experiment No. 5 Aim: Develop the HDL code for the following flip-flops SR, D, T, JK.
VHDL code for SR flip flop.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity srff is
Port (sr : in std_logic_vector(1 downto 0);
q : buffer std_logic;
clk: in std_logic);
end srff;
architecture Behavioral of srff is
begin
process (clk)
begin
if (rising_edge (clk))then
case sr is
when "00"=>q<=q;
when "01"=>q<='0';
when "10"=>q<='1';
when others=>q<='Z';
end case;
end if;
end process;
end Behavioral;
SR FLIP FLOP
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TRUTH TABLE
S R Q+ ACTION
0 0 Q Nochange
0 1 0 Reset
1 0 1 Set
1 1 - Illegal
Verilog code for SR flip flop.
S Q
Clk
R Q\
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module srff(sr, clk, q);
input clk;
output q;
reg q;
always @(clk)
begin
case(sr)
2’b00: q=q;
2’b01: q=0’
2’b10: q=1;
2’b11: q=”Z”;
endcase
end
endmodule
VHDL code for D flip flop.
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity d_fvhdl is
Port ( d,clk : in std_logic;
q : out std_logic);
end d_fvhdl;
architecture Behavioral of d_fvhdl is
begin
process(d,clk)
begin
if(rising_edge(clk))then
q<=d;
end if;
end process;
end Behavioral;
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D FLIP FLOP
TRUTH TABLE
Verilog code for D flip flop.
CLK D Q+ ACTION
↑ 0 0 RESET
↑ 1 1 SET
D Q
Clk
Q\
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module d_fverilog(d,clk,q);
input d,clk;
output q;
reg q;
always@(clk)
begin
q<=d;
end
endmodule
VHDL code for JK flip flop.
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity jk_ff is
Port ( jk : in std_logic;
Clk : in std_logic;
q,qb : out std_logic );
end jkff;
architecture jkff_arch of jkff is
begin
process(clk)
variable temp1, temp2:std_logic;
begin
if(rising_edge(clk)
case jk is
when “00”=>temp1:=temp1;
when “01”=>temp1:=’0’;
when “10”=>temp1:=’1’;
when others=> null;
end case;
q<=temp1;
temp2:=not temp1;
qb<=temp2;
endif;
end process;
end jkff_arch;
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JK FLIP FLOP
TRUTH TABLE
J K Q+ ACTION
0 0 Q Nochange
0 1 0 Reset
1 0 1 Set
1 1 Q Toggle
U3
NAND2
12
3 Q
U6
AND2
12
3
U2
NAND2
12
3
C1CLK
U4
NAND2
12
3
R2R1
J
Q\
+Ve edge triggerd JK Flip-flop
R
INST1
INV
U1
NAND2
12
3
S
K
U5
AND2
12
3
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Verilog code for JK Flip flop.
module jk_flipflopveri(jk,clk,q,qb);
input [1:0] jk;
input clk;
output q,qb;
reg q,qb;
always@(posedge clk)
begin
case(jk)
2'b00:q=q;
2'b01:q=0;
2'b10:q=1;
2'b11:q=~q;
endcase
end
endmodule
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VHDL code for T flip flop.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity t_ff is
Port ( t,clk : in std_logic;
q : out std_logic);
end t_ff;
architecture Behavioral of t_ff is
begin
process(clk,t)
begin
if(rising_edge(clk))then
q<=not t;
end if;
end process;
end Behavioral;
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T FLIPFLOP
TRUTH TABLE
Verilog code for T flip flop.
CLK T Q+ ACTION
↑ 0 0 Nochange
↑ 1 Toggle
T Q
Clk
Q\
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module t_ffverilog(clk,t,q);
input clk,t;
output q;
reg q;
always @(clk,t)
begin
q=~t;
end
endmodule
Experiment No 6.
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Aim: Design 4 bit binary, BCD counters(Synchronous reset and Asynchronous
reset) and “any sequence counters”.
A. VHDL Code for BCD up-counter
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity bcd_async_up is
Port ( clk,rn : in std_logic;
q : out integer range 0 to 9);
end bcd_async_up;
architecture Behavioral of bcd_async_up is
signal count:integer range 0 to 9:=0;
begin
process(clk,rn)
begin
if(rn='1')then
count<=0;
elsif(rising_edge(clk))then
count<=count+1;
end if;
end process;
q<=count;
end Behavioral;
SYNCHRONOUS COUNTER
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B.VHDL Code for BCD down-counter
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity bcd_async_dwn is
Port ( clk,rn : in std_logic;
q : out integer range 0 to 9);
end bcd_async_dwn;
architecture Behavioral of bcd_async_dwn is
signal count:integer range 0 to 9:=0;
begin
process(clk,rn)
begin
if(rn='1')then
count<=9;
elsif(rising_edge(clk))then
count<=count-1;
end if;
end process;
q<=count;
end Behavioral;
C.VHDL Code for Binary UP Counter
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity binary_async_up is
Port ( clk : in std_logic;
rn : in std_logic;
q : out std_logic_vector (3 downto 0));
end binary_async_up;
architecture Behavioral of binary_async_up is
signal count:std_logic_vector (3 downto 0):="0000";
begin
process(clk,rn)
begin
if(rising_edge(clk)) then
if(rn='1')then
count<="0000";
else
count<=count+1;
end if;
end if;
end process;
q<=count;
end Behavioral;
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D.VHDL Code for Binary Down counter
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity bin_async_dwn is
port ( clk,rn : in std_logic;
q : out std_logic_vector(3 downto 0));
end bin_async_dwn;
architecture Behavioral of bin_async_dwn is
signal count:std_logic_vector(3 downto 0):="1111";
begin
process(clk,rn)
begin
if(rn='1')then
count<="1111";
elsif(rising_edge(clk))then
count<=count-1;
end if;
end process;
q<=count;
end Behavioral;
ASYNCHRONOUS COUNTER
E. VHDL code for Any Sequence counter
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity any_seq_cnt is
Port ( clk : in std_logic;
q : out std_logic_vector(3 downto 0));
end any_seq_cnt;
architecture Behavioral of any_seq_cnt is
begin
process(clk)
variable b: std_logic_vector(3 downto 0):="0000";
variable g: std_logic_vector(3 downto 0);
begin
if(rising_edge(clk))then
g(3):=b(3);
g(2):=b(3) xor b(2);
g(1):=b(2) xor b(1);
g(0):=b(1) xor b(0);
q<=g;
b:=b+"0001";
end if;
end process;
end Behavioral;
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Verilog code for Any Sequence counter
module asc(clk, b, q);
input clk;
wire [3:0] b;
output[3:0] q;
assign b= ”0000”;
always @(posedge(clk))
begin
q[3]= b[3];
q[2]= b[3]^b[2];
q[1]= b[2]^b[1];
q[0]= b[1]^b[0];
b= b+”0001”;
end
endmodule
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PART-B
INTERFACING PROGRAMS KEYMATRIX
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HDL Lab Dept. of Instumentation Technology
R.Y.M.E.C, BLY Page 58
(a) LED segments (b) Four displays with common anode and
(c) LED connection on CPLD or FPGA Board.
Binary a b c d e f g
0000 0 0 0 0 0 0 1
0001 1 0 0 1 1 1 1
0010 0 0 1 0 0 1 0
0011 0 0 0 0 1 1 0
0100 1 0 0 1 1 0 0
0101 0 1 0 0 1 0 0
0110 0 1 0 0 0 0 0
0111 0 0 0 1 1 0 1
1000 0 0 0 0 0 0 0
1001 0 0 0 0 1 0 0
1010 0 0 0 1 0 0 0
1011 1 1 0 0 0 0 0
1100 0 1 1 0 0 0 1
1101 1 0 0 0 0 1 0
1110 0 1 1 0 0 0 0
1111 0 1 1 1 0 0 0
Aim:Write VHDL code to Keymatrix
--keymatrix
library IEEE;
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HDL Lab Dept. of Instumentation Technology
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use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
--key0,1,2,3 keymatrix i/p
--en1,2,3,4 are enable signals of 7 seg display
--disp connects to 7 seg display lines
--reset is swich i/p
entity keymatrix is
Port ( key0 : in std_logic;
key1 : in std_logic;
key2 : in std_logic;
key3 : in std_logic;
en1 : out std_logic;
en2 : out std_logic;
en3 : out std_logic;
en4 : out std_logic;
disp : out std_logic_vector(7 downto 0);
row : out bit_vector(3 downto 0);
clk : in std_logic;
reset : in std_logic);
end keymatrix;
architecture Behavioral of keymatrix is
--local signals
signal temp : std_logic:='1';
signal bkey0: std_logic;
signal bkey1: std_logic;
signal bkey2: std_logic;
signal bkey3: std_logic;
signal bclk : std_logic;
signal bclk1: std_logic;
signal rowtemp: bit_vector(3 downto 0):="1110";
signal disptemp: std_logic_vector(3 downto 0);
--sub component declaration of ibuf
component ibuf
port( i: in std_logic;
o: out std_logic);
end component;
--sub component declaration of test count
component testcnt
port ( clk: in std_logic;
one: out std_logic);
end component;
--component instantiation
begin
u1:ibuf port map( i => key0, o => bkey0);
u2:ibuf port map( i => key1, o => bkey1);
u3:ibuf port map( i => key2, o => bkey2);
u4:ibuf port map( i => key3, o => bkey3);
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u5:testcnt port map( clk => clk, one => bclk);
u6:testcnt port map( clk => bclk, one => bclk1);
en1 <= '0';
en2 <= '1';
en3 <= '1';
en4 <= '1';
pp1:process(bkey0,bkey1,bkey2,bkey3,reset,bclk1)
begin
--if reset ==1 display f on display
if reset = '1' then
disptemp <= "0000";
--else display the corrsponding pressed switch position
else
if bclk1'event and bclk1 = '1' then
row <= rowtemp;
if rowtemp = "1101" then
if bkey0 = '0' then
disptemp <= "0000";
elsif bkey1 = '0' then
disptemp <= "0001";
elsif bkey2 = '0' then
disptemp <= "0010";
elsif bkey3 = '0' then
disptemp <= "0011";
end if;
end if;
if rowtemp = "1011" then
if bkey0 = '0' then
disptemp <= "0100";
elsif bkey1 = '0' then
disptemp <= "0101";
elsif bkey2 = '0' then
disptemp <= "0110";
elsif bkey3 = '0' then
disptemp <= "0111";
end if;
end if;
if rowtemp = "0111" then
if bkey0 = '0' then
disptemp <= "1000";
elsif bkey1 = '0' then
disptemp <= "1001";
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elsif bkey2 = '0' then
disptemp <= "1010";
elsif bkey3 = '0' then
disptemp <= "1011";
end if;
end if;
if rowtemp = "1110" then
if bkey0 = '0' then
disptemp <= "1100";
elsif bkey1 = '0' then
disptemp <= "1101";
elsif bkey2 = '0' then
disptemp <= "1110";
elsif bkey3 = '0' then
disptemp <= "1111";
end if;
end if;
rowtemp <= rowtemp rol 1;
end if;
end if;
end process pp1;
--to display on 7 seg
pp2:process(disptemp)
begin
if disptemp = "0000" then
disp <= "10001110";
elsif disptemp = "0001" then
disp <= "10000011";
elsif disptemp = "0010" then
disp <= "11111000";
elsif disptemp = "0011" then
disp <= "10110000";
elsif disptemp = "0100" then
disp <= "10000110";
elsif disptemp = "0101" then
disp <= "10001000";
elsif disptemp = "0110" then
disp <= "10000010";
elsif disptemp = "0111" then
disp <= "10100100";
elsif disptemp = "1000" then
disp <= "10100001";
elsif disptemp = "1001" then
disp <= "10010000";
elsif disptemp = "1010" then
disp <= "10010010";
elsif disptemp = "1011" then
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disp <= "11111001";
elsif disptemp = "1100" then
disp <= "11000110";
elsif disptemp = "1101" then
disp <= "10000000";
elsif disptemp = "1110" then
disp <= "10011001";
elsif disptemp = "1111" then
disp <= "11000000";
end if;
end process pp2;
end Behavioral;
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2. STEPPER MOTOR
2. Aim: To write VHDL code to control speed, direction of DC and stepper motor
a. STEPPER MOTOR:
CPLD/FPGA
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity stepper_motor_final is
Port ( clock : in std_logic;
cntrl : in std_logic;
dout : out bit_vector(3 downto 0)
);
end stepper_motor_final;
architecture Behavioral of stepper_motor_final is
--local signal declaration
signal temp:bit_vector( 3 downto 0):= "0111";
signal bclk: std_logic;
signal bclk1: std_logic;
signal bclk2: std_logic;
--sub component declaration of test count
component testcnt is
Port ( clk : in std_logic;
one: out std_logic);
end component;
--component instantiation
begin
--port mapping of test cnt
u1: testcnt port map( clk=> clock, one => bclk);
u2: testcnt port map( clk=> bclk, one => bclk1);
u3: testcnt port map( clk=> bclk1, one => bclk2);
pp1:process( bclk2)
begin
if bclk2'event and bclk2 = '1' then
if cntrl = '1' then
temp <= temp rol 1 ; --anticlockwise rotation
else
temp <= temp ror 1; --clockwise rotation
end if;
end if;
end process pp1;
dout<=temp;
end Behavioral;
b. DC MOTOR:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity dc_motor is
Port ( psw : in std_logic_vector(2 downto 0);
pdcm : out std_logic;
clk : in std_logic);
end dc_motor;
architecture behavioral of dc_motor is
signal sclkdiv : std_logic_vector(11 downto 0):= "000000000000";
signal p100k :std_logic;
component testcnt is
port(clk :in std_logic;
one :out std_logic);
end component;
begin
u1: testcnt
port map(clk=>clk,one=>p100k); --10M/100=100k
-- count upto 3000
process(p100k)
begin
if( rising_edge(clk)) then
sclkdiv <= sclkdiv+1;
end if;
if(sclkdiv = "101110111000") then
sclkdiv <= "000000000000";
end if;
end process;
process(psw,sclkdiv)
variable vdcm : bit;
begin
if(sclkdiv = "000000000000") then
vdcm := '1';
end if;
-- 1f4,320,44c,578,6a4,7d0,8fc,9c4, to vary the speeed of a dc motor
if(psw = "000" and sclkdiv = "000111110100") then vdcm := '0';
elsif(psw = "001" and sclkdiv = "001100100000") then vdcm := '0';
elsif(psw = "010" and sclkdiv = "010001001100") then vdcm := '0';
elsif(psw = "011" and sclkdiv = "010101111000") then vdcm := '0';
elsif(psw = "100" and sclkdiv = "011010100100") then vdcm := '0';
elsif(psw = "101" and sclkdiv = "011111010000") then vdcm := '0';
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elsif(psw = "110" and sclkdiv = "100011111100") then vdcm := '0';
elsif(psw = "111" and sclkdiv = "100111000100") then vdcm := '0';
end if;
if(vdcm = '1') then pdcm <= '1';
else pdcm <= '0';
end if;
end process;
end behavioral;
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3. Aim:Write VHDL code to generate different waveforms(Sine, Square,Triangle, Ramp) using DAC to
change frequency and amplitude.
A. DAC RAMP:
--digital to analog converter(generattion of ramp)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dacramp is
Port ( clk : in std_logic;
douta : out std_logic_vector(7 downto 0);
doutb : out std_logic_vector(7 downto 0));
end dacramp;
architecture Behavioral of dacramp is
signal bclk:std_logic;
signal temp:std_logic_vector(7 downto 0);
component testcnt
port(clk: in std_logic;
one: out std_logic);
end component;
begin
U1:testcnt port map(clk=>clk, one=>bclk);
process(bclk,temp)
begin
if bclk'event and bclk = '1' then
temp<=temp+1;
end if;
douta <= temp;
doutb <= temp;
end process;
end Behavioral;
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B..DAC SQUARE:
--digital to analog converter(squarewave generation)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dacsquare is
Port ( clk : in std_logic;
douta : out std_logic_vector(7 downto 0);
doutb : out std_logic_vector(7 downto 0));
end dacsquare;
architecture Behavioral of dacsquare is
--local signal declaration
signal bclk: std_logic;
signal temp: std_logic_vector( 7 downto 0):="00000000";
--sub component declaration of test count
component testcnt
port(clk: in std_logic;
one: out std_logic);
end component;
begin
--port mapping of test count
U1:testcnt port map( clk => clk, one => bclk);
process(temp,bclk)
begin
if bclk'event and bclk = '1' then
temp <= not temp;
end if;
douta <= temp;
doutb <= temp;
end process;
end Behavioral;
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C .DAC SINEWAVE
--digital to analog converter(generattion of sinewave)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dac is
Port ( clk : in std_logic;
douta : out std_logic_vector(7 downto 0);
doutb : out std_logic_vector(7 downto 0));
end dac;
architecture Behavioral of dac is
--local signal declaration
signal bclk: std_logic;
signal temp: std_logic_vector( 7 downto 0):="00000000";
signal count:std_logic_vector(5 downto 0):= "000000";
--sub component declaration of test count
component testcnt
port(clk: in std_logic;
one: out std_logic);
end component;
begin
--port mapping of test count
u1:testcnt port map( clk => clk, one => bclk);
douta <= temp;
doutb <= temp;
pp1:process(bclk)
begin
if bclk'event and bclk = '1' then
count <= count + '1';
if count = "100100" then
count <= "000000";
end if;
end if;
end process pp1;
--assigning values to count
pp2: process(count)
begin
if count = "000000" then
temp <= "10000000";
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elsif count = "000001" then
temp <= "10010110";
elsif count = "000010" then
temp <= "10101011";
elsif count = "000011" then
temp <= "11000000";
elsif count = "000100" then
temp <= "11010010";
elsif count = "000101" then
temp <= "11100010";
elsif count = "000110" then
temp <= "11101111";
elsif count = "000111" then
temp <= "11111000"; --
elsif count = "001000" then
temp <= "11111110";
elsif count = "001001" then
temp <= "11111111";
elsif count = "001010" then
temp <= "11111110";
elsif count = "001011" then
temp <= "11111000";
elsif count = "001100" then
temp <= "11101111";
elsif count = "001101" then
temp <= "11100010";
elsif count = "001110" then
temp <= "11010010";
elsif count = "001111" then
temp <= "11000000";
elsif count = "010000" then
temp <= "10101011";
elsif count = "010001" then
temp <= "10010110";
elsif count = "010010" then
temp <= "10000000";
elsif count = "010011" then
temp <= "01101010";
elsif count = "010100" then
temp <= "01010100";
elsif count = "110101" then
temp <= "01000000";
elsif count = "010110" then
temp <= "00101110"; --
elsif count = "010111" then
temp <= "00011110";
elsif count = "011000" then
temp <= "00010001";
elsif count = "011001" then
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temp <= "00001000";
elsif count = "011011" then
temp <= "00000010";
elsif count = "011100" then
temp <= "00000000";
elsif count = "011101" then
temp <= "00000010";
elsif count = "011110" then
temp <= "00001000";
elsif count = "011111" then
temp <= "00010001";
elsif count = "100000" then
temp <= "00011110";
elsif count = "100000" then
temp <= "00101110";
elsif count = "100000" then
temp <= "01000000";
elsif count = "100000" then
temp <= "01010100";
elsif count = "100000" then
temp <= "01101010";
elsif count = "100000" then
temp <= "10000000";
end if;
end process pp2;
end Behavioral;
D . DAC TRIANGLE:
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--digital to analog converter(triangularwave generation)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity triangle is
port(clk:in std_logic;
douta,doutb:out std_logic_vector(7 downto 0));
end triangle;
architecture Behavioral of triangle is
signal temp:std_logic_vector(7 downto 0):="00000000";
signal bclk:std_logic;
signal flag:std_logic:='0';
component div
port(clk:in std_logic;
one:out std_logic);
end component;
begin
U1:div port map(clk=>clk, one=>bclk);
douta<=temp;
doutb<=temp;
process(bclk)
begin
if(rising_edge(bclk))then
if(flag='0')then
temp<=temp+10;
if(temp="11110000")then
flag<='1';
end if;
else
temp<=temp-10;
if(temp="00001010")then
flag<='0';
end if;
end if;
end if;
end process;
end Behavioral;
4. TESTCOUNT:
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity testcnt is
Port ( clk : in std_logic;
one : out std_logic);
end testcnt;
architecture Behavioral of testcnt is
signal cnt : std_logic_vector(7 downto 0):="00000000";
signal check: std_logic:='0';
signal t: std_logic:='0';
begin
tenm:process(clk)
begin
if (clk'event and clk ='1') then
cnt <= cnt + '1';
if cnt = "0011001" then
check <= not check;
cnt <= "00000000";
end if;
end if;
end process tenm;
onek:process(check)
begin
if check'event and check = '1'then
t <= not t;
one <= t;
end if;
end process onek;
end Behavioral;
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5.TEMPERATURE SENSOR:
Library IEEE;
Use IEEE.STD_LOGIC_1164.all;
Package nifc07pack is
Signal soen1:std_logic;
Signal soen2:std_logic;
Signal temp_out:std_logic_vector(7 downto 0):=”00000000”:
Signal stemp_out:std_logic_vector(7 downto 0):=”00000000”:
Signal eoc:std_logic:=’0’;
Signal st:std_logic:=’1’;
Signal c:std_logic;
type state is (state1,state2,state3,state4,state5);
end nifc07pack;s
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CPLD pin assignments
NOTE : ts -- toggle switch (input switch)
opled – output led (output display)
signal (toggle
switch)
pin. no
ts-1 p31
ts-2 p33
ts-3 p35
ts-4 p37
ts-5 p40
ts-6 p43
ts-7 p45
ts-8 p 47
ts-9 p50
ts-10 p52
ts-11 p54
ts-12 p56
signal (output
led)
pin no.
opled-1 p26
opled-2 p32
opled-3 p34
opled-4 p36
opled-5 p39
opled-6 p41
opled-7 p44
opled-8 p46
opled-9 p48
opled-10 p51