HDL as Anfinal Destination

8/2/2019 HDL as Anfinal Destination

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HDL AND ITSAPPLICATIONS

PRESENTED BY:

www.tricksworld.net.tc


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INTRODUCTION

HDL is any language from a class of computerlanguages and/or programmed languages forformal description of electronic circuits ,and morespecially digital logic circuits

It can describe the circuit operation, design andorganization and tests to verify its operation by

means of simulation.

The first hardware description languages were ISPdeveloped at Carnegie Mellon University, andKARL, developed at University of Kaiserslautern,

both around 1977.


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ABEL HDL is developed by telecommunicationresearch center CSELT at Torino , Italy, around1980.

VERILOG HDL was introduced by gateway designautomation in 1985.

In 1987, a request from the U.S. Department of

Defense led to the development of VHDL.


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INTERPRETATION OF HDLS

ISP ISP (Instruction Set Processor) was, however, more like

a software programming language used to describerelations between the inputs and the outputs of thedesign. Therefore, it could be used to simulate the design,but not to synthesize it.

KARL

KARL included design calculus language featuressupporting VLSI chip floor planning and structuredhardware design.


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ABEL

ABEL stands for Advanced Boolean Equation Logic.

The ABEL HDL was made for PLD circuit design byDATA I/O and with other hardware descriptorlanguages come to easy the PLD design.

ABEL hardware description language allows to oneto describe digital designs with equations, truthtables, state diagrams, or any combinations of thethree, optimize and simulate the design without

specifying a device or assigning pins.


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ABEL Program Structure

The complete functional description of the designit is included in the so called module. An ABELprogram can have more than one module, but theenvironment will translate only the first module,

the other modules will be checked syntactically. Inone module can be specified only one PLD device.


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ABEL MODULE

HEADER (module name, options, titlestring)

DECLARATIONS (keyword, device, pin, node, constant,macro, library)

LOGIC DESCRIPTION (equations, truth tables, statediagrams, fuses, XOR factors)

TEST VECTORS (TEST_VECTOR,TRACE)

END STATEMENT


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VERILOG HDL

Verilog is a hardware description language (HDL),similar to VHDL that was originally written by PhilMoorby in 1984 who needed a simple, intuitive

and effective way of describing digital circuit formodeling, simulation and analysis purpose. It supports the design verification as well as

implementation of analog, digital and mixed signalcircuits at various levels of abstraction.

It is similar to C programming language, verilogis a fairly language to learn. Verilog is a casesensitive language.


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Verilog can be used to describe design at fourlevels of abstraction:

Switch level (the switches are MOS transistorinside gates)

Gate level (interconnected AND, NOR etc)

Register transfer level (RTL uses registersconnected by Boolean equations)

Algorithmic level (much like code c with case andloop statements)


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VHDL

In June 2006, VHDL Technical Committee ofAccellera approved so called Draft 3.0 of VHDL-2006. While maintaining full compatibility witholder versions, this proposed standard providesnumerous extensions that make writing andmanaging VHDL code easier.

In February 2008, Accellera approved VHDL 4.0also informally known as VHDL 2008, whichaddressed more than 90 issues discoveredduring the trial period for version 3.0 andincludes enhanced generic types.
http://en.wikipedia.org/wiki/Accellerahttp://en.wikipedia.org/wiki/Accellera


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entity but_not_gate is

port (X, Y: in bit; Z: out bit);

end entity but_not_gate

architecture behavioral of but_not_gate is

begin

work_cycle: process (X, Y) is begin

if X = 1 and Y = 0 then

Z


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entity declaration establishes external interfacesignal names, modes, types

architecture details implementationtypessignals

constantsvariablesfunctionsprocedurescomponents

beginconcurrent statements (processes)

end


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Examples:

architecture behavioral of but_not_gate isbegin

work_cycle: process (X, Y) is begin

if X = 1 and Y = 0 then

Z


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Phases in a HDL design project


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Timing Diagram


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VERILOG VS VHDL

The language syntax is the main factor since VHDL isbased on ADA and Verilog is based on C.

Verilog is easier to learn since C is a far simpler language.

It also produces more compact code; easier both to writeand read.

VHDL is very strongly typed, and allow programmer todefine their own types although, in practice, the main typesused are either the basic types of the language itself or

those define by the IEEE.

The benefit is that type checking is performed by thecompiler which can reduce errors; the disadvantage is thatchanging types must be done explicitly.


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ADVANTAGES OF VHDL OVER

VERILOG It provides a simple mechanism (the configure

statement) that allows the designer to switchpainless between different description of aparticular module.

It allows the conditional instancing of modules(if/for generate). This is one of those featuresthat you do not miss until you have used it once and then you need it all the time.

Many Verilog users recognize this lack and create

personal preprocessing routine it implement it(which negates some of the advantages of alanguage standard).


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ADVANTAGES OF VERILOG HDL

OVER VHDL

It ensures that all signals are initialized tounknown which ensures that all designers willproduce the necessary logic to initialize theirdesign the base type in VHDL initialize to zeroand the hasty designer may omit the globalreset.

It allows switchlevel modeling which somedesigners find useful for exploring new circuits.


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CONCLUSION

With the help of HDLs we can perform

many operations. As we know that HDLs

are used to operate or design digital

circuits, so by using HDLs we can designand describe the digital hardware.

HDL as Anfinal Destination

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