Hardware Lab 4

8/4/2019 Hardware Lab 4

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Hardware Lab 4

[A] Verify NAND Operation

[A1] From the data sheet draw out the pin-out diagram for the 74LS00 chip, labelling each

pin. Which pin are the power supply and ground respectively.

Pin 7 is the ground while pin 14 is the power supply.

[A2] Wire up a 74LS00 chip on the breadboard and verify the NAND operation using any

one of the four NAND gates available on the chip. You should draw a truth table (A and B

are inputs, and X is the output) indicating HIGH or LOW values.

Input Output

A B X = (A . B)'

0 (LOW) 0 (LOW) 1 (HIGH)

0 (LOW) 1 (HIGH) 1 (HIGH)

1 (HIGH) 0 (LOW) 1 (HIGH)

1 (HIGH) 1 (HIGH) 0 (LOW)

[A3] How do these voltages relate to logic values 0 (false) and 1(true)? Explain.

From the above table, we can conclude that the logic value 0 (false) is represented by a LOWvoltage. Similarly, the logic value 1 (true) is represented by a HIGH voltage. This is because

when the voltage is HIGH, the input is on. When the voltage is LOW, the input is off.

[A4] Explain whether 74LS00 uses positive logic or negative logic.

The 74LS00 uses positive logic. This is because the logic value 0 (false) is represented by a

LOW voltage. Meanwhile, the logic value 1 (true) is represented by a HIGH voltage.


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[B] Combinational Logic Implementation

[B1] Consider the logical expression F = A' C + A' B + A B' C + B C. Find the truth table

for F. Record your calculation in a table.

A A' B B' C C' A' C A' B A B' C B C F = A' C + A' B + A B' C + B C0 1 0 1 0 1 0 0 0 0 0

0 1 0 1 1 0 1 0 0 0 1

0 1 1 0 0 1 0 1 0 0 1

0 1 1 0 1 0 1 1 0 1 1

1 0 0 1 0 1 0 0 0 0 0

1 0 0 1 1 0 0 0 1 0 1

1 0 1 0 0 1 0 0 0 0 0

1 0 1 0 1 0 0 0 0 1 1

A B C Theory: F (unminimised) Theory : F (minimised) Measured : F (minimised)0 0 0 0 0 0

0 0 1 1 1 1

0 1 0 1 1 1

0 1 1 1 1 1

1 0 0 0 0 0

1 0 1 1 1 1

1 1 0 0 0 0

1 1 1 1 1 1

[B2] Minimise the logic function F. Find the truth table for the minimised F.


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A A' B C A' B F = A'B + C

0 1 0 0 0 0

0 1 0 1 0 1

0 1 1 0 1 1

0 1 1 1 1 1

1 0 0 0 0 01 0 0 1 0 1

1 0 1 0 0 0

1 0 1 1 0 1

[B3] Draw a circuit diagram of the minimised function using AND, OR and NOT gates.


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[B4] Find a draw a circuit diagram of the minimised function using NAND gates only.


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[B5] Build a circuit implementing the minimised function F using NAND gates only. Verify

its operation and complete the table above.

A B C Theory: F (unminimised) Theory : F (minimised) Measured : F (minimised)0 0 0 0 0 0

0 0 1 1 1 1

0 1 0 1 1 1

0 1 1 1 1 1

1 0 0 0 0 0

1 0 1 1 1 1

1 1 0 0 0 0

1 1 1 1 1 1


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[C] Propagation Delay

[C1] From the data sheet, find the average propagation delay tPD (average) for the 74LS00.

Typical value of tPLH = 9.0 ns

Typical value of tPHL = 10.0 ns

tPD = () ()

tPD =

tPD = 9.5 ns

[C2] To measure the propagation delay, connect the circuit as shown in the diagram below.


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[C3] Measure the propagation delay according to the definition used n the data sheets.

(Why is that definition used here?) You may use the delay feature accessed by the/ delayed

button on the CRO. Monitor VCC and watch for voltage spikes as the gates change states.

Try using a capacitor to filter out the spikes.

Measured value of tPHL= 9.6 ns

Measured value of tPLH = 7.2 ns

tPD (measured) = () ()

tPD (measured) =

tPD (measured) = 8.4 ns

Difference between the measured value and typical value of tPD = 9.6 ns8.4 ns

Difference between the measured value and typical value of tPD = 1.2 ns

The difference between the measured value and the typical value of tPD is only 1.2 ns. Therefore,

our result is acceptable.


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[D] 7 Segment Display

[D1] Wire up the 7-segment display chip and verify that all segments are working.

[D2]Consider the truth table for the 7-segment display. Find the (unminimised) Boolean

expression for the segment e.

Input Output

A B C D e

0 0 0 0 1

0 0 0 1 0

0 0 1 0 1

0 0 1 1 00 1 0 0 0

0 1 0 1 0

0 1 1 0 1

0 1 1 1 0

1 0 0 0 1

1 0 0 1 1

1 0 1 0 X

1 0 1 1 X

1 1 0 0 X

1 1 0 1 X

1 1 1 0 X1 1 1 1 X

F = A' B' C' D' + A' B' C D' + A' B C D' + A B' C' D'


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[D3] Using Karnaugh Maps and dont care conditions, find the minimised expression for

the segment e.

F = C D + B D


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[D4] Using NAND gates, build a circuit implementing the minimised expression for the

segment e. Verify the correct operation of the segment and record the results in a table.

Input Output

B C D B D C D BD F = C D + B D

0 0 0 1 1 0 1 1

0 0 1 1 0 0 0 0

0 1 0 1 1 1 1 1

0 1 1 1 0 0 0 0

1 0 0 0 1 0 0 0

1 0 1 0 0 0 0 0

1 1 0 0 1 1 0 1

1 1 1 0 0 0 0 00 0 0 1 1 0 1 1

0 0 1 1 0 0 0 0

0 1 0 1 1 1 1 X

0 1 1 1 0 0 0 X

1 0 0 0 1 0 0 X

1 0 1 0 0 0 0 X

1 1 0 0 1 1 0 X


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1 1 1 0 0 0 0 X

[E] Evaluation and Review Questions

[E1] When is the output of a 2-input NAND gate LOW.

The output of a 2-input NAND gate is LOW only when both the inputs are HIGH.

[E2] Define fan out and average power dissipation. What are the typical values for 74LS00?

Fan out is the maximum number of gates (of the same series in an IC family) that can be

connected to the output of a gate without degrading its performance. The average power

dissipation represents the average amount of power needed by the gate.

[E3] Define Dont care condition in a Karnaugh map.

The Dont care condition in a Karnaugh map is a condition when some combinations of the

input variables may not occur. In this case, the corresponding outputs are called Dont care

conditions and are denoted by an X. The Dont care output can be used as a 1 or 0, depending

on which results in a simpler simplification. However, it is not necessary to include all the

Dont care conditions in Karnaugh map simplification.

[E4] What is the limitation of the Karnaugh map technique?

The Karnaugh map technique can only be used to simplify expressions with 2, 3, 4 and 5

variables. An expression with more than 5 variables cannot be simplified by the Karnaugh map

technique.

[E5] What is the difference between a common-anode and a common-cathode 7-segment

LED?

The difference between a common-anode and a common-cathode 7-segment LED is due to the

arrangement of the LEDs inside it. For a common-anode 7-segment LED, the pins 3 and 8 act as

the common anodes while the pins 1, 2, 4, 5, 6, 7, 9 and 10 act as the cathodes. The LEDS have

the pins 3 and 8 as common anodes in which the current flows into it. For a common-cathode 7-

segment LED, the pins 3 and 8 act as the common cathodes while the pins 1, 2, 4, 5, 6, 7, 9 and

10 acts as the anodes. The LEDs have the pins 3 and 8 in which the current flows out of it.

Hardware Lab 4

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