1© 2015 The MathWorks, Inc.

Hardware Implementation and Verification by Model-Based Design Workflow- Communication Models to FPGA-based Radio

Katsuhisa Shibata – Industry MarketingMathWorks Japan

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Agenda

Challenges on Wireless Communication System Design Model-Based Design Workflow Hardware Implementation by Code Generation Verification User Stories

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Challenges on Wireless Communication System Design

It’s about Collaboration

RF / AnalogFront-End

DACModulationEncode

ADCDemodulationDecode

RF / AnalogHardwareVerification

/ TestDigital Hardware

Algorithms/ System

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Executable Specification Model– Model-Based Design entry point– Satisfies system requirements

Double Precision / Floating Point Model – Model in MATLAB and/or Simulink with Toolbox

Model Elaboration– Develop implementation friendly architecture in

Simulink– Convert to fixed-point using Fixed-Point Designer

Implement by Code Generation– Generate HDL code using HDL Coder– Customize code generation to meet

implementation goals (area, speed, etc.)– Import custom and vendor IP

Verification – HDL Verifier– HDL co-simulation– FPGA-in-the-loop verification– DPI-C generation for EDA-integrated verification

Verification

Implement byCode Generation

ModelElaboration

Continuous Verification

ExecutableSpecificationModel

SystemRequirements

Model-Based Design Workflow

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A Typical Model Structure

Algorithmic System-level Testbench

ComponentModelAnalysis

ComponentModel

EnvironmentModel

DataSource

Algo

rithm

Algorithm interacts with outside environment through other components

Algorithm is stimulated with data source Algorithm performance is analyzed by system level metrics

Executable Specification

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Executable Specification Model / Model Elaboration

RF / AnalogFront-End

DACModulationEncode

ADCDemodulationDecode

Data

SourceAnalysis

Environment

Demodulation

synch.

OFDM demodulation

channel estimation

equalisation

channel estimation

equalisationOFDM

demodulation

Fixed Point model

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Executable Specification Model /Model Elaboration with Simulink

Modeling and Simulation Environment for Model-Based Design

– Multi-domain system design – Visualize and Analysis

Application specific Add-on– Communications System Toolbox– LTE System Toolbox

Data type conversion from Floating point to Fixed point

– Analyze the conversion effect– Recommend word length and

rounding mode

Simulink

Fixed-Point Designer

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Hardware Implementation by Code Generation

Demodulation

synch.

OFDM demodulation

channel estimation

equalisation

channel estimation

equalisationOFDM

demodulation

Fixed Point model

HDL

Refine Algorithm/System for hardware implementation– Should be bit/cycle accurate, Fixed Point data type required

Debug / Review with Algorithm/System engineers Explore alternative options for better implementation

– Optimize resource utilization…DSP unit, register, etc.

Integrate with existing code / IP

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Hardware Implementation by Code Generation – From Model to Hardware by HDL Coder

Generate HDL from MATLAB,Simulink and Stateflow– Device independent code– Readable / Synthesizable– Verilog / VHDL supported

Easy operation from GUI tool– HDL Workflow advisor

Create reports / Scripts– Resource usability,

traceability, etc.– Compilation, Simulation and

Synthesis

Algorithmic System-level Testbench

ComponentModelAnalysis

ComponentModel

EnvironmentModel

DataSource

Algo

rithm

RTL HDL(VHDL, Verilog)

HDL Coder

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MATLAB & Simulink Support for HDL generationHDL Coder

Over 200 blocks supported Core Simulink Blocks

– Basic and Array Arithmetic, Look-Up Tables, Signal Routing (Mux/Demux, Delays, Selectors), Logic & Bit Operations, Dual and single port RAMs, FIFOs, CORDICs

Signal Processing Blocks– NCOs, FFTs, Digital Filters (FIR, IIR, Multi-

rate, Adaptive), Rate Changes (Up &Down Sample), Statistics (Min/Max)

Communications Blocks– Psuedo-random Sequence Generators,

Modulators / Demodulators, Interleavers / Deinterleavers, Viterbi Decoders

MATLAB Function Stateflow

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HDL Workflow AdvisorHDL Coder

Step-by-step guidance through code generation process– Model setup– HDL code generation– FPGA synthesis and analysis

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Create Report and ScriptsHDL Coder

Documents generated code inan HTML report – Resource Utilization Report– Optimization Report– Traceability Report– HDL Coding Standard Report

Generate scripts to control EDA tools – Compilation, Simulation– Synthesis– Lint

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VerificationIntegrating with other Verification Activities

Verification is commonly cited as the single biggest cost in hardware design– Significant investment in developing simulations for verification

SystemVerilog and UVM test frameworks SystemC/TLM virtual platforms

– Shift towards ‘model-based’ verification Enabling techniques like Constrained Random testing Reusable / Parameterized testbench

Rather than recreate a behavioural model, we can reuse the assets developed in the system models in MATLAB & Simulink– Maintains connection with earlier part of the flow

Removes risk of manual error in test framework Avoids duplicating effort

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Co-simulation with HDL simulators

Co-simulation with 3rd-party HDL simulator

– HDL code execution in 3rd-party HDL simulator

– Flexible HDL sources Handwritten or generated code

– Automatic co-simulation Combined analysis and

debugging in both simulators

– Reuse of existing testbench in MATLAB/Simulink

Algorithmic System-level Testbench

ComponentModelAnalysis

ComponentModel

EnvironmentModel

DataSource

Algo

rithm

Co-Sim

3rd-party HDL Simulator

RTL HDL(VHDL, Verilog)

HDL Verifier

HDL Verifier

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Visualize simulation result in MATLAB/ SimulinkBetter insight to the result

Automatically generated co-simulation models and Wizards for legacy HDL codeEasy configuration

No need to recreate testbench in HDLReuse existing system level model as testbench

Flexible testbench creation in SimulinkParameterized / Integrated multi-domain testbench

Advantages of Co-Simulation with HDL simulators

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FPGA-in-the-Loop Verification

FIL simulation with FPGA development board

– HDL code execution on FPGA

– Flexible HDL sources Handwritten or generated code

– Automated FIL Encapsulation of algorithm within

GBit Ethernet MAC

– Automatic handshaking

– Reuse of existing testbench in MATLAB/Simulink

Algorithmic System-level Testbench MATLAB and Simulink

ComponentModelAnalysis

ComponentModel

EnvironmentModel

DataSource

Algo

rithm

FIL

HDL Verifier

HDL Verifier

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Flexible testbench creation in SimulinkParameterized / Integrated multi-domain testbench

Re-use system level test bench for FPGA verificationNo need to recreate testbench in T&M hardware

Building confidence that the algorithm works on real hardwareNo need to wait until other components become ready

Advantages of FPGA-in-the-Loop Verification

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FPGA-in-the-Loop supports more FPGA boards natively

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33

0

5

10

15

20

25

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35 Number of FPGA Boards Supported by FIL Xilinx VC707

Altera Cyclone V GT

Arrow SoCKit(Altera Cyclone V SoC)

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SystemVerilog Testbench Environment

System Verilog DPI-C Component GenerationReuse of models in SystemVerilog Testbench

Develop – System components (IP and test

benches) in Simulink and MATLAB

– Model, Simulate, and Verify

Export – Components as C code with

SystemVerilog wrappers

Integrate – Components with components in

the HDL Simulator

Verify– Verification of the complete

system design!

Algorithmic System-level Testbench

ComponentModelAnalysis

ComponentModel

EnvironmentModel

DataSource

Algo

rithm

ComponentModel

DPI-C

HDL VerifierSimulink Coder

DPI-C DPI-C DPI-C

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Verification workflow using System VerilogDPI-C component Generation

Generate C Code as DPI-C components for

HDL testbench

Hand-coded or Generated HDL code

C Code(DPI) HDL Code

Reuse system-level Model for HDL verification

HDL Simulator/System Verilog

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Advantages of System Verilog DPI-C component generation Generate System

Verilog component directly from MATLAB/Simulink algorithms

Available Parameterized component generation

Small impact to existing EDA environment

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Hitachi Drives Adoption of Model-Based Design

Challenge Improve a fragmented workflow and reduce FPGA development time

SolutionAdopt Model-Based Design with MATLAB and Simulink

Results Engineering headcount halved HDL verification accelerated Development time reduced by over 30%

“We have adopted Model-Based Design with MATLAB and Simulink as our standard development workflow for FPGA design. As a result, we have improved communication between teams, reduced development time, and reduced risk by evaluating system performance early in the design process.”Noritaka Kosugi, Kazuyuki Hori, Yuji Ishida,

and Makoto HasegawaHitachi

Link to article

Development workflow after the introduction of Model-Based Design.

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Customer Presentation at MATLAB EXPO 2014

Generating code for FPGAs with HDL Coder to prototype future wireless communications systems.

www.mathworks.com/videos/radio-testbed-design-using-hdl-coder-92636.html

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Customer Presentation at MATLAB EXPO 2014

Development and Adoption of Algorithm & RTL-integrated Verification Platform

https://www.mathworks.com/company/events/conferences/matlab-expo-japan/2014/

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Summary

Challenges on Wireless Communication System Design– It’s about Collaboration

Model-Based Design Workflow– Help your communication system project in Digital hardware

implementation and verification Hardware implementation by Code Generation

– Help Digital hardware engineers Better collaboration with Algorithm/System Engineer, RF/Analog Engineer Optimize implementation by automatic / systematic exploration

Verification by reusing MATLAB/Simulink model– Co-simulation with HDL simulator– FPGA-in-the-loop simulation– System Verilog DPI-C Component generation

This is a proven-workflow by User Stories