Hardik_VLSI_Resume
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1 HARDIK TRIVEDI E-Mail: [email protected] Mobile: +91-9825665563, +91-7676523424 OBJECTIVE Seeking Entry Level positions in ASIC Design and Verification domain in semiconductor organization which offers professional growth, where I can utilize my skills in order to ensure quality services to the organization. SUMMARY Masters in VLSI Design and around 1 year (June 2013-June 2014) experience in ASIC Design and Verification, Manipal University, Karnataka. Strong hands on working experience in ASIC Design and Verification. Good in Design and Verification approach, flow and concepts. Experience in writing test cases in System Verilog. Possess sound knowledge of programming languages such as Verilog, System Verilog. Gained knowledge in subjects like High Level Digital Design, Digital Systems in VLSI Design, Verification and Testing. AREAS OF INTEREST ASIC Verification, RTL Design, SOC INTERNSHIP PROJECT Project : Design and Verification of USB 3.0 SuperSpeed Physical Layer. The project aimed at to manage transfer data either on 2.5 GT/s or 5.0 GT/s depends upon the mode and rate. In Design I manage to capture the data that are coming asynchronously and lock the receiver clock with incoming asynchronous serial data. Verify the complete design of USB 3.0 SuperSpeed Physical Layer using System Verilog. I wrote an exhaustive verification plan from the specifications. I created Verification Environment and wrote Test Cases to verify design in System Verilog. Project : Verification of USB 3.0 Link Layer (LTSSM). Verification of LTSSM state machine of USB 3.0 using System Verilog. Link Training and Status State Machine (LTSSM) is a state machine defined for link connectivity and the link power management. Designing is done in Verilog and simulation is done in Cadence tool. Verification is done in System Verilog using CRV (Constrained Random Verification) methodology. ACADEMIC PROJECT HDLC CONTROLLER DESIGN Designed HDLC transmitter using Verilog HDL, HDLC protocol was implemented with transmission of 8bit flag, followed by data transmission by synchronous fifo which was further processed by zero stuffing in order to differentiate data from flag bit during reception. HDLC Receiver received data bit by bit. Reception begins with recognition of flag register, which indicates the reception of new HDLC frame, followed by zero unstuffing process, and after that data is received by secondary station.
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Transcript of Hardik_VLSI_Resume
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HARDIK TRIVEDI E-Mail: [email protected]
Mobile: +91-9825665563, +91-7676523424
OBJECTIVE
Seeking Entry Level positions in ASIC Design and Verification domain in semiconductor
organization which offers professional growth, where I can utilize my skills in order to
ensure quality services to the organization.
SUMMARY
Masters in VLSI Design and around 1 year (June 2013-June 2014) experience in ASIC Design and Verification,
Manipal University, Karnataka.
Strong hands on working experience in ASIC Design and Verification.
Good in Design and Verification approach, flow and concepts.
Experience in writing test cases in System Verilog.
Possess sound knowledge of programming languages such as Verilog, System Verilog.
Gained knowledge in subjects like High Level Digital Design, Digital Systems in VLSI Design, Verification and Testing.
AREAS OF INTEREST
ASIC Verification, RTL Design, SOC
INTERNSHIP PROJECT
Project : Design and Verification of USB 3.0 SuperSpeed Physical Layer.
The project aimed at to manage transfer data either on 2.5 GT/s or 5.0 GT/s depends upon the mode and rate. In Design I manage to capture the data that are coming asynchronously and lock the receiver clock with incoming asynchronous serial data.
Verify the complete design of USB 3.0 SuperSpeed Physical Layer using System Verilog. I wrote an exhaustive verification plan from the specifications. I created Verification Environment and wrote Test Cases to verify design in System Verilog.
Project : Verification of USB 3.0 Link Layer (LTSSM).
Verification of LTSSM state machine of USB 3.0 using System Verilog. Link Training and Status State Machine (LTSSM) is a state machine defined for link connectivity and the link power management.
Designing is done in Verilog and simulation is done in Cadence tool. Verification is done in System Verilog using CRV (Constrained Random Verification) methodology.
ACADEMIC PROJECT
HDLC CONTROLLER DESIGN Designed HDLC transmitter using Verilog HDL, HDLC protocol was implemented with transmission of 8bit flag,
followed by data transmission by synchronous fifo which was further processed by zero stuffing in order to differentiate data from flag bit during reception.
HDLC Receiver received data bit by bit. Reception begins with recognition of flag register, which indicates the reception of new HDLC frame, followed by zero unstuffing process, and after that data is received by
secondary station.
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PUBLICATIONS
Published paper on “Implementation of USB 3.0 SuperSpeed Physical Layer Using Verilog HDL” at International Journal of Computer Applications (IJCA) 95(24):1-5, June 2014. Published by Foundation of
Computer Science, New York, USA Published paper on “Design and Verification of USB 3.0 Link Layer (LTSSM)” at International Journal
of Computer Science and Information Technologies (IJCSIT), Vol. 5 (4), 2014, 4916-4921. Published paper on “Implementation of HDLC Controller Design Using Verilog HDL” at International
Conference on Electrical, Electronics and System Engineering (ICEESE), organized by IEEE Education Malaysia Chapter.
ACADEMIC CREDENTIALS
Masters of Science in Technology (MS) VLSI Design from School of Information Science, Manipal University, Manipal in 2014. Secured CGPA 8.43.
B-Tech. (Electronics & Communication Engineering) from Geetanjali Institute of Technical Studies, Rajasthan Technical University, Udaipur in 2011. Secured 58.31%
12th from Jawahar Navodaya Vidhyalaya, CBSE in 2007. Secured 71.20% 10th from Jawahar Navodaya Vidhyalaya, CBSE in 2005. Secured 72%
TECHNICAL SKILLS
Programming Language : C, C++ HDL : Verilog HVL : System Verilog Scripting : Linux Shell Scripting, Perl Protocols : USB 3.0 (Physical Layer, Link Layer), HDLC EDA Tools : Synopsys VCS, Design Compiler, Cadence NCSim, Cadence Encounter,
Cadence Virtuoso, Xilinx ISE, Quartus, Matlab, Magic Layout.
Operating Systems : Windows, Linux.
BEYOND CURRICULUM AND ACHIEVEMENTS
Secured Runners-up position in Inter Collegiate Volleyball Tournament in Feb 13-14. Played State Level Volleyball Tournament in 2010. Secured 4th position in National Level Youth Parliament in 2006
Actively participated in various Mathematics and Science Projects presentations during High School.
PERSONAL DOSSIER
Date of Birth : 16th December, 1989 Address : A-17, Tirupati Township B/H Rajpath Hotel Nagalpur, Mahesana – 384002, Gujarat.
Contact No. : +91-9825665563, +91-7676523424 Languages Known : English, Hindi and Gujarati. Nationality : Indian
