Hanyang University Hyunmin Yoon...
Transcript of Hanyang University Hyunmin Yoon...
Real-Time Computing and Communications Lab.Hanyang University
Operating System(Undergraduate, 2018 Spring)
Operating System
Hanyang University
Hyunmin Yoon([email protected])
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Real-Time Computing and Communications Lab.Hanyang University
Operating System(Undergraduate, 2018 Spring)
INTERRUPTInterrupt vs. Polling
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Real-Time Computing and Communications Lab.Hanyang University
Operating System(Undergraduate, 2018 Spring)
Polling (Programmed I/O)
Processor has direct control over I/O Processor waits for I/O module to complete
operation Processor determines state of device
Command-ready Busy Error
Busy-wait cycle to wait for I/O
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Real-Time Computing and Communications Lab.Hanyang University
Operating System(Undergraduate, 2018 Spring)
Interrupt (Interrupt-driven I/O)
1. Processor issues commands for I/O operations2. Processor does other work while I/O devices do
the operations3. I/O devices send hardware interrupt signal to
processor when they complete the operations4. Processor stops the work, and then starts ISR
(interrupt service routine)5. Processor redo the work that is stopped by
interrupt
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Real-Time Computing and Communications Lab.Hanyang University
Operating System(Undergraduate, 2018 Spring)
Interrupt
IRQUSR
interrupt
ISR
return to previous work
stop current work
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Real-Time Computing and Communications Lab.Hanyang University
Operating System(Undergraduate, 2018 Spring)
ARM PROCESSOR FUNDAMENTALS #3
Interrupt Service Routine
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Real-Time Computing and Communications Lab.Hanyang University
Operating System(Undergraduate, 2018 Spring)
Registers
• Register size• 32 bits
• 18 Active registers • 16 data registers (r0 to r15)• 2 processor status registers
• CPSR = current psr• SPSR = saved psr
20 Banked registers
ARM System Developer’s Guide
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Real-Time Computing and Communications Lab.Hanyang University
Operating System(Undergraduate, 2018 Spring)
Processor Status Register
ARM System Developer’s Guide
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Real-Time Computing and Communications Lab.Hanyang University
Operating System(Undergraduate, 2018 Spring)
Mode Switch (1)
Mode switch by Hardware when the core responds to an exception or
interrupt Software that writes directly to the mode bits of cpsr
• Except USR mode
Banked register All processor modes have a set of associated banked
registers• Except SYS mode
A banked register maps one-to-one onto a USR mode register
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Real-Time Computing and Communications Lab.Hanyang University
Operating System(Undergraduate, 2018 Spring)
Mode Switch (2) Example
: When processor changes from USR mode to IRQ mode cpsr of previous mode (USR) is
automatically saved into spsr of the next mode (IRQ)
Return address is saved into r14_irq Processor read r13 and r14 of the current
mode when it accesses them• PRE
: r0 = 0x00, r13 = 0x10, r13_irq = 0x20,cpsr = IRQ mode
mov r0, r13
• POST: r0 = 0x20 , r13 = 0x10, r13_irq = 0x20 ,cpsr = IRQ mode
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Real-Time Computing and Communications Lab.Hanyang University
Operating System(Undergraduate, 2018 Spring)
Vector Table
When an exception or interrupt occurs Suspend normal execution Set the pc to a specific memory address
Start address of vector table can be changed
ARM System Developer’s Guide
(rose/hal/kernel/entry-armv.S)
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Real-Time Computing and Communications Lab.Hanyang University
Operating System(Undergraduate, 2018 Spring)
ISR (timer)
interrupt from device
(rose/hal/kernel/entry-armv.S)
(rose/hal/kernel/entry-armv.S)
(rose/hal/io/timer.c)
(rose/hal/irq/gic.c)
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Real-Time Computing and Communications Lab.Hanyang University
Operating System(Undergraduate, 2018 Spring)
HOMEWORK #1Write codes for the return from ISR to user application
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Real-Time Computing and Communications Lab.Hanyang University
Operating System(Undergraduate, 2018 Spring)
Homework #1
Complete vector_irq and ret_to_usr rose/hal/kernel/entry-armv.S
Do not use branch instructions
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Real-Time Computing and Communications Lab.Hanyang University
Operating System(Undergraduate, 2018 Spring)
Purpose Consider that processor runs
counting program as below
And, timer interrupt request is generated during the program execution Processor register has cnt value But, that register is using on ISR also
-> cnt value will be corrupted
OS has to restore previous program execution states including cnt value before the return from ISR
IRQUSR
interrupt
ISR
return to previous work
stop current work
void main(void) {unsigned int cnt = 0;while(1)
cnt++;}
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Real-Time Computing and Communications Lab.Hanyang University
Operating System(Undergraduate, 2018 Spring)
Process Control Block
(rose/hal/kernel/entry-armv.S)
(rose/kernel/sched.c)
(rose/include/rose/sched.h)Memory
point at PCB of current program
…
task_struct
task_struct
task_struct
PCBList
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Real-Time Computing and Communications Lab.Hanyang University
Operating System(Undergraduate, 2018 Spring)
H1-A Save context
1. Save r0-r12 of USR mode onto reg[R0]-reg[R12]2. Save cpsr of USR mode onto reg[CPSR]3. Save return address (from IRQ to USR) onto reg[RET]
…
class
state
pid
alloc
reg[RET]
reg[CPSR]
reg[LR]
reg[SP]
reg[12]
..
reg[R2]
reg[R1]
reg[R0]lrlr+4lr+8
lr+60lr+64lr+68lr+72lr+76lr+80
address value
MEMORY
r0~r12 of USR
lr+56lr+52lr+48
cpsr of USR
task_struct
…Return Address
…
sp
address value
MEMORY
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Real-Time Computing and Communications Lab.Hanyang University
Operating System(Undergraduate, 2018 Spring)
H1-B Restore context
1. Make stack area and fill it for RFE instruction by using reg[CPSR] and reg[RET]
2. Restore r0-r12 of USR mode by using reg[R0]-reg[R12]…
class
state
pid
alloc
reg[RET]
reg[CPSR]
reg[LR]
reg[SP]
reg[12]
..
reg[R2]
reg[R1]
reg[R0]lrlr+4lr+8
lr+60lr+64lr+68lr+72lr+76lr+80
address value
MEMORY
r0~r12 of USR
lr+56lr+52lr+48
cpsr of USR
task_struct
…
cpsr_usrReturn Address
…sp
address value
MEMORY
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Real-Time Computing and Communications Lab.Hanyang University
Operating System(Undergraduate, 2018 Spring)
Result (1)
Now, we can use shell program