Hamed List
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S.NO PROJECT TITLE 1 Area–Delay–Power Efficient Carry-Select Adder 2 All Optical Reversible Multiplexer Design using Mach-Zehnder Interferometer 3 A Low Power Fault Tolerant Reversible Decoder Using MOS Transistor 4 Design and Synthesis of Reversible Arithmetic and Logic Unit (ALU) 5 Realization of 2:4 reversible decoder and its applications 6 Energy Efficient Code Converters using Reversible Logic Gates 7 Design of Low Logical Cost Conservative Reversible Adders using Novel PCTG 8 Design of Dedicated Reversible Quantum Circuitry for Square Computation 9 An Optimized Design of Binary Comparator Circuit in Quantum Computing 10 High-speed Energy-efficient 5:2 Compressor 11 Mach-Zehnder Interferometer based All Optical Reversible Carry-Lookahead Adder 12 Implementation of an Efficient Multiplier based on Vedic Mathematics Using High speed adder 13 Design and Estimation of delay, power and area for Parallel prefix adders 14 Design of Low Power Multiplier Using Reversible Logic Gate 15 Design of Low Power and High Speed Modified Carry Select Adder for 16 bit Vedic Multiplier 16 Low-Power and Area-Efficient Carry Select Adder 17 Recursive Approach to the Design of a Parallel Self-Timed Adder 18 Implementation of Vending MachineController with Auto-Billing Features using Finite State Machine 19 FPGA Implementation(s) of a Scalable Encryption Algorithm 20 Implementation of High Speed Low Power Combinational and Sequential Circuits using Reversible logic
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Transcript of Hamed List
S.NO PROJECT TITLE1 Area–Delay–Power Efficient Carry-Select Adder2 All Optical Reversible Multiplexer Design using Mach-Zehnder Interferometer3 A Low Power Fault Tolerant Reversible Decoder Using MOS Transistor4 Design and Synthesis of Reversible Arithmetic and Logic Unit (ALU)5 Realization of 2:4 reversible decoder and its applications6 Energy Efficient Code Converters using Reversible Logic Gates7 Design of Low Logical Cost Conservative Reversible Adders using Novel PCTG8 Design of Dedicated Reversible Quantum Circuitry for Square Computation9 An Optimized Design of Binary Comparator Circuit in Quantum Computing10 High-speed Energy-efficient 5:2 Compressor11 Mach-Zehnder Interferometer based All Optical Reversible Carry-Lookahead Adder12 Implementation of an Efficient Multiplier based on Vedic Mathematics Using High speed
adder13 Design and Estimation of delay, power and area for Parallel prefix adders14 Design of Low Power Multiplier Using Reversible Logic Gate15 Design of Low Power and High Speed Modified Carry Select Adder for 16 bit Vedic
Multiplier16 Low-Power and Area-Efficient Carry Select Adder17 Recursive Approach to the Design of a Parallel Self-Timed Adder18 Implementation of Vending MachineController with Auto-Billing Features using Finite
State Machine19 FPGA Implementation(s) of a Scalable Encryption Algorithm20 Implementation of High Speed Low Power Combinational and Sequential Circuits using
Reversible logic
