H8S/2626 Series, H8S/2623 Series H8S/2626F-ZTAT™, H8S ... · The H8S/2626 Series and H8S/2623...

Hitachi 16-Bit Single-Chip Microcomputer

H8S/2626 Series, H8S/2623 Series H8S/2626F-ZTAT™,H8S/2623F-ZTAT™

H8S/2626 SeriesH8S/2626 HD6432626H8S/2625 HD6432625H8S/2624 HD6432624

H8S/2623 SeriesH8S/2623 HD6432623H8S/2622 HD6432622H8S/2621 HD6432621

H8S/2626F-ZTAT™HD64F2626

H8S/2623F-ZTAT™HD64F2623

Hardware Manual

ADE-602-164BRev. 3.05/25/00Hitachi, Ltd.

Cautions

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4. Design your application so that the product is used within the ranges guaranteed by Hitachiparticularly for maximum rating, operating supply voltage range, heat radiation characteristics,installation conditions and other characteristics. Hitachi bears no responsibility for failure ordamage when used beyond the guaranteed ranges. Even within the guaranteed ranges,consider normally foreseeable failure rates or failure modes in semiconductor devices andemploy systemic measures such as fail-safes, so that the equipment incorporating Hitachiproduct does not cause bodily injury, fire or other consequential damage due to operation ofthe Hitachi product.

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Preface

The H8S/2626 Series and H8S/2623 Series are series of high-performance microcontrollers with a32-bit H8S/2600 CPU core, and a set of on-chip supporting modules required for systemconfiguration.

The H8S/2600 CPU can execute basic instructions in one state, and is provided with sixteen 16-bitgeneral registers with a 32-bit internal configuration, and a concise and optimized instruction set.The CPU can handle a 16 Mbyte linear address space (architecturally 4 Gbytes). Programs basedon the high-level language C can also be run efficiently.

The address space is divided into eight areas. The data bus width and access states can be selectedfor each of these areas, and various kinds of memory can be connected fast and easily.

Single-power-supply flash memory (F-ZTAT™*), and mask ROM versions are available,providing a quick and flexible response to conditions from ramp-up through full-scale volumeproduction, even for applications with frequently changing specifications.

On-chip supporting functions include a 16-bit timer pulse unit (TPU), programmable pulsegenerator (PPG), watchdog timer (WDT), serial communication interface (SCI), Hitachi controllerarea network (HCAN), A/D converter, D/A converter (H8S/2626 Series only), and I/O ports.

In addition, data transfer controller (DTC) is provided, enabling high-speed data transfer withoutCPU intervention.

Use of the H8S/2626 Series or H8S/2623 Series enables easy implementation of compact, high-performance systems capable of processing large volumes of data.

This manual describes the hardware of the H8S/2626 Series and H8S/2623 Series. Refer to theH8S/2600 Series and H8S/2000 Series Programming Manual for a detailed description of theinstruction set.

Note: * F-ZTAT (Flexible-ZTAT) is a trademark of Hitachi, Ltd.

Revisions and Additions in this Edition

Page Item Revisions (See Manual for Details)

All Amendments associated with additionof H8S/2626 Series

2 to 5 Table 1-1 Overview Following items amended due toaddition of H8S/2626 SeriesWDT, D/A converter, I/O ports, memory,interrupt controller, power-down mode,product lineup

7 Figure 1-2 Internal Block Diagram Added

9 Figure 1-4 Pin Arrangement Added

14 to 17 Table 1-3 Pin Functions in Each OperatingMode

Added

18, 22 Table 1-4 Pin Functions Clock: OSC1, OSC2 (subclock pins)addedI/O ports: Note added to Port A

61 Figure 2-14 Processing States Note added

62 Figure 2-15 State Transitions Note 3. added

66 2.8.6 Power-Down State Description amended

76 3.2.3 Pin Function Control Register (PFCR) Bit 5 description amended

84 Figure 4-1 Exception Sources Note 2. added

85 Table 4-2 Exception Vector Table Exception handling source ÒDirecttransitionsÓ added

90 Figure 4-4 Interrupt Sources and Number ofInterrupts

Internal interrupt ÒWDTÓ amended

99 Table 5-3 Correspondence between InterruptSources and IPR Settings

Amended

103 5.3 Interrupt Sources Internal interrupt sources amended

105 to107

Table 5-4 Interrupt Sources, VectorAddresses, and Interrupt Priorities

Amended

130, 131 6.3.4 Operation in Transitions to Power-DownModes

Amended

148 7.2.6 Pin Function Control Register (PFCR) Bit 5 description amended

209 9.1 Overview Description amended

210 to212

Table 9-1 Port Functions Ports 9, A, and F amended

230, 231 9.4 Port 9 Description of pins DA2 and DA3 added


232 to239

9.5 Port A Description of pins OSC2 and OSC1added

273 to278

9.10 Port F Description of BUZZ pin added

397 to416

Section 12 Watchdog Timer WDT1 related description added

524 15.2.1 Master Control Register (MCR) R/W of bits 6, 4, 3 amended

525 15.2.2 General Status Register (GSR) R/W of bits 7 to 4 amended

528 Figure 15-2 Detailed Description of One Bit Note added

529 Table 15-3 Setting Range for TSEG1 andTSEG2 in BCR

Note added

531 15.2.4 Mailbox Configuration Register(MBCR)

R/W of bit 8 amended

532 15.2.5 Transmit Wait Register (TXPR) R/W of bit 8 amended

533 15.2.6 Transmit Wait Cancel Register (TXCR) R/W of bit 8 amended

534 15.2.7 Transmit Acknowledge Register(TXACK)

R/W of bit 8 amended

535 15.2.8 Abort Acknowledge Register (ABACK) R/W of bit 8 amended

536 15.2.9 Receive Complete Register (RXPR) Description amended

537 15.2.10 Remote Request Register (RFPR) Description amended

538, 540 15.2.11 Interrupt Register (IRR) R/W of bit 10 amendedBit 8 description amended

543 to545

15.2.13 Interrupt Mask Register (IMR) R/W of bits 8 to 5, 3, 2 amendedBit descriptions amended

546 15.2.16 Unread Message Status Register(UMSR)

Description amended

547, 548 15.2.17 Local Acceptance Filter Masks(LAFML, LAFMH)

R/W of bits 12 to 10 amendedBit descriptions amended

549, 550 15.2.18 Message Control (MC0 to MC15) R/W of MCx[1] bits amendedDescription of MCx[1] bits 3 to 0amended

553, 554 15.2.19 Message Data (MD0 to MD15) Bit descriptions amended

559 15.3.2 Initialization after Hardware Reset IRR0 Clearing Added

559 Bit Rate Settings Variable SJW restriction amended


563 15.3.3 Transmit Mode

Initialization (After Hardware Reset Only)

IRR0 Clearing Added

566 Message transmission and interrupts · Message transmission completionand interrupt Description amended

568 15.3.4 Receive Mode

Initialization (After Hardware Reset Only)

IRR0 Clearing Added

575 15.3.5 HCAN Sleep ModeClearing by CAN bus operation

Description amended

580 15.5 Usage Notes

1. Reset Description amended

7. Register retention during standby Added

603 to610

Section 17 D/A Converter[Provided in the H8S/2626 Series only]

Added

629, 630 19.5.6 Flash Memory Power Control Register(FLPWCR)

Added

667 19.12 Flash Memory and Power-Down States Amendments associated with additionof subclock function

675 to686

Section 20 Clock Pulse Generator Amendments associated with additionof subclock function

687 to702

Section 21A Power-Down Modes[H8S/2623 Series] (no subclock function)

Divided by series

690 21A.2.1 Standby Control Register (SBYCR) Initial value of bits 6 and 4 amended

703 to728

Section 21B Power-Down Modes[H8S/2626 Series] (subclock function provided)

Divided by series

708 21B.2.1 Standby Control Register (SBYCR) Initial value of bits 6 and 4 amended

729 Table 22-1 Absolute Maximum Ratings Amendments associated with additionof pins OSC1 and OSC2

730 to732

Table 22-2 DC Characteristics Amendments associated with additionof pins OSC1 and OSC2Amendments associated with additionof subclock functionAmendments associated with additionof D/A converter

733 Figure 22-1 Output Load Circuit Amended

734 Table 22-4 Clock Timing Amendments associated with additionof subclock function

736 Table 22-5 Control Signal Timing Conditions: ¿ value amended

738 Table 22-6 Bus Timing Conditions: ¿ value amended


745, 746 Table 22-7 Timing of On-Chip SupportingModules

Conditions: ¿ value amendedBUZZ output delay time added

749 Figure 22-22 WDT1 Output Timing Added

750 Table 22-8 A/D Conversion Characteristics Conversion time amended

751 22.5 D/A Conversion Characteristics Added

830 to844

B.1 Address AddedH'FDAC DADR2H'FDAD DADR3H'FDAE DADR23H'FFA2 TCSR1/TCNT1H'FFA3 TCNT1H'FFAC FLPWCR

845 to994

B.2 Functions Registers for which amendments havebeen made in this manualH'F800 MCRH'F801 GSRH'F804 MBCRH'F806 TXPRH'F808 TXCRH'F80A TXACKH'F80C ABACKH'F812 IRRH'F816 IMRH'F81C LAFMLH'F81E LAFMHH'F820ÑH'F898 MC0ÑMC15H'F8B0ÑH'F928 MD0ÑMD15H'FDE4 SBYCRH'FDE6 SCKCRH'FDE8ÑH'FDEA

MSTPCRAÑMSTPCRCH'FDEB PFCRH'FDEC LPWRCRH'FE39 PADDRH'FE40 PAPCRH'FE47 PAODRH'FEC0ÑH'FECC IPRAÑIPRMH'FF09 PADRH'FFB9 PORTA

1006 Figure C-4 (e) Port A Block Diagram (PinsPA4 and PA5)

Amended

1016 Figure C-9 (c) Port F Block Diagram in theH8S/2626 Series (Pin PF1)

Added

1027 Appendix F Product Code Lineup Addition of H8S/2626 Series

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Contents

Section 1 Overview ........................................................................................................... 11.1 Overview............................................................................................................................ 11.2 Internal Block Diagram ..................................................................................................... 61.3 Pin Descriptions................................................................................................................. 8

1.3.1 Pin Arrangement .................................................................................................. 81.3.2 Pin Functions in Each Operating Mode................................................................ 101.3.3 Pin Functions........................................................................................................ 18

Section 2 CPU..................................................................................................................... 232.1 Overview............................................................................................................................ 23

2.1.1 Features ................................................................................................................ 232.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU .................................. 242.1.3 Differences from H8/300 CPU............................................................................. 252.1.4 Differences from H8/300H CPU.......................................................................... 25

2.2 CPU Operating Modes ...................................................................................................... 262.3 Address Space.................................................................................................................... 312.4 Register Configuration ...................................................................................................... 32

2.4.1 Overview .............................................................................................................. 322.4.2 General Registers.................................................................................................. 332.4.3 Control Registers.................................................................................................. 342.4.4 Initial Register Values .......................................................................................... 36

2.5 Data Formats...................................................................................................................... 372.5.1 General Register Data Formats ............................................................................ 372.5.2 Memory Data Formats.......................................................................................... 39

2.6 Instruction Set.................................................................................................................... 402.6.1 Overview .............................................................................................................. 402.6.2 Instructions and Addressing Modes ..................................................................... 412.6.3 Table of Instructions Classified by Function........................................................ 432.6.4 Basic Instruction Formats..................................................................................... 52

2.7 Addressing Modes and Effective Address Calculation ..................................................... 542.7.1 Addressing Mode.................................................................................................. 542.7.2 Effective Address Calculation.............................................................................. 57

2.8 Processing States ............................................................................................................... 612.8.1 Overview .............................................................................................................. 612.8.2 Reset State ............................................................................................................ 622.8.3 Exception-Handling State .................................................................................... 632.8.4 Program Execution State ...................................................................................... 662.8.5 Bus-Released State ............................................................................................... 662.8.6 Power-Down State................................................................................................ 66

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2.9 Basic Timing...................................................................................................................... 672.9.1 Overview .............................................................................................................. 672.9.2 On-Chip Memory (ROM, RAM) ......................................................................... 672.9.3 On-Chip Supporting Module Access Timing....................................................... 692.9.4 On-Chip HCAN Module Access Timing ............................................................. 712.9.5 External Address Space Access Timing............................................................... 72

2.10 Usage Note ........................................................................................................................ 722.10.1 TAS Instruction .................................................................................................... 72

Section 3 MCU Operating Modes ................................................................................ 733.1 Overview............................................................................................................................ 73

3.1.1 Operating Mode Selection.................................................................................... 733.1.2 Register Configuration ......................................................................................... 74

3.2 Register Descriptions......................................................................................................... 743.2.1 Mode Control Register (MDCR).......................................................................... 743.2.2 System Control Register (SYSCR) ...................................................................... 753.2.3 Pin Function Control Register (PFCR) ................................................................ 76

3.3 Operating Mode Descriptions............................................................................................ 783.3.1 Mode 4.................................................................................................................. 783.3.2 Mode 5.................................................................................................................. 783.3.3 Mode 6.................................................................................................................. 783.3.4 Mode 7.................................................................................................................. 78

3.4 Pin Functions in Each Operating Mode............................................................................. 793.5 Address Map in Each Operating Mode ............................................................................. 79

Section 4 Exception Handling........................................................................................ 834.1 Overview............................................................................................................................ 83

4.1.1 Exception Handling Types and Priority ............................................................... 834.1.2 Exception Handling Operation ............................................................................. 844.1.3 Exception Vector Table........................................................................................ 84

4.2 Reset .................................................................................................................................. 864.2.1 Overview .............................................................................................................. 864.2.2 Reset Sequence..................................................................................................... 864.2.3 Interrupts after Reset ............................................................................................ 884.2.4 State of On-Chip Supporting Modules after Reset Release ................................. 88

4.3 Traces ................................................................................................................................ 894.4 Interrupts............................................................................................................................ 904.5 Trap Instruction ................................................................................................................. 914.6 Stack Status after Exception Handling .............................................................................. 924.7 Notes on Use of the Stack.................................................................................................. 93

Section 5 Interrupt Controller ........................................................................................ 955.1 Overview............................................................................................................................ 95

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5.1.1 Features ................................................................................................................ 955.1.2 Block Diagram ..................................................................................................... 965.1.3 Pin Configuration ................................................................................................. 975.1.4 Register Configuration ......................................................................................... 97

5.2 Register Descriptions......................................................................................................... 985.2.1 System Control Register (SYSCR) ...................................................................... 985.2.2 Interrupt Priority Registers A to K, M (IPRA to IPRK, IPRM)........................... 995.2.3 IRQ Enable Register (IER) .................................................................................. 1005.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 1015.2.5 IRQ Status Register (ISR) .................................................................................... 102

5.3 Interrupt Sources................................................................................................................ 1035.3.1 External Interrupts................................................................................................ 1035.3.2 Internal Interrupts ................................................................................................. 1045.3.3 Interrupt Exception Handling Vector Table ......................................................... 104

5.4 Interrupt Operation ............................................................................................................ 1085.4.1 Interrupt Control Modes and Interrupt Operation ................................................ 1085.4.2 Interrupt Control Mode 0...................................................................................... 1115.4.3 Interrupt Control Mode 2...................................................................................... 1135.4.4 Interrupt Exception Handling Sequence .............................................................. 1155.4.5 Interrupt Response Times..................................................................................... 116

5.5 Usage Notes ....................................................................................................................... 1175.5.1 Contention between Interrupt Generation and Disabling..................................... 1175.5.2 Instructions that Disable Interrupts ...................................................................... 1185.5.3 Times when Interrupts are Disabled..................................................................... 1185.5.4 Interrupts during Execution of EEPMOV Instruction.......................................... 119

5.6 DTC Activation by Interrupt ............................................................................................. 1195.6.1 Overview .............................................................................................................. 1195.6.2 Block Diagram...................................................................................................... 1195.6.3 Operation.............................................................................................................. 120

Section 6 PC Break Controller (PBC) ......................................................................... 1236.1 Overview............................................................................................................................ 123

6.1.1 Features ................................................................................................................ 1236.1.2 Block Diagram...................................................................................................... 1246.1.3 Register Configuration ......................................................................................... 125

6.2 Register Descriptions......................................................................................................... 1256.2.1 Break Address Register A (BARA) ..................................................................... 1256.2.2 Break Address Register B (BARB)...................................................................... 1266.2.3 Break Control Register A (BCRA) ...................................................................... 1266.2.4 Break Control Register B (BCRB) ....................................................................... 1286.2.5 Module Stop Control Register C (MSTPCRC).................................................... 128

6.3 Operation ........................................................................................................................... 1296.3.1 PC Break Interrupt Due to Instruction Fetch........................................................ 129

iv

6.3.2 PC Break Interrupt Due to Data Access ............................................................... 1296.3.3 Notes on PC Break Interrupt Handling ................................................................ 1306.3.4 Operation in Transitions to Power-Down Modes ................................................ 1306.3.5 PC Break Operation in Continuous Data Transfer ............................................... 1316.3.6 When Instruction Execution is Delayed by One State ......................................... 1326.3.7 Additional Notes .................................................................................................. 133

Section 7 Bus Controller.................................................................................................. 1357.1 Overview............................................................................................................................ 135

7.1.1 Features ................................................................................................................ 1357.1.2 Block Diagram...................................................................................................... 1367.1.3 Pin Configuration ................................................................................................. 1377.1.4 Register Configuration ......................................................................................... 138

7.2 Register Descriptions......................................................................................................... 1397.2.1 Bus Width Control Register (ABWCR) ............................................................... 1397.2.2 Access State Control Register (ASTCR).............................................................. 1407.2.3 Wait Control Registers H and L (WCRH, WCRL).............................................. 1417.2.4 Bus Control Register H (BCRH).......................................................................... 1457.2.5 Bus Control Register L (BCRL)........................................................................... 1477.2.6 Pin Function Control Register (PFCR) ................................................................ 148

7.3 Overview of Bus Control................................................................................................... 1507.3.1 Area Partitioning .................................................................................................. 1507.3.2 Bus Specifications ................................................................................................ 1517.3.3 Memory Interfaces................................................................................................ 1527.3.4 Interface Specifications for Each Area................................................................. 153

7.4 Basic Bus Interface............................................................................................................ 1547.4.1 Overview .............................................................................................................. 1547.4.2 Data Size and Data Alignment ............................................................................. 1547.4.3 Valid Strobes ........................................................................................................ 1567.4.4 Basic Timing ........................................................................................................ 1577.4.5 Wait Control ......................................................................................................... 165

7.5 Burst ROM Interface ......................................................................................................... 1677.5.1 Overview .............................................................................................................. 1677.5.2 Basic Timing ........................................................................................................ 1677.5.3 Wait Control ......................................................................................................... 169

7.6 Idle Cycle........................................................................................................................... 1707.6.1 Operation.............................................................................................................. 1707.6.2 Pin States in Idle Cycle ........................................................................................ 172

7.7 Write Data Buffer Function ............................................................................................... 1737.8 Bus Release........................................................................................................................ 174

7.8.1 Overview .............................................................................................................. 1747.8.2 Operation.............................................................................................................. 1747.8.3 Pin States in External Bus Released State............................................................ 175

v

7.8.4 Transition Timing................................................................................................. 1767.8.5 Usage Note ........................................................................................................... 177

7.9 Bus Arbitration .................................................................................................................. 1777.9.1 Overview .............................................................................................................. 1777.9.2 Operation.............................................................................................................. 1777.9.3 Bus Transfer Timing ............................................................................................ 178

7.10 Resets and the Bus Controller............................................................................................ 178

Section 8 Data Transfer Controller (DTC) ................................................................ 1798.1 Overview............................................................................................................................ 179

8.1.1 Features ................................................................................................................ 1798.1.2 Block Diagram...................................................................................................... 1808.1.3 Register Configuration ......................................................................................... 181

8.2 Register Descriptions......................................................................................................... 1828.2.1 DTC Mode Register A (MRA)............................................................................. 1828.2.2 DTC Mode Register B (MRB) ............................................................................. 1848.2.3 DTC Source Address Register (SAR).................................................................. 1858.2.4 DTC Destination Address Register (DAR).......................................................... 1858.2.5 DTC Transfer Count Register A (CRA) .............................................................. 1858.2.6 DTC Transfer Count Register B (CRB) ............................................................... 1868.2.7 DTC Enable Registers (DTCER) ......................................................................... 1868.2.8 DTC Vector Register (DTVECR) ........................................................................ 1878.2.9 Module Stop Control Register A (MSTPCRA).................................................... 188

8.3 Operation ........................................................................................................................... 1898.3.1 Overview .............................................................................................................. 1898.3.2 Activation Sources................................................................................................ 1918.3.3 DTC Vector Table ................................................................................................ 1928.3.4 Location of Register Information in Address Space ............................................ 1958.3.5 Normal Mode........................................................................................................ 1968.3.6 Repeat Mode ........................................................................................................ 1978.3.7 Block Transfer Mode............................................................................................ 1988.3.8 Chain Transfer...................................................................................................... 2008.3.9 Operation Timing ................................................................................................. 2018.3.10 Number of DTC Execution States........................................................................ 2028.3.11 Procedures for Using DTC ................................................................................... 2048.3.12 Examples of Use of the DTC................................................................................ 205

8.4 Interrupts............................................................................................................................ 2088.5 Usage Notes ....................................................................................................................... 208

Section 9 I/O Ports ............................................................................................................ 2099.1 Overview............................................................................................................................ 2099.2 Port 1.................................................................................................................................. 213

9.2.1 Overview .............................................................................................................. 213

vi

9.2.2 Register Configuration ......................................................................................... 2149.2.3 Pin Functions........................................................................................................ 216

9.3 Port 4.................................................................................................................................. 2289.3.1 Overview .............................................................................................................. 2289.3.2 Register Configuration ......................................................................................... 2299.3.3 Pin Functions........................................................................................................ 229

9.4 Port 9.................................................................................................................................. 2309.4.1 Overview .............................................................................................................. 2309.4.2 Register Configuration ......................................................................................... 2319.4.3 Pin Functions........................................................................................................ 231

9.5 Port A................................................................................................................................. 2329.5.1 Overview .............................................................................................................. 2329.5.2 Register Configuration ......................................................................................... 2339.5.3 Pin Functions........................................................................................................ 2369.5.4 MOS Input Pull-Up Function ............................................................................... 239

9.6 Port B ................................................................................................................................. 2409.6.1 Overview .............................................................................................................. 2409.6.2 Register Configuration ......................................................................................... 2419.6.3 Pin Functions........................................................................................................ 2439.6.4 MOS Input Pull-Up Function ............................................................................... 252

9.7 Port C ................................................................................................................................. 2539.7.1 Overview .............................................................................................................. 2539.7.2 Register Configuration ......................................................................................... 2549.7.3 Pin Functions........................................................................................................ 2579.7.4 MOS Input Pull-Up Function ............................................................................... 262

9.8 Port D................................................................................................................................. 2639.8.1 Overview .............................................................................................................. 2639.8.2 Register Configuration ......................................................................................... 2649.8.3 Pin Functions........................................................................................................ 2669.8.4 MOS Input Pull-Up Function ............................................................................... 267

9.9 Port E ................................................................................................................................. 2689.9.1 Overview .............................................................................................................. 2689.9.2 Register Configuration ......................................................................................... 2699.9.3 Pin Functions........................................................................................................ 2719.9.4 MOS Input Pull-Up Function ............................................................................... 272

9.10 Port F ................................................................................................................................. 2739.10.1 Overview .............................................................................................................. 2739.10.2 Register Configuration ......................................................................................... 2749.10.3 Pin Functions........................................................................................................ 276

Section 10 16-Bit Timer Pulse Unit (TPU).................................................................. 27910.1 Overview............................................................................................................................ 279

10.1.1 Features ................................................................................................................ 279

vii

10.1.2 Block Diagram...................................................................................................... 28310.1.3 Pin Configuration ................................................................................................. 28410.1.4 Register Configuration ......................................................................................... 286

10.2 Register Descriptions......................................................................................................... 28810.2.1 Timer Control Register (TCR) ............................................................................. 28810.2.2 Timer Mode Register (TMDR) ............................................................................ 29310.2.3 Timer I/O Control Register (TIOR) ..................................................................... 29510.2.4 Timer Interrupt Enable Register (TIER) .............................................................. 30810.2.5 Timer Status Register (TSR) ................................................................................ 31110.2.6 Timer Counter (TCNT) ........................................................................................ 31510.2.7 Timer General Register (TGR) ............................................................................ 31610.2.8 Timer Start Register (TSTR)................................................................................ 31710.2.9 Timer Synchro Register (TSYR).......................................................................... 31810.2.10 Module Stop Control Register A (MSTPCRA).................................................... 319

10.3 Interface to Bus Master...................................................................................................... 32010.3.1 16-Bit Registers.................................................................................................... 32010.3.2 8-Bit Registers...................................................................................................... 320

10.4 Operation ........................................................................................................................... 32210.4.1 Overview .............................................................................................................. 32210.4.2 Basic Functions .................................................................................................... 32310.4.3 Synchronous Operation ........................................................................................ 32910.4.4 Buffer Operation .................................................................................................. 33110.4.5 Cascaded Operation.............................................................................................. 33510.4.6 PWM Modes ........................................................................................................ 33710.4.7 Phase Counting Mode .......................................................................................... 342

10.5 Interrupts............................................................................................................................ 34910.5.1 Interrupt Sources and Priorities............................................................................ 34910.5.2 DTC Activation .................................................................................................... 35110.5.3 A/D Converter Activation .................................................................................... 351

10.6 Operation Timing .............................................................................................................. 35210.6.1 Input/Output Timing ............................................................................................ 35210.6.2 Interrupt Signal Timing........................................................................................ 356

10.7 Usage Notes ....................................................................................................................... 360

Section 11 Programmable Pulse Generator (PPG) .................................................... 37111.1 Overview............................................................................................................................ 371

11.1.1 Features ................................................................................................................ 37111.1.2 Block Diagram...................................................................................................... 37211.1.3 Pin Configuration ................................................................................................. 37311.1.4 Registers ............................................................................................................... 374

11.2 Register Descriptions......................................................................................................... 37511.2.1 Next Data Enable Registers H and L (NDERH, NDERL)................................... 37511.2.2 Output Data Registers H and L (PODRH, PODRL)............................................ 376

viii

11.2.3 Next Data Registers H and L (NDRH, NDRL).................................................... 37711.2.4 Notes on NDR Access.......................................................................................... 37711.2.5 PPG Output Control Register (PCR).................................................................... 37911.2.6 PPG Output Mode Register (PMR)...................................................................... 38111.2.7 Port 1 Data Direction Register (P1DDR) ............................................................. 38411.2.8 Module Stop Control Register A (MSTPCRA).................................................... 384

11.3 Operation ........................................................................................................................... 38511.3.1 Overview .............................................................................................................. 38511.3.2 Output Timing ...................................................................................................... 38611.3.3 Normal Pulse Output ............................................................................................ 38711.3.4 Non-Overlapping Pulse Output ............................................................................ 38911.3.5 Inverted Pulse Output ........................................................................................... 39211.3.6 Pulse Output Triggered by Input Capture ............................................................ 393

11.4 Usage Notes ....................................................................................................................... 394

Section 12 Watchdog Timer ............................................................................................. 39712.1 Overview............................................................................................................................ 397


12.2 Register Descriptions......................................................................................................... 40112.2.1 Timer Counter (TCNT) ........................................................................................ 40112.2.2 Timer Control/Status Register (TCSR) ................................................................ 40112.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 40612.2.4 Pin Function Control Register (PFCR) ................................................................ 40712.2.5 Notes on Register Access ..................................................................................... 408

12.3 Operation ........................................................................................................................... 41012.3.1 Watchdog Timer Operation.................................................................................. 41012.3.2 Interval Timer Operation...................................................................................... 41212.3.3 Timing of Setting Overflow Flag (OVF).............................................................. 41212.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF) ......................... 413


12.5.1 Contention between Timer Counter (TCNT) Write and Increment ..................... 41412.5.2 Changing Value of PSS and CKS2 to CKS0........................................................ 41512.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode................ 41512.5.4 System Reset by WDTOVF Signal ...................................................................... 41512.5.5 Internal Reset in Watchdog Timer Mode ............................................................. 415

Section 13 Serial Communication Interface (SCI) .................................................... 41713.1 Overview............................................................................................................................ 417

13.1.1 Features ................................................................................................................ 417

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13.1.2 Block Diagram...................................................................................................... 41913.1.3 Pin Configuration ................................................................................................. 42013.1.4 Register Configuration ......................................................................................... 421

13.2 Register Descriptions......................................................................................................... 42213.2.1 Receive Shift Register (RSR)............................................................................... 42213.2.2 Receive Data Register (RDR) .............................................................................. 42213.2.3 Transmit Shift Register (TSR).............................................................................. 42313.2.4 Transmit Data Register (TDR) ............................................................................. 42313.2.5 Serial Mode Register (SMR)................................................................................ 42413.2.6 Serial Control Register (SCR).............................................................................. 42713.2.7 Serial Status Register (SSR)................................................................................. 43113.2.8 Bit Rate Register (BRR)....................................................................................... 43513.2.9 Smart Card Mode Register (SCMR) .................................................................... 44413.2.10 Module Stop Control Register B (MSTPCRB).................................................... 445

13.3 Operation ........................................................................................................................... 44713.3.1 Overview .............................................................................................................. 44713.3.2 Operation in Asynchronous Mode........................................................................ 44913.3.3 Multiprocessor Communication Function............................................................ 46013.3.4 Operation in Clocked Synchronous Mode ........................................................... 468

13.4 SCI Interrupts .................................................................................................................... 47613.5 Usage Notes ....................................................................................................................... 478

Section 14 Smart Card Interface...................................................................................... 48714.1 Overview............................................................................................................................ 487


14.2 Register Descriptions......................................................................................................... 49114.2.1 Smart Card Mode Register (SCMR) .................................................................... 49114.2.2 Serial Status Register (SSR)................................................................................. 49314.2.3 Serial Mode Register (SMR)................................................................................ 49514.2.4 Serial Control Register (SCR).............................................................................. 497

14.3 Operation ........................................................................................................................... 49814.3.1 Overview .............................................................................................................. 49814.3.2 Pin Connections.................................................................................................... 49814.3.3 Data Format.......................................................................................................... 50014.3.4 Register Settings................................................................................................... 50214.3.5 Clock .................................................................................................................... 50414.3.6 Data Transfer Operations ..................................................................................... 50614.3.7 Operation in GSM Mode...................................................................................... 51314.3.8 Operation in Block Transfer Mode ...................................................................... 514

14.4 Usage Notes ....................................................................................................................... 515

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Section 15 Hitachi Controller Area Network (HCAN) ............................................ 51915.1 Overview............................................................................................................................ 519


15.2 Register Descriptions......................................................................................................... 52415.2.1 Master Control Register (MCR)........................................................................... 52415.2.2 General Status Register (GSR)............................................................................. 52515.2.3 Bit Configuration Register (BCR)........................................................................ 52715.2.4 Mailbox Configuration Register (MBCR)............................................................ 53115.2.5 Transmit Wait Register (TXPR) .......................................................................... 53215.2.6 Transmit Wait Cancel Register (TXCR).............................................................. 53315.2.7 Transmit Acknowledge Register (TXACK) ........................................................ 53415.2.8 Abort Acknowledge Register (ABACK).............................................................. 53515.2.9 Receive Complete Register (RXPR) .................................................................... 53615.2.10 Remote Request Register (RFPR)........................................................................ 53715.2.11 Interrupt Register (IRR) ....................................................................................... 53815.2.12 Mailbox Interrupt Mask Register (MBIMR)........................................................ 54215.2.13 Interrupt Mask Register (IMR) ............................................................................ 54315.2.14 Receive Error Counter (REC) .............................................................................. 54515.2.15 Transmit Error Counter (TEC) ............................................................................. 54615.2.16 Unread Message Status Register (UMSR) ........................................................... 54615.2.17 Local Acceptance Filter Masks (LAFML, LAFMH) ........................................... 54715.2.18 Message Control (MC0 to MC15)........................................................................ 54915.2.19 Message Data (MD0 to MD15)............................................................................ 55315.2.20 Module Stop Control Register C (MSTPCRC).................................................... 555

15.3 Operation ........................................................................................................................... 55615.3.1 Hardware and Software Resets............................................................................. 55615.3.2 Initialization after Hardware Reset ...................................................................... 55915.3.3 Transmit Mode ..................................................................................................... 56215.3.4 Receive Mode....................................................................................................... 56815.3.5 HCAN Sleep Mode .............................................................................................. 57415.3.6 HCAN Halt Mode ................................................................................................ 57615.3.7 Interrupt Interface................................................................................................. 57615.3.8 DTC Interface....................................................................................................... 578

15.4 CAN Bus Interface ............................................................................................................ 57915.5 Usage Notes ....................................................................................................................... 580

Section 16 A/D Converter ................................................................................................. 58116.1 Overview............................................................................................................................ 581

16.1.1 Features ................................................................................................................ 58116.1.2 Block Diagram...................................................................................................... 582

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16.1.3 Pin Configuration ................................................................................................. 58316.1.4 Register Configuration ......................................................................................... 584

16.2 Register Descriptions......................................................................................................... 58516.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 58516.2.2 A/D Control/Status Register (ADCSR)................................................................ 58616.2.3 A/D Control Register (ADCR)............................................................................. 58916.2.4 Module Stop Control Register A (MSTPCRA).................................................... 590

16.3 Interface to Bus Master...................................................................................................... 59116.4 Operation ........................................................................................................................... 592

16.4.1 Single Mode (SCAN = 0) ..................................................................................... 59216.4.2 Scan Mode (SCAN = 1) ....................................................................................... 59416.4.3 Input Sampling and A/D Conversion Time.......................................................... 59616.4.4 External Trigger Input Timing ............................................................................. 597


Section 17 D/A Converter [Provided in the H8S/2626 Series only] .................... 60317.1 Overview............................................................................................................................ 603


17.2 Register Descriptions......................................................................................................... 60617.2.1 D/A Data Registers 2 and 3 (DADR2, DADR3).................................................. 60617.2.2 D/A Control Register 23 (DACR23).................................................................... 60617.2.3 Module Stop Control Register C (MSTPCRC).................................................... 608

17.3 Operation ........................................................................................................................... 609

Section 18 RAM ................................................................................................................... 61118.1 Overview............................................................................................................................ 611

18.1.1 Block Diagram...................................................................................................... 61118.1.2 Register Configuration ......................................................................................... 612

18.2 Register Descriptions......................................................................................................... 61218.2.1 System Control Register (SYSCR) ...................................................................... 612

18.3 Operation ........................................................................................................................... 61318.4 Usage Notes ....................................................................................................................... 613

Section 19 ROM ................................................................................................................... 61519.1 Features.............................................................................................................................. 61519.2 Overview............................................................................................................................ 616

19.2.1 Block Diagram...................................................................................................... 61619.2.2 Mode Transitions.................................................................................................. 61719.2.3 On-Board Programming Modes ........................................................................... 618

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19.2.4 Flash Memory Emulation in RAM....................................................................... 62019.2.5 Differences between Boot Mode and User Program Mode.................................. 62119.2.6 Block Configuration ............................................................................................. 622

19.3 Pin Configuration .............................................................................................................. 62219.4 Register Configuration ...................................................................................................... 62319.5 Register Descriptions......................................................................................................... 623

19.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 62319.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 62619.5.3 Erase Block Register 1 (EBR1)............................................................................ 62719.5.4 Erase Block Register 2 (EBR2)............................................................................ 62719.5.5 RAM Emulation Register (RAMER) ................................................................... 62819.5.6 Flash Memory Power Control Register (FLPWCR) ............................................ 62919.5.7 Serial Control Register X (SCRX) ....................................................................... 630

19.6 On-Board Programming Modes ........................................................................................ 63119.6.1 Boot Mode............................................................................................................ 63119.6.2 User Program Mode ............................................................................................. 636

19.7 Flash Memory Programming/Erasing................................................................................ 63819.7.1 Program Mode...................................................................................................... 64019.7.2 Program-Verify Mode .......................................................................................... 64119.7.3 Erase Mode........................................................................................................... 64519.7.4 Erase-Verify Mode ............................................................................................... 645

19.8 Protection........................................................................................................................... 64719.8.1 Hardware Protection............................................................................................. 64719.8.2 Software Protection .............................................................................................. 64819.8.3 Error Protection .................................................................................................... 649

19.9 Flash Memory Emulation in RAM.................................................................................... 65119.10 Interrupt Handling when Programming/Erasing Flash Memory ....................................... 65319.11 Flash Memory Programmer Mode .................................................................................... 653

19.11.1 Socket Adapter Pin Correspondence Diagram ................................................... 65419.11.2 Programmer Mode Operation............................................................................. 65619.11.3 Memory Read Mode........................................................................................... 65719.11.4 Auto-Program Mode .......................................................................................... 66019.11.5 Auto-Erase Mode................................................................................................ 66219.11.6 Status Read Mode............................................................................................... 66419.11.7 Status Polling...................................................................................................... 66519.11.8 Programmer Mode Transition Time................................................................... 66519.11.9 Notes on Memory Programming........................................................................ 666

19.12 Flash Memory and Power-Down States ............................................................................ 66719.12.1 Note on Power-Down States .............................................................................. 667

19.13 Flash Memory Programming and Erasing Precautions ..................................................... 66819.14 Note on Switching from F-ZTAT Version to Mask ROM Version .................................. 673

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Section 20 Clock Pulse Generator .................................................................................. 67520.1 Overview............................................................................................................................ 675

20.1.1 Block Diagram...................................................................................................... 67620.1.2 Register Configuration ......................................................................................... 676

20.2 Register Descriptions......................................................................................................... 67720.2.1 System Clock Control Register (SCKCR) ........................................................... 67720.2.2 Low-Power Control Register (LPWRCR)............................................................ 678

20.3 Oscillator............................................................................................................................ 67920.3.1 Connecting a Crystal Resonator ........................................................................... 67920.3.2 External Clock Input ............................................................................................ 682

20.4 PLL Circuit ........................................................................................................................ 68420.5 Medium-Speed Clock Divider........................................................................................... 68420.6 Bus Master Clock Selection Circuit .................................................................................. 68420.7 Subclock Oscillator............................................................................................................ 68520.8 Subclock Waveform Shaping Circuit ................................................................................ 68620.9 Note on Crystal Resonator................................................................................................. 686

Section 21A Power-Down Modes [H8S/2623 Series] ............................................. 68721A.1 Overview ........................................................................................................................ 687

21A.1.1 Register Configuration ................................................................................... 69021A.2 Register Descriptions...................................................................................................... 690

21A.2.1 Standby Control Register (SBYCR) .............................................................. 69021A.2.2 System Clock Control Register (SCKCR) ..................................................... 69221A.2.3 Low-Power Control Register (LPWRCR)...................................................... 69321A.2.4 Module Stop Control Register (MSTPCR) .................................................... 694

21A.3 Medium-Speed Mode ..................................................................................................... 69521A.4 Sleep Mode..................................................................................................................... 696

21A.4.1 Sleep Mode..................................................................................................... 69621A.4.2 Exiting Sleep Mode........................................................................................ 696

21A.5 Module Stop Mode ......................................................................................................... 69621A.5.1 Module Stop Mode ......................................................................................... 69621A.5.2 Usage Notes.................................................................................................... 698

21A.6 Software Standby Mode ................................................................................................. 69821A.6.1 Software Standby Mode ................................................................................. 69821A.6.2 Clearing Software Standby Mode .................................................................. 69821A.6.3 Setting Oscillation Stabilization Time after Clearing Software

Standby Mode ................................................................................................ 69921A.6.4 Software Standby Mode Application Example .............................................. 70021A.6.5 Usage Notes.................................................................................................... 701

21A.7 Hardware Standby Mode................................................................................................ 70121A.7.1 Hardware Standby Mode................................................................................ 70121A.7.2 Hardware Standby Mode Timing ................................................................... 702

21A.8 ø Clock Output Disabling Function................................................................................ 702

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Section 21B Power-Down Modes [H8S/2626 Series] ............................................. 70321B.1 Overview ........................................................................................................................ 703

21B.1.1 Register Configuration ................................................................................... 70721B.2 Register Descriptions...................................................................................................... 708

21B.2.1 Standby Control Register (SBYCR) .............................................................. 70821B.2.2 System Clock Control Register (SCKCR) ..................................................... 71021B.2.3 Low-Power Control Register (LPWRCR)...................................................... 71121B.2.4 Timer Control/Status Register (TCSR) .......................................................... 71321B.2.5 Module Stop Control Register (MSTPCR) .................................................... 715

21B.3 Medium-Speed Mode ..................................................................................................... 71621B.4 Sleep Mode..................................................................................................................... 717

21B.4.1 Sleep Mode..................................................................................................... 71721B.4.2 Exiting Sleep Mode........................................................................................ 717

21B.5 Module Stop Mode ......................................................................................................... 71721B.5.1 Module Stop Mode ......................................................................................... 71721B.5.2 Usage Notes.................................................................................................... 719

21B.6 Software Standby Mode ................................................................................................. 71921B.6.1 Software Standby Mode ................................................................................. 71921B.6.2 Clearing Software Standby Mode .................................................................. 71921B.6.3 Setting Oscillation Stabilization Time after Clearing Software

Standby Mode ................................................................................................ 72021B.6.4 Software Standby Mode Application Example .............................................. 72121B.6.5 Usage Notes.................................................................................................... 722

21B.7 Hardware Standby Mode................................................................................................ 72221B.7.1 Hardware Standby Mode................................................................................ 72221B.7.2 Hardware Standby Mode Timing ................................................................... 723

21B.8 Watch Mode ................................................................................................................... 72321B.8.1 Watch Mode ................................................................................................... 72321B.8.2 Exiting Watch Mode ...................................................................................... 72421B.8.3 Notes............................................................................................................... 724

21B.9 Sub-Sleep Mode ............................................................................................................. 72521B.9.1 Sub-Sleep Mode ............................................................................................. 72521B.9.2 Exiting Sub-Sleep Mode ................................................................................ 725

21B.10 Sub-Active Mode............................................................................................................ 72621B.10.1 Sub-Active Mode............................................................................................ 72621B.10.2 Exiting Sub-Active Mode............................................................................... 726

21B.11 Direct Transitions ........................................................................................................... 72721B.11.1 Overview of Direct Transitions...................................................................... 727

21B.12 ø Clock Output Disabling Function................................................................................ 727

Section 22 Electrical Characteristics.............................................................................. 72922.1 Absolute Maximum Ratings.............................................................................................. 72922.2 DC Characteristics ............................................................................................................. 730

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22.3 AC Characteristics ............................................................................................................. 73322.3.1 Clock Timing........................................................................................................ 73422.3.2 Control Signal Timing.......................................................................................... 73522.3.3 Bus Timing ........................................................................................................... 73722.3.4 Timing of On-Chip Supporting Modules ............................................................. 743

22.4 A/D Conversion Characteristics ........................................................................................ 74722.5 D/A Conversion Characteristics ........................................................................................ 74822.6 Flash Memory Characteristics ........................................................................................... 74922.7 Usage Note ........................................................................................................................ 750

Appendix A Instruction Set.............................................................................................. 751A.1 Instruction List................................................................................................................... 751A.2 Instruction Codes ............................................................................................................... 776A.3 Operation Code Map.......................................................................................................... 791A.4 Number of States Required for Instruction Execution ...................................................... 795A.5 Bus States During Instruction Execution .......................................................................... 806A.6 Condition Code Modification............................................................................................ 820

Appendix B Internal I/O Register .................................................................................. 826B.1 Address .............................................................................................................................. 826B.2 Functions............................................................................................................................ 841

Appendix C I/O Port Block Diagrams.......................................................................... 991C.1 Port 1 Block Diagrams ...................................................................................................... 991C.2 Port 4 Block Diagram........................................................................................................ 997C.3 Port 9 Block Diagram........................................................................................................ 997C.4 Port A Block Diagrams...................................................................................................... 998C.5 Port B Block Diagram ....................................................................................................... 1003C.6 Port C Block Diagrams...................................................................................................... 1004C.7 Port D Block Diagram ....................................................................................................... 1008C.8 Port E Block Diagram........................................................................................................ 1009C.9 Port F Block Diagrams ...................................................................................................... 1010

Appendix D Pin States ....................................................................................................... 1019D.1 Port States in Each Mode .................................................................................................. 1019

Appendix E Timing of Transition to and Recovery from HardwareStandby Mode.............................................................................................. 1022

Appendix F Product Code Lineup ................................................................................. 1023

Appendix G Package Dimensions.................................................................................. 1024

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Section 1 Overview

1.1 Overview

The H8S/2626 Series and H8S/2623 Series are series of microcomputers (MCUs) that integrateperipheral functions required for system configuration together with an H8S/2600 CPU employingan original Hitachi architecture.

The H8S/2600 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit generalregisters and a concise, optimized instruction set designed for high-speed operation, and canaddress a 16-Mbyte linear address space. The instruction set is upward-compatible with H8/300and H8/300H CPU instructions at the object-code level, facilitating migration from the H8/300,H8/300L, or H8/300H Series.

On-chip peripheral functions required for system configuration include a data transfer controller(DTC) bus master, ROM and RAM memory, a16-bit timer-pulse unit (TPU), programmable pulsegenerator (PPG), watchdog timer (WDT), serial communication interface (SCI), Hitachi controllerarea network (HCAN), A/D converter, D/A converter (H8S/2626 Series only), and I/O ports.

The on-chip ROM is 256-kbyte flash memory (F-ZTAT™)* or 256-, 128-, or 64-kbyte maskROM. The ROM is connected to the CPU by a 16-bit data bus, enabling both byte and word datato be accessed in one state. Instruction fetching has been speeded up, and processing speedincreased.

Four operating modes, modes 4 to 7, are provided, and there is a choice of single-chip mode orexternal expansion mode.

The features of the H8S/2626 Series and H8S/2623 Series are shown in table 1-1.

Note: * F-ZTAT is a trademark of Hitachi, Ltd.

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Table 1-1 Overview

Item Specifications

CPU • General-register machine

Sixteen 16-bit general registers

(also usable as sixteen 8-bit registers or eight 32-bit registers)

• High-speed operation suitable for realtime control

Maximum operating frequency: 20 MHz

High-speed arithmetic operations

8/16/32-bit register-register add/subtract: 50 ns

16 × 16-bit register-register multiply: 200 ns

16 × 16 + 42-bit multiply and accumulate: 200 ns

32 ÷ 16-bit register-register divide: 1000 ns

• Instruction set suitable for high-speed operation

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