H8/3048B Group Hardware Manual - RS Components · Revision Date: Sep 27, 2006 8 H8/3048B Group...

8 H8/3048B GroupHardware Manual

REJ09B0325-0300

Renesas 8-Bit Single-Chip MicrocomputerH8 Family/H8/300H Series

H8/3048B HD6433048BHD6433048BV

H8/3048F-ONE HD64F3048BHD64F3048BV

Revision Date: Sep 27, 2006Rev. 3.00

UnknownThe revision list can be viewed directly by clicking the title page.

The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text.

Rev. 3.00 Sep 27, 2006 page ii of xxvi

1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.

2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.

3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com).

4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein.

5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.

6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials.

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8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.

1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.

Keep safety first in your circuit designs!

Notes regarding these materials

Rev. 3.00 Sep 27, 2006 page iii of xxvi

General Precautions on Handling of Product

1. Treatment of NC Pins

Note: Do not connect anything to the NC pins.The NC (not connected) pins are either not connected to any of the internal circuitry or areused as test pins or to reduce noise. If something is connected to the NC pins, theoperation of the LSI is not guaranteed.

2. Treatment of Unused Input Pins

Note: Fix all unused input pins to high or low level.Generally, the input pins of CMOS products are high-impedance input pins. If unused pinsare in their open states, intermediate levels are induced by noise in the vicinity, a pass-through current flows internally, and a malfunction may occur.

3. Processing before Initialization

Note: When power is first supplied, the product’s state is undefined.The states of internal circuits are undefined until full power is supplied throughout thechip and a low level is input on the reset pin. During the period where the states areundefined, the register settings and the output state of each pin are also undefined. Designyour system so that it does not malfunction because of processing while it is in thisundefined state. For those products which have a reset function, reset the LSI immediatelyafter the power supply has been turned on.

4. Prohibition of Access to Undefined or Reserved Addresses

Note: Access to undefined or reserved addresses is prohibited.The undefined or reserved addresses may be used to expand functions, or test registersmay have been be allocated to these addresses. Do not access these registers; the system’soperation is not guaranteed if they are accessed.

Rev. 3.00 Sep 27, 2006 page iv of xxvi

Rev. 3.00 Sep 27, 2006 page v of xxvi

Preface

The H8/3048B Group is a series of high-performance microcontrollers that integrate systemsupporting functions together with an H8/300H CPU core. In addition, the H8/3048F-ONE isequipped with an on-chip emulator (E10T)*2.

The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and aconcise, optimized instruction set designed for speed. It can address a 16-Mbyte linear addressspace.

The on-chip emulator (E10T)*2 has functions that allow it to emulate directly a microcontrollermounted on the user board. This makes possible on-board program debugging.

The on-chip supporting functions include ROM, RAM, a 16-bit integrated timer unit (ITU), aprogrammable timing pattern controller (TPC), a watchdog timer (WDT), a serial communicationinterface (SCI), an A/D converter, a D/A converter, I/O ports, a direct memory access controller(DMAC), a refresh controller, and other facilities. Of the two SCI channels, one has beenexpanded to support the ISO/IEC7816-3 smart card interface. Functions have also been added toreduce power consumption in battery-powered applications: individual modules can be placed instandby, and the frequency of the system clock supplied to the chip can be divided down undersoftware control.

The address space is divided into eight areas. The data bus width and access cycle length can beselected independently in each area, simplifying the connection of different types of memory.Seven operating modes (modes 1 to 7) are provided, offering a choice of data bus width andaddress space size.

With these features, the H8/3048B Group can be used to implement compact, high-performancesystems easily.

Versions with either flash memory (F-ZTAT™*1) or mask ROM as the on-chip ROM areavailable. This enables users to respond quickly and flexibly to changing application specificationsfrom the initial production stage through full-scale volume production.

This manual describes the H8/3048B Group hardware. For information on H8/3048 Groupproducts, please refer to the H8/3048 Group Hardware Manual. For details of the instruction set,refer to the H8/300H Series Programming Manual.

Notes: 1. F-ZTAT (Flexible ZTAT) is a trademark of Renesas Technology Corp.

2. An on-chip emulator (E10T) is not provided in the mask ROM version.

Rev. 3.00 Sep 27, 2006 page vi of xxvi

Notes on using the on-chip emulator (E10T) installed in the H8/3048F-ONE

H8/3048 Group products and H8/3048B Group products have different specifications regardingthe pin arrangement (pin 1, VCL), flash memory, and maximum operating frequency. Refer toComparison of H8/3048 Group Product Specifications for details of these differences.

Notes:When using an on-chip emulator (E10T) for H8/3048 program development and debugging, thefollowing restrictions must be noted.

1. Only programs in the on-chip flash memory can be developed and debugged. Consequently,emulation is not possible for programs in external memory or in the no-ROM mode.

2. Refresh controller and DMAC operation are not supported, so settings should not be made tothe registers for these modules.

3. During break mode of on-chip emulation, the watchdog timer stops counting. Accordingly, thecounter value may be invalid after resuming from the break mode.

4. The FWE (BRK) pin and pins P91, P93, and P95 are reserved for the E10T, and cannot beused.

5. Area H'F7000 to H'F7FFF in 1-M address mode (area H'FF7000 to H'FF77FF in 16-M addressmode) is used by the E10T, and is not available to the user.

6. The initial program instructions following a reset should be initialize stack pointer (SP) andread mode register (MDCR). (After initializing SP using the MOV.L instruction, use theMOV.B instruction to read the MDCR register.)

7. Emulation of the hardware standby mode is not supported.

Rev. 3.00 Sep 27, 2006 page vii of xxvi

Comparison of H8/3048 Group Product Specifications

There are eight members of the H8/3048 Group; the H8/3048F-ZTAT (H8/3048F*1, H8/3048F-ONE*2), H8/3048ZTAT, H8/3048 mask ROM version, H8/3048B mask ROM version, H8/3047mask ROM version, H8/3045 mask ROM version, and H8/3044 mask ROM version.

The specifications of each model is compared below.

Notes: 1. H8/3048F has dual power supply with flash memory installed.

2. H8/3048F-ONE has single power supply with flash memory and E10T installed.

HardwareManual

H8/3048 Group(Rev. 7.0)

H8/3048B Group(Rev. 3.0)

ROM Type ZTAT Mask ROM F-ZTAT Mask ROM

Model Type H8/3048 H8/3048 mask ROMversionH8/3047 mask ROMversionH8/3045 mask ROMversionH8/3044 mask ROMversion

H8/3048F H8/3048F-ONE H8/3048B maskROM version

Model Spec PROM model Mask ROM model Dual powersupply, flashmemory isinstalled

Single powersupply, flashmemory installed,internal step-down (5 Voperation model),high-speedoperation model

Mask ROMmodel

Refer to 1.4,DifferencesbetweenH8/3048F andH8/3048F-ONE.

Refer to 1.4.3,DifferencesbetweenH8/3048F andH8/3048F-ONE.

Model TypeNo.

HD6473048 HD6433048HD6433047HD6433045HD6433044

HD64F3048 HD64F3048B(5 V operationmodel)

HD64F3048BV(3 V operationmodel)

HD6433048B(5 V operationmodel)

HD6433048BV(3 V operationmodel)

PinAssignment

Refer to figure 1.2, Pin Arrangement of H8/3048ZTAT,H8/3048 Mask ROM Version, H8/3047 Mask ROMVersion, H8/3045 Mask ROM Version, H8/3044 MaskROM Version, and H8/3048F (FP-100B or TFP-100B, TopView), in section 1.

5-V operation models have a VCL pinand an external capacitor must beconnected.

Refer to figure 1.3, H8/3048F-ONEPin Arrangement (FP-100B or TFP-100B, Top View), in section 1.

Rev. 3.00 Sep 27, 2006 page viii of xxvi

HardwareManual

H8/3048 Group(Rev. 7.0)

H8/3048B Group(Rev. 3.0)

ROM Type ZTAT Mask ROM F-ZTAT Mask ROM

RAM Capacity 4 kbytes H8/3048: 4 kbytesH8/3047: 4 kbytesH8/3045: 2 kbytesH8/3044: 2 kbytes

4 kbytes 4 kbytes

ROM Capacity 128 kbytes H8/3048: 128 kbytesH8/3047: 96 kbytesH8/3045: 64 kbytesH8/3044: 32 kbytes

128 kbytes 128 kbytes

Flash Memory — — Refer to section19, FlashMemory(H8/3048F DualPower Supply).

Refer to section18, ROM(H8/3048F-ONE:Single PowerSupply, H8/3048BMask ROMVersion)

—

Clock PulseGenerator

Refer to section 20, Clock Pulse Generator. Refer to section 19, Clock PulseGenerator.

Refer to section 21, Power-Down State. Refer to section 20, Power-DownState.

Power-DownState

Clock oscillator settling time: Waiting time of up to 131072states

Clock oscillator settling time: Waitingtime of up to 262144 states

Refer to table 22.1, Electrical Characteristics of H8/3048Group Products, in section 22.

Refer to table 21.1, ElectricalCharacteristics of H8/3048 Groupand H8/3048B Group Products, insection 21.

ElectricalCharacteristics(Clock Rate)

1 to 18 MHz 1 to 16MHz

5 V operation models:2 to 25 MHz,3 V operation models:2 to 25 MHz.

List ofRegisters

Refer to table B.1, Comparison of H8/3048 Group Internal I/O Register Specifications, inappendix B.

Refer to appendix B.1, Addresses.

Notes onUsage

— — — Refer to section1.4, Notes onH8/3048F-ONE(Single PowerSupply)

—

On-chipEmulator(E10T)

— — — On-chip emulator(E10T)

—

Main Revisions for This Edition

Item Page Revision (See Manual for Details)

All — • Notification of change in company name amended

(Before) Hitachi, Ltd. → (After) Renesas Technology Corp.• Product naming convention amended

(Before) H8/3048B Series → (After) H8/3048B Group

1.3.1 PinArrangement

Figure 1.3 H8/3048BGroup PinArrangement (FP-100B or TFP-100B,Top View)

8 Note amended

Note: 1. For the 5 V operation product, this pin is used as theVCL terminal, and for the 3 V operation models, this pin is usedas the VCC terminal that requires an external capacitor.

1.3.3 Pin Functions

Table 1.4 PinFunctions

18, 19 Table amendedType Symbol Pin No. I/O Name and Function

A/D and D/Aconverters

AVCC 76 Input Power supply pin for the A/D and D/Aconverters. Connect to the system powersupply (VCC) when not using the A/D andD/A converters.

AVSS 86 Input Ground pin for the A/D and D/A converters.Connect to system ground (VSS).

VREF 77 Input Reference voltage input pin for the A/D andD/A converters. Connect to the systempower supply (VCC) when not using the A/Dand D/A converters.

1.4.2 Product TypeNames and Markings

Table 1.5 Differencesin H8/3048F andH8/3048F-ONE

21 Sample markings amendedDual Power SupplyModel: H8/3048F Single Power Supply Model: H8/3048F-ONE

Samplemarkings

H8/3048

HD64F3048F16

3J1 H8/3048F-ONE

PGM 5.0 B 0021

BK80090

64F3048F25

H8/3048F-ONE

PGM 3.3 B 0021

BK80090

64F3048VF25

Rev. 3.00 Sep 27, 2006 page ix of xxvi


5.5.4 Usage Notes onExternal Interrupts

Figure 5.9 IRQnFFlag When InterruptProcessing Is NotConducted

120 Figure amended

Read1

Write 0

Read1

Write 1

IRQb

Execution

Read1

Write 0

Read0

Write 0

Clear in error

Occurrence condition 1

IRQaF

IRQbF

Occurrence condition 2

10.2.3 Timer ModeRegister (TMDR)

Bit 6—Phase CountingMode Flag (MDF)

335 Table amendedCounting Direction Down-Counting Up-Counting

TCLKA pin ↑ High ↓ Low ↑ Low ↓ High

TCLKB pin Low ↑ High ↓ High ↑ Low ↓

13.2.8 Bit RateRegister (BRR)

Table 13.3 Examplesof Bit Rates and BRRSettings inAsynchronous Mode

473,475

Table amendedφφφφ (MHz)

3 3.6864 25

Bit Rate(bits/s) n N

Error(%) n N

Error(%) n N

Error(%)

110 1 212 0.03 2 64 0.70 3 110 –0.02

150 1 155 0.16 1 191 0.00 3 80 0.47

300 1 77 0.16 1 95 0.00 2 162 –0.15

600 0 155 0.16 0 191 0.00 2 80 0.47

1200 0 77 0.16 0 95 0.00 1 162 –0.15

2400 0 38 0.16 0 47 0.00 1 80 0.47

4800 0 19 –2.34 0 23 0.00 0 162 –0.15

9600 0 9 –2.34 0 11 0.00 0 80 0.47

19200 0 4 –2.34 0 5 0.00 0 40 –0.76

31250 0 2 0.00 0 3 –7.84 0 24 0.00

38400 0 1 22.07 0 2 0.00 0 19 1.73

13.3.2 Operation inAsynchronous Mode

Figure 13.8 Exampleof SCI ReceiveOperation (8-Bit Datawith Parity and OneStop Bit)

492 Figure amended

1Startbit

0 D0 D1 D7 0/1

Stopbit

1

DataParitybit

Startbit

0 D0 D1 D7 0/1

Stopbit

1

DataParitybit 1

Idle (mark)state

RDRF

FER

1 frame

Framing error,ERI request

RXI interrupt handlerreads data in RDR andclears RDRF flag to 0

RXIrequest

Rev. 3.00 Sep 27, 2006 page x of xxvi


13.3.3 MultiprocessorCommunication

Figure 13.11Example of SCITransmit Operation(8-Bit Data withMultiprocessor Bit andOne Stop Bit)

495 Figure amended

1Startbit

0 D0 D1 D7 0/1

Stopbit

1

Data

Multi-processorbit

Startbit

0 D0 D1 D7 0/1

Stopbit

1

Data 1

Idle (mark)state

TDRE

TEND

TXIrequest

TXI interrupt handlerwrites data in TDR andclears TDRE flag to 0

1 frame

TEI request

Multi-processorbit

TXIrequest

13.3.4 SynchronousOperation

Clock

500 Description amended

An internal clock generated by the on-chip baud rategenerator or an external clock input from the SCK pin can beselected by setting the C/A bit in SMR and the CKE1 andCKE0 bits in SCR. See table 13.9.

14.2.3 Serial ModeRegister (SMR)

Bit 7—GSM Mode(GM)

521 Table amendedBit 7: GM Description

0 Using the regular smart card interface mode

• The TEND flag is set 12.5 etu after the beginning of the start bit (Initial value)

• Clock output on/off control only1 Using the GSM mode smart card interface mode

• The TEND flag is set 11.0 etu after the beginning of the start bit

• Clock output on/off and fixed-(set by SCR)

high/fixed-low control

18.5.1 Flash MemoryControl Register 1(FLMCR1)

Bit 1—Erase Bit (E)

587 Note amended

Note: * Do not access flash memory while the E bit is set to 1.

Section 21 ElectricalCharacteristics

Table 21.1 ElectricalCharacteristics ofH8/3048 Group andH8/3048B GroupProducts

653,654

Table amended

H8/3048B Group

Item H8/3048ZTAT

H8/3048F-ONE(SinglePower

Supply)

H8/3048BMaskROM

VPP pin rating Yes — —Absolutemaximumratings

Flashmemorycharac-teristics*4

— See table21.11

—

Rev. 3.00 Sep 27, 2006 page xi of xxvi


21.2 ElectricalCharacteristics ofH8/3048B (MaskROM)

675 to689

Preliminary deleted

21.2.2 DCCharacteristics

Table 21.13 DCCharacteristics (2)

678 Conditions amended

Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V,VREF = 3.0 V to AVCC, VSS = AVSS = 0 V*

1, Ta = –20°C to +75°C(regular specifications), Ta = –40°C to +85°C (wide-rangespecifications)

B.1 Addresses (ForH8/3048F-ONE,H8/3048B Mask ROMVersion)

742 Note amended

Note: 4. Byte data must be used to access FLMCR1,FLMCR2, EBR, and RAMCR.Registers FLMCR1, FLMCR2, EBR, and RAMCR areimplemented in the flash memory version only. The maskROM version does not have these registers.

B.3 Function

ADCR

829 Table amended

H8/3048F-ONE Not include this registerH8/3048FH8/3048B mask ROM versionH8/3048ZTATH8/3048 mask ROM versionH8/3047 mask ROM versionH8/3045 mask ROM versionH8/3044 mask ROM version

Include this register

ADCR 829 Table amended

H8/3048F-ONE Include this registerH8/3048FH8/3048B mask ROM versionH8/3048ZTATH8/3048 mask ROM versionH8/3047 mask ROM versionH8/3045 mask ROM versionH8/3044 mask ROM version

Not include this register

SYSCR 833 Table amendedStandby timer select 2 to 0

STS2

0

1

H8/3048F-ONEH8/3048B mask ROM version

Standby Timer

Waiting time = 8,192 states Waiting time = 16,384 statesWaiting time = 32,768 statesWaiting time = 65,536 statesWaiting time = 131,072 statesWaiting time = 262,144 states

Bit 6

Note: * H8/3048F H8/3048ZTAT H8/3048 mask ROM version H8/3047 mask ROM version H8/3045 mask ROM version

STS1

0

1

0

Bit 5

STS0

0101

1Waiting time = 1,024 states1 0Illegal setting

*

Waiting time = 8,192 states Waiting time = 16,384 statesWaiting time = 32,768 statesWaiting time = 65,536 statesWaiting time = 131,072 statesWaiting time = 1,024 statesIllegal settingIllegal setting1

Bit 4

0

Rev. 3.00 Sep 27, 2006 page xii of xxvi

H8/3044 mask ROM version

Rev. 3.00 Sep 27, 2006 page xiii of xxvi

Contents

Section 1 Overview............................................................................................................. 11.1 Overview........................................................................................................................... 11.2 Block Diagram .................................................................................................................. 61.3 Pin Description.................................................................................................................. 7

1.3.1 Pin Arrangement .................................................................................................. 71.3.2 Pin Assignments in Each Mode ........................................................................... 91.3.3 Pin Functions ....................................................................................................... 15

1.4 Notes on H8/3048F-ONE (Single Power Supply) ............................................................ 201.4.1 Voltage Application ............................................................................................. 201.4.2 Product Type Names and Markings..................................................................... 211.4.3 Differences between H8/3048F and H8/3048F-ONE .......................................... 211.4.4 VCL Pin.................................................................................................................. 261.4.5 Note on Changeover to H8/3048 Group Mask ROM Version............................. 27

1.5 Setting Oscillation Settling Wait Time ............................................................................. 281.6 Notes on Crystal Resonator Connection ........................................................................... 28

Section 2 CPU ...................................................................................................................... 292.1 Overview........................................................................................................................... 29

2.1.1 Features................................................................................................................ 292.1.2 Differences from H8/300 CPU ............................................................................ 30

2.2 CPU Operating Modes ...................................................................................................... 312.3 Address Space................................................................................................................... 322.4 Register Configuration...................................................................................................... 33

2.4.1 Overview.............................................................................................................. 332.4.2 General Registers ................................................................................................. 342.4.3 Control Registers ................................................................................................. 352.4.4 Initial CPU Register Values................................................................................. 36

2.5 Data Formats..................................................................................................................... 372.5.1 General Register Data Formats ............................................................................ 372.5.2 Memory Data Formats ......................................................................................... 39

2.6 Instruction Set ................................................................................................................... 402.6.1 Instruction Set Overview ..................................................................................... 402.6.2 Instructions and Addressing Modes ..................................................................... 412.6.3 Tables of Instructions Classified by Function...................................................... 422.6.4 Basic Instruction Formats .................................................................................... 522.6.5 Notes on Use of Bit Manipulation Instructions.................................................... 53

2.7 Addressing Modes and Effective Address Calculation ..................................................... 542.7.1 Addressing Modes ............................................................................................... 54

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2.7.2 Effective Address Calculation ............................................................................. 582.8 Processing States............................................................................................................... 62

2.8.1 Overview.............................................................................................................. 622.8.2 Program Execution State...................................................................................... 622.8.3 Exception-Handling State .................................................................................... 632.8.4 Exception-Handling Sequences ........................................................................... 642.8.5 Bus-Released State............................................................................................... 652.8.6 Reset State............................................................................................................ 662.8.7 Power-Down State ............................................................................................... 66

2.9 Basic Operational Timing ................................................................................................. 672.9.1 Overview.............................................................................................................. 672.9.2 On-Chip Memory Access Timing........................................................................ 672.9.3 On-Chip Supporting Module Access Timing ...................................................... 682.9.4 Access to External Address Space ....................................................................... 69

Section 3 MCU Operating Modes .................................................................................. 713.1 Overview........................................................................................................................... 71

3.1.1 Operating Mode Selection ................................................................................... 713.1.2 Register Configuration......................................................................................... 72

3.2 Mode Control Register (MDCR) ...................................................................................... 723.3 System Control Register (SYSCR) ................................................................................... 733.4 Operating Mode Descriptions ........................................................................................... 75

3.4.1 Mode 1 ................................................................................................................. 753.4.2 Mode 2 ................................................................................................................. 753.4.3 Mode 3 ................................................................................................................. 753.4.4 Mode 4 ................................................................................................................. 763.4.5 Mode 5 ................................................................................................................. 763.4.6 Mode 6 ................................................................................................................. 763.4.7 Mode 7 ................................................................................................................. 76

3.5 Pin Functions in Each Operating Mode ............................................................................ 773.6 Memory Map in Each Operating Mode ............................................................................ 77

Section 4 Exception Handling ......................................................................................... 814.1 Overview........................................................................................................................... 81

4.1.1 Exception Handling Types and Priority............................................................... 814.1.2 Exception Handling Operation............................................................................. 814.1.3 Exception Vector Table ....................................................................................... 82

4.2 Reset.................................................................................................................................. 844.2.1 Overview.............................................................................................................. 844.2.2 Reset Sequence .................................................................................................... 844.2.3 Interrupts after Reset............................................................................................ 87

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4.3 Interrupts ........................................................................................................................... 884.4 Trap Instruction................................................................................................................. 894.5 Stack Status after Exception Handling.............................................................................. 894.6 Notes on Stack Usage ....................................................................................................... 90

Section 5 Interrupt Controller .......................................................................................... 915.1 Overview........................................................................................................................... 91

5.1.1 Features................................................................................................................ 915.1.2 Block Diagram..................................................................................................... 925.1.3 Pin Configuration................................................................................................. 935.1.4 Register Configuration......................................................................................... 93

5.2 Register Descriptions ........................................................................................................ 945.2.1 System Control Register (SYSCR) ...................................................................... 945.2.2 Interrupt Priority Registers A and B (IPRA, IPRB)............................................. 955.2.3 IRQ Status Register (ISR).................................................................................... 1025.2.4 IRQ Enable Register (IER) .................................................................................. 1035.2.5 IRQ Sense Control Register (ISCR) .................................................................... 104

5.3 Interrupt Sources............................................................................................................... 1055.3.1 External Interrupts ............................................................................................... 1055.3.2 Internal Interrupts................................................................................................. 1075.3.3 Interrupt Vector Table.......................................................................................... 107

5.4 Interrupt Operation............................................................................................................ 1115.4.1 Interrupt Handling Process................................................................................... 1115.4.2 Interrupt Sequence ............................................................................................... 1165.4.3 Interrupt Response Time...................................................................................... 117

5.5 Usage Notes ...................................................................................................................... 1185.5.1 Contention between Interrupt and Interrupt-Disabling Instruction ...................... 1185.5.2 Instructions That Inhibit Interrupts ...................................................................... 1195.5.3 Interrupts during EEPMOV Instruction Execution.............................................. 1195.5.4 Usage Notes on External Interrupts ..................................................................... 1195.5.5 Notes on Non-Maskable Interrupts (NMI)........................................................... 121

Section 6 Bus Controller ................................................................................................... 1236.1 Overview........................................................................................................................... 123

6.1.1 Features................................................................................................................ 1236.1.2 Block Diagram..................................................................................................... 1246.1.3 Input/Output Pins ................................................................................................. 1256.1.4 Register Configuration......................................................................................... 126

6.2 Register Descriptions ........................................................................................................ 1266.2.1 Bus Width Control Register (ABWCR)............................................................... 1266.2.2 Access State Control Register (ASTCR) ............................................................. 127

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6.2.3 Wait Control Register (WCR).............................................................................. 1286.2.4 Wait State Controller Enable Register (WCER) .................................................. 1296.2.5 Bus Release Control Register (BRCR) ................................................................ 1306.2.6 Chip Select Control Register (CSCR).................................................................. 132

6.3 Operation .......................................................................................................................... 1336.3.1 Area Division....................................................................................................... 1336.3.2 Chip Select Signals .............................................................................................. 1356.3.3 Data Bus............................................................................................................... 1366.3.4 Bus Control Signal Timing .................................................................................. 1376.3.5 Wait Modes.......................................................................................................... 1456.3.6 Interconnections with Memory (Example) .......................................................... 1516.3.7 Bus Arbiter Operation.......................................................................................... 153

6.4 Usage Notes ...................................................................................................................... 1566.4.1 Connection to Dynamic RAM and Pseudo-Static RAM...................................... 1566.4.2 Register Write Timing ......................................................................................... 1566.4.3 BREQ Input Timing............................................................................................. 1586.4.4 Transition To Software Standby Mode................................................................ 158

Section 7 Refresh Controller ............................................................................................ 1597.1 Overview........................................................................................................................... 159


7.2 Register Descriptions ........................................................................................................ 1637.2.1 Refresh Control Register (RFSHCR)................................................................... 1637.2.2 Refresh Timer Control/Status Register (RTMCSR) ............................................ 1667.2.3 Refresh Timer Counter (RTCNT)........................................................................ 1687.2.4 Refresh Time Constant Register (RTCOR) ......................................................... 168

7.3 Operation .......................................................................................................................... 1697.3.1 Overview.............................................................................................................. 1697.3.2 DRAM Refresh Control ....................................................................................... 1717.3.3 Pseudo-Static RAM Refresh Control ................................................................... 1857.3.4 Interval Timer ...................................................................................................... 190

7.4 Interrupt Source ................................................................................................................ 1967.5 Usage Notes ...................................................................................................................... 196

Section 8 DMA Controller................................................................................................ 1998.1 Overview........................................................................................................................... 199

8.1.1 Features................................................................................................................ 1998.1.2 Block Diagram..................................................................................................... 200

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8.1.3 Functional Overview............................................................................................ 2018.1.4 Input/Output Pins ................................................................................................. 2038.1.5 Register Configuration......................................................................................... 203

8.2 Register Descriptions (Short Address Mode).................................................................... 2058.2.1 Memory Address Registers (MAR) ..................................................................... 2058.2.2 I/O Address Registers (IOAR) ............................................................................. 2068.2.3 Execute Transfer Count Registers (ETCR).......................................................... 2068.2.4 Data Transfer Control Registers (DTCR) ............................................................ 208

8.3 Register Descriptions (Full Address Mode)...................................................................... 2118.3.1 Memory Address Registers (MAR) ..................................................................... 2118.3.2 I/O Address Registers (IOAR) ............................................................................. 2118.3.3 Execute Transfer Count Registers (ETCR).......................................................... 2128.3.4 Data Transfer Control Registers (DTCR) ............................................................ 214

8.4 Operation .......................................................................................................................... 2208.4.1 Overview.............................................................................................................. 2208.4.2 I/O Mode.............................................................................................................. 2228.4.3 Idle Mode............................................................................................................. 2248.4.4 Repeat Mode ........................................................................................................ 2278.4.5 Normal Mode....................................................................................................... 2318.4.6 Block Transfer Mode ........................................................................................... 2348.4.7 DMAC Activation................................................................................................ 2398.4.8 DMAC Bus Cycle ................................................................................................ 2418.4.9 DMAC Multiple-Channel Operation ................................................................... 2478.4.10 External Bus Requests, Refresh Controller, and DMAC ..................................... 2488.4.11 NMI Interrupts and DMAC.................................................................................. 2498.4.12 Aborting a DMA Transfer ................................................................................... 2508.4.13 Exiting Full Address Mode.................................................................................. 2518.4.14 DMAC States in Reset State, Standby Modes, and Sleep Mode ......................... 252

8.5 Interrupts ........................................................................................................................... 2538.6 Usage Notes ...................................................................................................................... 254

8.6.1 Note on Word Data Transfer................................................................................ 2548.6.2 DMAC Self-Access ............................................................................................. 2548.6.3 Longword Access to Memory Address Registers ................................................ 2548.6.4 Note on Full Address Mode Setup....................................................................... 2548.6.5 Note on Activating DMAC by Internal Interrupts ............................................... 2548.6.6 NMI Interrupts and Block Transfer Mode ........................................................... 2568.6.7 Memory and I/O Address Register Values .......................................................... 2568.6.8 Bus Cycle when Transfer Is Aborted ................................................................... 257

Section 9 I/O Ports .............................................................................................................. 2599.1 Overview........................................................................................................................... 259

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9.2 Port 1................................................................................................................................. 2639.2.1 Overview.............................................................................................................. 2639.2.2 Register Descriptions ........................................................................................... 264






9.8 Port 7................................................................................................................................. 2849.8.1 Overview.............................................................................................................. 2849.8.2 Register Description............................................................................................. 285



9.11 Port A................................................................................................................................ 2979.11.1 Overview.............................................................................................................. 2979.11.2 Register Descriptions ........................................................................................... 2999.11.3 Pin Functions ....................................................................................................... 301

9.12 Port B ................................................................................................................................ 3099.12.1 Overview.............................................................................................................. 3099.12.2 Register Descriptions ........................................................................................... 3119.12.3 Pin Functions ....................................................................................................... 313

Section 10 16-Bit Integrated Timer Unit (ITU).......................................................... 31910.1 Overview........................................................................................................................... 319

10.1.1 Features................................................................................................................ 31910.1.2 Block Diagrams ................................................................................................... 32210.1.3 Input/Output Pins ................................................................................................. 327

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10.1.4 Register Configuration......................................................................................... 32810.2 Register Descriptions ........................................................................................................ 331

10.2.1 Timer Start Register (TSTR)................................................................................ 33110.2.2 Timer Synchro Register (TSNC) ......................................................................... 33210.2.3 Timer Mode Register (TMDR) ............................................................................ 33410.2.4 Timer Function Control Register (TFCR)............................................................ 33710.2.5 Timer Output Master Enable Register (TOER) ................................................... 33910.2.6 Timer Output Control Register (TOCR) .............................................................. 34110.2.7 Timer Counters (TCNT) ...................................................................................... 34210.2.8 General Registers A, B (GRA, GRB) .................................................................. 34310.2.9 Buffer Registers A, B (BRA, BRB) ..................................................................... 34410.2.10 Timer Control Registers (TCR) ........................................................................... 34510.2.11 Timer I/O Control Register (TIOR) ..................................................................... 34810.2.12 Timer Status Register (TSR)................................................................................ 35010.2.13 Timer Interrupt Enable Register (TIER) .............................................................. 352

10.3 CPU Interface.................................................................................................................... 35310.3.1 16-Bit Accessible Registers ................................................................................. 35310.3.2 8-Bit Accessible Registers ................................................................................... 356

10.4 Operation .......................................................................................................................... 35710.4.1 Overview.............................................................................................................. 35710.4.2 Basic Functions.................................................................................................... 35910.4.3 Synchronization ................................................................................................... 36710.4.4 PWM Mode.......................................................................................................... 36910.4.5 Reset-Synchronized PWM Mode......................................................................... 37310.4.6 Complementary PWM Mode............................................................................... 37610.4.7 Phase Counting Mode.......................................................................................... 38510.4.8 Buffering.............................................................................................................. 38710.4.9 ITU Output Timing .............................................................................................. 392

10.5 Interrupts ........................................................................................................................... 39510.5.1 Setting of Status Flags ......................................................................................... 39510.5.2 Timing of Clearing of Status Flags ...................................................................... 39810.5.3 Interrupt Sources and DMA Controller Activation.............................................. 398

10.6 Usage Notes ...................................................................................................................... 400

Section 11 Programmable Timing Pattern Controller............................................... 41511.1 Overview........................................................................................................................... 415

11.1.1 Features................................................................................................................ 41511.1.2 Block Diagram..................................................................................................... 41611.1.3 TPC Pins .............................................................................................................. 41711.1.4 Registers............................................................................................................... 418

11.2 Register Descriptions ........................................................................................................ 419

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11.2.1 Port A Data Direction Register (PADDR) ........................................................... 41911.2.2 Port A Data Register (PADR).............................................................................. 41911.2.3 Port B Data Direction Register (PBDDR)............................................................ 42011.2.4 Port B Data Register (PBDR) .............................................................................. 42011.2.5 Next Data Register A (NDRA) ............................................................................ 42111.2.6 Next Data Register B (NDRB)............................................................................. 42311.2.7 Next Data Enable Register A (NDERA).............................................................. 42511.2.8 Next Data Enable Register B (NDERB) .............................................................. 42611.2.9 TPC Output Control Register (TPCR) ................................................................. 42711.2.10 TPC Output Mode Register (TPMR) ................................................................... 429

11.3 Operation .......................................................................................................................... 43111.3.1 Overview.............................................................................................................. 43111.3.2 Output Timing...................................................................................................... 43211.3.3 Normal TPC Output............................................................................................. 43311.3.4 Non-Overlapping TPC Output ............................................................................. 43511.3.5 TPC Output Triggering by Input Capture ............................................................ 437

11.4 Usage Notes ...................................................................................................................... 43811.4.1 Operation of TPC Output Pins ............................................................................. 43811.4.2 Note on Non-Overlapping Output........................................................................ 438

Section 12 Watchdog Timer............................................................................................. 44112.1 Overview........................................................................................................................... 441

12.1.1 Features................................................................................................................ 44112.1.2 Block Diagram..................................................................................................... 44212.1.3 Pin Configuration................................................................................................. 44212.1.4 Register Configuration......................................................................................... 443

12.2 Register Descriptions ........................................................................................................ 44312.2.1 Timer Counter (TCNT)........................................................................................ 44312.2.2 Timer Control/Status Register (TCSR)................................................................ 44412.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 44612.2.4 Notes on Register Rewriting ................................................................................ 447

12.3 Operation .......................................................................................................................... 44912.3.1 Watchdog Timer Operation ................................................................................. 44912.3.2 Interval Timer Operation ..................................................................................... 45012.3.3 Timing of Setting of Overflow Flag (OVF)......................................................... 45012.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) .................................. 451

12.4 Interrupts ........................................................................................................................... 45212.5 Usage Notes ...................................................................................................................... 45212.6 Notes ................................................................................................................................. 453

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Section 13 Serial Communication Interface ................................................................ 45513.1 Overview........................................................................................................................... 455


13.2 Register Descriptions ........................................................................................................ 45913.2.1 Receive Shift Register (RSR) .............................................................................. 45913.2.2 Receive Data Register (RDR) .............................................................................. 45913.2.3 Transmit Shift Register (TSR) ............................................................................. 46013.2.4 Transmit Data Register (TDR)............................................................................. 46013.2.5 Serial Mode Register (SMR)................................................................................ 46113.2.6 Serial Control Register (SCR).............................................................................. 46413.2.7 Serial Status Register (SSR) ................................................................................ 46813.2.8 Bit Rate Register (BRR) ...................................................................................... 472

13.3 Operation .......................................................................................................................... 48113.3.1 Overview.............................................................................................................. 48113.3.2 Operation in Asynchronous Mode ....................................................................... 48313.3.3 Multiprocessor Communication........................................................................... 49213.3.4 Synchronous Operation........................................................................................ 499

13.4 SCI Interrupts.................................................................................................................... 50813.5 Usage Notes ...................................................................................................................... 509

Section 14 Smart Card Interface ..................................................................................... 51514.1 Overview........................................................................................................................... 515


14.2 Register Descriptions ........................................................................................................ 51814.2.1 Smart Card Mode Register (SCMR) .................................................................... 51814.2.2 Serial Status Register (SSR) ................................................................................ 51914.2.3 Serial Mode Register (SMR)................................................................................ 52114.2.4 Serial Control Register (SCR).............................................................................. 522

14.3 Operation .......................................................................................................................... 52314.3.1 Overview.............................................................................................................. 52314.3.2 Pin Connections ................................................................................................... 52314.3.3 Data Format ......................................................................................................... 52414.3.4 Register Settings .................................................................................................. 52614.3.5 Clock.................................................................................................................... 52814.3.6 Transmitting and Receiving Data ........................................................................ 530

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14.4 Usage Notes ...................................................................................................................... 538

Section 15 A/D Converter................................................................................................. 54115.1 Overview........................................................................................................................... 541

15.1.1 Features................................................................................................................ 54115.1.2 Block Diagram..................................................................................................... 54215.1.3 Input Pins ............................................................................................................. 54315.1.4 Register Configuration......................................................................................... 544

15.2 Register Descriptions ........................................................................................................ 54515.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 54515.2.2 A/D Control/Status Register (ADCSR) ............................................................... 54615.2.3 A/D Control Register (ADCR) ............................................................................ 548

15.3 CPU Interface.................................................................................................................... 54915.4 Operation .......................................................................................................................... 550

15.4.1 Single Mode (SCAN = 0) .................................................................................... 55015.4.2 Scan Mode (SCAN = 1)....................................................................................... 55215.4.3 Input Sampling and A/D Conversion Time ......................................................... 55415.4.4 External Trigger Input Timing............................................................................. 555

15.5 Interrupts ........................................................................................................................... 55615.6 Usage Notes ...................................................................................................................... 556

Section 16 D/A Converter................................................................................................. 56116.1 Overview ............................................................................................................................ 561

16.1.1 Features ................................................................................................................. 56116.1.2 Block Diagram..................................................................................................... 56216.1.3 Input/Output Pins ................................................................................................. 56316.1.4 Register Configuration......................................................................................... 563

16.2 Register Descriptions ........................................................................................................ 56416.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1) ................................................. 56416.2.2 D/A Control Register (DACR) ............................................................................ 56416.2.3 D/A Standby Control Register (DASTCR).......................................................... 566

16.3 Operation .......................................................................................................................... 56716.4 D/A Output Control .......................................................................................................... 568

Section 17 RAM .................................................................................................................. 56917.1 Overview........................................................................................................................... 569

17.1.1 Block Diagram..................................................................................................... 57017.1.2 Register Configuration......................................................................................... 570

17.2 System Control Register (SYSCR) ................................................................................... 57117.3 Operation .......................................................................................................................... 572

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Section 18 ROM (H8/3048F-ONE: Single Power Supply,H8/3048B Mask ROM Version)................................................................ 573

18.1 Flash Memory Overview .................................................................................................. 57318.1.1 Notes on H8/3048F-ONE (Single Power Supply) ............................................... 57318.1.2 Mode Pin Settings ................................................................................................ 574

18.2 Flash Memory Features..................................................................................................... 57518.2.1 Block Diagram..................................................................................................... 57618.2.2 Mode Transitions ................................................................................................. 57618.2.3 On-Board Programming Modes........................................................................... 57918.2.4 Flash Memory Emulation in RAM ...................................................................... 58118.2.5 Differences between Boot Mode and User Program Mode ................................. 58218.2.6 Block Configuration ............................................................................................ 583

18.3 Flash Memory Pin Configuration...................................................................................... 58318.4 Flash Memory Register Configuration.............................................................................. 58418.5 Flash Memory Register Descriptions................................................................................ 584

18.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 58418.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 58818.5.3 Erase Block Register (EBR) ................................................................................ 58918.5.4 RAM Control Register (RAMCR) ....................................................................... 590

18.6 Flash Memory On-Board Programming Modes................................................................ 59218.6.1 Boot Mode ........................................................................................................... 59318.6.2 User Program Mode............................................................................................. 598

18.7 Programming/Erasing Flash Memory ............................................................................... 60018.7.1 Program Mode ..................................................................................................... 60218.7.2 Program-Verify Mode.......................................................................................... 60318.7.3 Erase Mode .......................................................................................................... 60718.7.4 Erase-Verify Mode .............................................................................................. 607

18.8 Flash Memory Protection.................................................................................................. 60918.8.1 Hardware Protection ............................................................................................ 60918.8.2 Software Protection.............................................................................................. 61118.8.3 Error Protection.................................................................................................... 61218.8.4 NMI Input Disable Conditions............................................................................. 614

18.9 Flash Memory Emulation in RAM ................................................................................... 61518.10 Flash Memory PROM Mode............................................................................................. 616

18.10.1 Socket Adapters and Memory Map ..................................................................... 61718.10.2 Notes on Use of PROM Mode ............................................................................. 618

18.11 Notes on Flash Memory Programming/Erasing................................................................ 61918.12 Mask ROM (H8/3048B Mask ROM Version) Overviews................................................ 625

18.12.1 Block Diagram..................................................................................................... 62518.13 Notes on Ordering Mask ROM Version Chips ................................................................. 626

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18.14 Notes when Converting the F-ZTAT (Single Power Supply) Application Softwareto the Mask-ROM Versions .............................................................................................. 627

Section 19 Clock Pulse Generator .................................................................................. 62919.1 Overview........................................................................................................................... 629

19.1.1 Block Diagram..................................................................................................... 63019.2 Oscillator Circuit............................................................................................................... 630

19.2.1 Connecting a Crystal Resonator........................................................................... 63019.2.2 External Clock Input ............................................................................................ 633

19.3 Duty Adjustment Circuit ................................................................................................... 63619.4 Prescalers .......................................................................................................................... 63619.5 Frequency Divider ............................................................................................................ 636

19.5.1 Register Configuration......................................................................................... 63719.5.2 Division Control Register (DIVCR) .................................................................... 63719.5.3 Usage Notes ......................................................................................................... 638

Section 20 Power-Down State ......................................................................................... 63920.1 Overview........................................................................................................................... 63920.2 Register Configuration...................................................................................................... 641

20.2.1 System Control Register (SYSCR) ...................................................................... 64120.2.2 Module Standby Control Register (MSTCR)....................................................... 643

20.3 Sleep Mode ....................................................................................................................... 64520.3.1 Transition to Sleep Mode..................................................................................... 64520.3.2 Exit from Sleep Mode.......................................................................................... 645

20.4 Software Standby Mode.................................................................................................... 64520.4.1 Transition to Software Standby Mode ................................................................. 64520.4.2 Exit from Software Standby Mode ...................................................................... 64620.4.3 Selection of Waiting Time for Exit from Software Standby Mode...................... 64620.4.4 Sample Application of Software Standby Mode.................................................. 64820.4.5 Note...................................................................................................................... 648

20.5 Hardware Standby Mode .................................................................................................. 64920.5.1 Transition to Hardware Standby Mode................................................................ 64920.5.2 Exit from Hardware Standby Mode ..................................................................... 64920.5.3 Timing for Hardware Standby Mode ................................................................... 649

20.6 Module Standby Function................................................................................................. 65020.6.1 Module Standby Timing ...................................................................................... 65020.6.2 Read/Write in Module Standby............................................................................ 65020.6.3 Usage Notes ......................................................................................................... 651

20.7 System Clock Output Disabling Function......................................................................... 652

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Section 21 Electrical Characteristics.............................................................................. 65321.1 Electrical Characteristics of H8/3048F-ONE (Single-Power Supply) .............................. 655

21.1.1 Absolute Maximum Ratings ................................................................................ 65521.1.2 DC Characteristics ............................................................................................... 65621.1.3 AC Characteristics ............................................................................................... 66321.1.4 A/D Conversion Characteristics........................................................................... 66921.1.5 D/A Conversion Characteristics........................................................................... 67021.1.6 Flash Memory Characteristics ............................................................................. 671

21.2 Electrical Characteristics of H8/3048B (Mask ROM) ...................................................... 67521.2.1 Absolute Maximum Ratings ................................................................................ 67521.2.2 DC Characteristics ............................................................................................... 67621.2.3 AC Characteristics ............................................................................................... 68221.2.4 A/D Conversion Characteristics........................................................................... 68821.2.5 D/A Conversion Characteristics........................................................................... 689

21.3 Operational Timing........................................................................................................... 69021.3.1 Bus Timing .......................................................................................................... 69021.3.2 Refresh Controller Bus Timing............................................................................ 69421.3.3 Control Signal Timing ......................................................................................... 69921.3.4 Clock Timing ....................................................................................................... 70121.3.5 TPC and I/O Port Timing..................................................................................... 70121.3.6 ITU Timing .......................................................................................................... 70221.3.7 SCI Input/Output Timing..................................................................................... 70321.3.8 DMAC Timing..................................................................................................... 704

Appendix A Instruction Set .............................................................................................. 705A.1 Instruction List .................................................................................................................. 705A.2 Operation Code Map......................................................................................................... 720A.3 Number of States Required for Execution ........................................................................ 723

Appendix B Internal I/O Register ................................................................................... 734B.1 Addresses (For H8/3048F-ONE, H8/3048B Mask ROM Version) .................................. 735B.2 Addresses (For H8/3048F, H8/3048ZTAT, H8/3048 Mask-ROM, H8/3047 Mask-ROM,

H8/3045 Mask-ROM, and H8/3044 Mask-ROM Versions) ............................................. 743B.3 Function ............................................................................................................................ 751

Appendix C I/O Port Block Diagrams........................................................................... 837C.1 Port 1 Block Diagram ....................................................................................................... 837C.2 Port 2 Block Diagram ....................................................................................................... 838C.3 Port 3 Block Diagram ....................................................................................................... 839C.4 Port 4 Block Diagram ....................................................................................................... 840C.5 Port 5 Block Diagram ....................................................................................................... 841

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C.6 Port 6 Block Diagrams...................................................................................................... 842C.7 Port 7 Block Diagrams...................................................................................................... 846C.8 Port 8 Block Diagrams...................................................................................................... 847C.9 Port 9 Block Diagrams...................................................................................................... 850C.10 Port A Block Diagrams ..................................................................................................... 854C.11 Port B Block Diagrams ..................................................................................................... 858

Appendix D Pin States ....................................................................................................... 862D.1 Port States in Each Mode .................................................................................................. 862D.2 Pin States at Reset ............................................................................................................. 865

Appendix E Timing of Transition to and Recovery from HardwareStandby Mode............................................................................................... 868

Appendix F Product Code Lineup.................................................................................. 869

Appendix G Package Dimensions................................................................................... 871

Section 1 Overview

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Section 1 Overview

1.1 Overview

The H8/3048B Group is a series of microcontrollers (MCUs) that integrate system supportingfunctions together with an H8/300H CPU core having an original Renesas Technologyarchitecture. In addition, the H8/3048F-ONE is equipped with an on-chip emulator (E10T)*2.

The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and aconcise, optimized instruction set designed for speed. It can address a 16-Mbyte linear addressspace. Its instruction set is upward-compatible at the object-code level with the H8/300 CPU,enabling easy porting of software from the H8/300 Series.

The on-chip system supporting functions include ROM, RAM, a 16-bit integrated timer unit(ITU), a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serialcommunication interface (SCI), an A/D converter, a D/A converter, I/O ports, a direct memoryaccess controller (DMAC), a refresh controller, and other facilities.

The H8/3048B Group has 128 kbytes of on-chip ROM and 4 kbytes of on-chip RAM.

Seven MCU operating modes offer a choice of data bus width and address space size. The modes(modes 1 to 7) include one single-chip mode and six expanded modes.

In addition to mask ROM products, the H8/3048B Group includes F-ZTAT™*1 version productswith on-chip user-programmable flash memory. It enables users to respond quickly and flexibly tochanging application specifications as well as to conditions when ramping up from initial to fullvolume production. The on-chip emulator (E10T)*2 is capable of direct emulation of themicrocontroller when mounted in the user’s system, thereby making possible on-board programdebugging.

Table 1.1 summarizes the features of the H8/3048B Group.

Notes: 1. F-ZTAT (Flexible ZTAT ) is a trademark of Renesas Technology Corp.2. An on-chip emulator (E10T) is not provided in the mask ROM version.

Section 1 Overview

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Table 1.1 Features

Feature Description

CPU Upward-compatible with the H8/300 CPU at the object-code level

• General-register machine Sixteen 16-bit general registers

(also usable as sixteen 8-bit registers + eight 16-bit registers or eight 32-bit registers)

• High-speed operation (flash memory version) Maximum clock rate: 25 MHz Add/subtract: 80 ns Multiply/divide: 560 ns 16-Mbyte address space

• Instruction features 8/16/32-bit data transfer, arithmetic, and logic instructions Signed and unsigned multiply instructions (8 bits × 8 bits, 16 bits × 16

bits)

Signed and unsigned divide instructions (16 bits ÷ 8 bits, 32 bits ÷ 16bits)

Bit accumulator function Bit manipulation instructions with register-indirect specification of bit

positions

Memory • ROM: 128 kbytes• RAM: 4 kbytes

Interruptcontroller

• Seven external interrupt pins: NMI, IRQ0 to IRQ5• 30 internal interrupts• Three selectable interrupt priority levels

B

H8/3048B Group Hardware Manual - RS Components · Revision Date: Sep 27, 2006 8 H8/3048B Group...

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