Group M1 - Enigma Group M1 - Enigma MachineMachine

Design Manager: Prateek GoenkaDesign Manager: Prateek Goenka

Adithya Attawar (M1-1)Adithya Attawar (M1-1)

Shilpi Chakrabarti (M1-2)Shilpi Chakrabarti (M1-2)

Zavo Gabriel (M1-3)Zavo Gabriel (M1-3)

Mike Sokolsky (M1-4)Mike Sokolsky (M1-4)

Milestone #4 - 2/6/06Gate Level Design

Status UpdateStatus Update Completed:Completed:

• Design ChosenDesign Chosen• Initial ArchitectureInitial Architecture• Behavioral Verilog and C SimulationBehavioral Verilog and C Simulation• Floorplan, Size Estimation, Transistor CountFloorplan, Size Estimation, Transistor Count• Gate-Level Verilog DesignGate-Level Verilog Design• Behavioral Verilog of new moduleBehavioral Verilog of new module

In ProgressIn Progress• Schematic Verilog Design Schematic Verilog Design • Gate level Verilog for new moduleGate level Verilog for new module

To Do:To Do:• LayoutLayout• DRC/LVSDRC/LVS• TestingTesting

Design DecisionsDesign Decisions

Wheel logic modifiedWheel logic modified• 2 sets of ROM for each wheel2 sets of ROM for each wheel

Implementation of new moduleImplementation of new module• Modernizing the Enigma MachineModernizing the Enigma Machine• Add an asymmetric key encryption to Add an asymmetric key encryption to

transmit the wheel positions and Stecker transmit the wheel positions and Stecker Board positionsBoard positions

• Using Prime numbers that will be calculated Using Prime numbers that will be calculated off chipoff chip

Asymmetric Key EncryptionAsymmetric Key Encryption

The Encryption is based on a public-The Encryption is based on a public-private key combinationprivate key combination• Public Key pair (e,N)Public Key pair (e,N)• Private Key pair (d,N)Private Key pair (d,N)• N is a large number that is a product of 2 primesN is a large number that is a product of 2 primes• Code = message^d mod(N)Code = message^d mod(N)• Message = Code^e mod(N)Message = Code^e mod(N)

Behavioral VerilogBehavioral Verilogmodule rsa(ciphertxt, plaintxt, exponent, modulus, clk);module rsa(ciphertxt, plaintxt, exponent, modulus, clk);

output [15:0] ciphertxt;output [15:0] ciphertxt; input [4:0] plaintxt; input [4:0] plaintxt; input [11:0] exponent; input [11:0] exponent; input [11:0] modulus; input [11:0] modulus; input clk; input clk; reg [4:0] plainreg; reg [4:0] plainreg; reg [16:0] datareg; reg [16:0] datareg; reg [11:0] outreg; reg [11:0] outreg; integer i; integer i; assign ciphertxt = outreg; assign ciphertxt = outreg; initial i = 0; initial i = 0; always@(posedge clk) begin always@(posedge clk) begin if( i == 0 ) begin if( i == 0 ) begin plainreg = plaintxt; plainreg = plaintxt; datareg = plainreg; datareg = plainreg; i = i+1; i = i+1; end end else if( i < exponent ) begin else if( i < exponent ) begin datareg = (datareg * plainreg) % modulus; datareg = (datareg * plainreg) % modulus; i = i+1; i = i+1; end end else begin else begin outreg = datareg; outreg = datareg; i = 0; i = 0; end end end end

endmoduleendmodule

Clocking IssuesClocking Issues Design requires complex control Design requires complex control

over clock signals to different over clock signals to different modules.modules.• Different modules need different clocksDifferent modules need different clocks• Also depends on state, for instance:Also depends on state, for instance:

Wheel module, during Set phase, is clocked Wheel module, during Set phase, is clocked at the global clock rate, however during at the global clock rate, however during character operations it is clocked only once character operations it is clocked only once per encode cycle.per encode cycle.

• FSM includes clock modulators for FSM includes clock modulators for various components that run at different various components that run at different speeds.speeds.

Updated Transistor CountUpdated Transistor Count

Transistor Count:Transistor Count:• Muxes = 550Muxes = 550• RAM = 1150RAM = 1150• ROM = 4700ROM = 4700• Adders/Dividers = 450Adders/Dividers = 450• Registers = 800Registers = 800• Counters = 1250Counters = 1250• FSM = 300FSM = 300

Total: 9200Total: 9200

Block Sizes (estimates)Block Sizes (estimates)

Adder % 26: Adder % 26: 3500 um^23500 um^2 RAM: RAM: 10000 um^210000 um^2 ROM:ROM: 30000 um^230000 um^2 CountersCounters :: 6000 um^26000 um^2 Control/FSM:Control/FSM: 3000 um^23000 um^2 Registers:Registers: 2500 um^22500 um^2

Total: 55,000 um^2Total: 55,000 um^2

Floor PlanFloor Plan

Counter&

WheelReg.

FSM & Data Reg.

RAM

5-bitAdder

+5-bit%26

ROM

Metal LayersMetal Layers Standard Usage:Standard Usage:

• Metal 1Metal 1 Gate connections, V++, GndGate connections, V++, Gnd

• Metal 2Metal 2 Inter-gate connections, local routingInter-gate connections, local routing

• Metal 3Metal 3 Global routing, horizontalGlobal routing, horizontal

• Metal 4Metal 4

Main Verilog ModuleMain Verilog Module// Main module// Main module

module enigma (charout, charin, usestek, stekset, numwheels, wheelord, wheelpos, reset, set, clk);module enigma (charout, charin, usestek, stekset, numwheels, wheelord, wheelpos, reset, set, clk);

output [4:0] charout;output [4:0] charout;

input [4:0] charin,input [4:0] charin,

input [4:0] stekset, wheelset;input [4:0] stekset, wheelset;

input [2:0] wheelord;input [2:0] wheelord;

input usestek, reset, set, clk;input usestek, reset, set, clk;

wire [4:0] mux0out, mux1out, mux2out, mux3out, mux4out, mux5out, cregout, nregout;wire [4:0] mux0out, mux1out, mux2out, mux3out, mux4out, mux5out, cregout, nregout;

wire [4:0] add0out, add1out, ram0out, rom0out, rom1out, wheelpos;wire [4:0] add0out, add1out, ram0out, rom0out, rom1out, wheelpos;

wire [2:0] wheel;wire [2:0] wheel;

register5b creg( cregout, mux0out, clk);register5b creg( cregout, mux0out, clk);

register5b nreg( nregout, mux1out, clk);register5b nreg( nregout, mux1out, clk);

register5b oreg( charout, mux2out, clk);register5b oreg( charout, mux2out, clk);

adder5bmod26 add0( add0out, nregout, cregout);adder5bmod26 add0( add0out, nregout, cregout);

adder5bmod26 add1( add1out, 5'b01101, add0out);adder5bmod26 add1( add1out, 5'b01101, add0out);

countunit wheels( curwheel, curwheelpos, wheelset, wheelnum, wheelpos, wheelord, reset, set, clk);countunit wheels( curwheel, curwheelpos, wheelset, wheelnum, wheelpos, wheelord, reset, set, clk);

fsm fsm0( mux0sel, mux1sel, mux2sel, mux3sel, mux4sel, loadcnt, ramrw, ramclk, reset, set,clk);fsm fsm0( mux0sel, mux1sel, mux2sel, mux3sel, mux4sel, loadcnt, ramrw, ramclk, reset, set,clk);

rom234x5b rom0( rom0out, {curwheel, mux3out});rom234x5b rom0( rom0out, {curwheel, mux3out});

rom26x5b rom1( rom1out, cregout);rom26x5b rom1( rom1out, cregout);

ram26x5b ram0( ram0out, ramrw, mux4out, stekset, ramclk);ram26x5b ram0( ram0out, ramrw, mux4out, stekset, ramclk);

mux5bx2 mux0( mux0out, mux0sel, charin, mux2out);mux5bx2 mux0( mux0out, mux0sel, charin, mux2out);

mux5bx2 mux1( mux1out, mux1sel, rom0out, curwheelpos);mux5bx2 mux1( mux1out, mux1sel, rom0out, curwheelpos);

mux5bx4 mux2( mux2out, mux2sel, ram1out, rom1out, cregout, add0out);mux5bx4 mux2( mux2out, mux2sel, ram1out, rom1out, cregout, add0out);

mux5bx2 mux3( mux3out, mux3sel, add0out, add1out);mux5bx2 mux3( mux3out, mux3sel, add0out, add1out);

mux5bx2 mux4( mux4out, mux4sel, cregout, loadcnt);mux5bx2 mux4( mux4out, mux4sel, cregout, loadcnt);

endmoduleendmodule

Obviously this is too small!!!Obviously this is too small!!!

Problems & QuestionsProblems & Questions Design is too smallDesign is too small

• Planning Additional ModulesPlanning Additional Modules ““Random” wheel motion based on state of Random” wheel motion based on state of

machinemachine Changing steckerboard parings.Changing steckerboard parings. Grouping characters (block cypher)Grouping characters (block cypher) Have the previous character(s) influence Have the previous character(s) influence

encoding/decoding ***encoding/decoding *** Public/Private Key Generation (Unmatched Public/Private Key Generation (Unmatched

encryption/decryption) ******encryption/decryption) ******

• Increase data-path(8,12,16-bit Increase data-path(8,12,16-bit operations?)operations?)