Greg Alkire/Brian Smith 197 MAPLD 20051 An Ultra Low Power Reconfigurable Task Processor for Space...

Greg Alkire/Brian Smith 197 MAPLD 20051

An Ultra Low Power Reconfigurable Task Processor

for Space

Brian Smith, Greg Alkire – PicoDyne Inc.Wes Powell – NASA GSFC


Outline

• Project Overview• Goals• Architecture• Implementation Approach• Conclusion


Project Overview

• Phase II SBIR for Nano-Sat Computing• Proposed joining our existing FPGA work

with a microcontroller on a single chip in Radiation Tolerant CMOS.

• During Phase I, decided that Cool-RAD™ and a full 32-bit processor would result in a more versatile chip.


Project Goals

• Combine RAM- configurable logic array with a common processor and standard I/O


Project Goals

• FPGA of Suitable size for simple filters, state machines, and I/O protocol logic functions

48x48 Cell Logic Array


Project Goals

• Processor powerful enough for primary processor on NanoSat missions

32-bit SPARC Leon2


Project Goals

• Radiation Tolerant and Low Power.

• PicoDyne’s Cool-RAD™ process operates at 0.5V Core Voltage for low power, is very total dose hard, and uses Radiation Tolerant circuit design for low SEUs


Implementation

• 0.35um Cool-RAD™• SEU tolerance

achieved by using Single Event Resistant Topology (SERT) cell, developed by UNM/CAMBR and through adequate spacing of critical nodes


Implementation

• Cool-RAD™• Low Power by using

Ultra Low Power CMOS process developed under CULPRiT program

• Total Dose Tolerance of this process

> 200 krad (Si)


Processor

• Leon 2 version of SPARC V8 architecture with 5-stage pipeline.

• Synthesized using STD Cell Library and standard tools.

• Laid out for minimal delay to FPGA core & I/O


Processor

• Features:– 2 UARTS, interrupt driven– 16 bit programmable I/O– Interrupt Controller– 3 Timers (1 watchdog)– 8/16/32 bit memory controller– I-Cache – D-Cache


FPGA

• Basic logic block is a mux-based universal logic block

• Implements 50 functions.


FPGA

• Input and output multiplexers route signal in and out of the logic section.

• Each mux, for logic and routing, has it’s own configuration register


FPGA

• Fine-grain architecture• Each configuration register is accessible in

memory map• The function of each logic and routing cell

is configurable on-the-fly


FPGA• Hierarchical architecture• First we developed individual logic cells• Then built configuration logic• Began placing adjacent cells and designing

interconnect• Array is made up of some number of 16x16 cells


FPGA

• Created 4x4 blocks of cells

• Then 16x16• Configuration

and routing take up very large percentage of die area


RTP

• FPGA placed on memory bus of LEON

• I/O to die pads• FPGA configured

through memory writes by processor software


RTP

• Development of user logic for array begins with HDL synthesis using std tools.

• Layout done with custom tool-set


RTP

• Example designs include Filter implementation

• (4-pole CIC)• Synthesized,

placed, routed, and simulated


Potential Uses

• Central Processor for nanosats• Data processor for miniaturized

instruments• Embedded processor for subsystems • I/O, instrument interface, comm protocol


Verification

• FPGA verification performed via extraction and conversion to verilog netlist for simulation against original RTL testbench

• Memory Cell verification two-fold basic functional via extraction and SPICE simulation

• SPARC verification via IP test suites and focused implementation simulation.

• RTP verification at interface level


Conclusion

• RTP will enable compression of board space for a computational node used in nanosats or as embedded or peripheral processor in larger spacecraft

• Ultra Low Power implementation means less thermal noise to instruments, can be embedded closer to sensors

Greg Alkire/Brian Smith 197 MAPLD 20051 An Ultra Low Power Reconfigurable Task Processor for Space...

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