GreenPAK

8/6/2019 GreenPAK

1/65

Silego Technology, Inc. Rev 1.07

000-0046200-107 Revised May 2, 2011

Production

GreenPAK TMProgrammable Mixed Signal Array

SLG46200

Block Diagram

Features Logic & Mixed Signal Circuits

Highly Versatile Macro Cells

3.3V Supply

Operating Temperature Range: -40C to 85C

RoHS Compliant / Halogen-Free

Pb-Free TDFN-8 2mm x 2mm Package

Applications

Personal Computers and Servers

PC Peripherals

Consumer Electronics

Data Communications Equipment

Handheld and Portable Electronics

Pin Configuration

GNDI/O_PSOI/O_PSI

I/O_PCLK

I/OI/O_RST

23

4 5

67

8

IN_VPP

VDD 1

Thermal Padconnected to GND

TDFN-8(Top View)

PIN1VDD

PIN2Input

PIN3I/O

PIN4I/O

PIN7I/O

PIN8I/O

Non-VolatileMemory

POR

VREF

RC OSC

S2P PIN6I/O

PIN5GND

ACMP1

ACMP0PWM

ADC

Look-Up Tables

2-bitLUT0

2-bitLUT1

3-bitLUT0

3-bitLUT1

3-bitLUT2

3-bitLUT3

4-bitLUT0

DigitalComparator

DCMP0

DCMP1

Counter/DelayGenerators

CNT/DLY0

CNT/DLY1

CNT/DLY2

D Flip-Flops/Latches

DFF0

DFF1

DFF2

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SLG46200Table of Contents

1.0 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2.0 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.1 Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22.2 Programming Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

3.0 User Programmability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

4.0 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45.0 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

5.1 Absolute Maximum Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

5.2 Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55.3 Logic Cell Current Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

5.4 Input Pin Current Measuremnts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76.0 Summary of Macro Cell Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

6.1 I/O Pins (6 total) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86.2 Delays/Counters (3 total) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86.3 Analog to Digital Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86.4 Analog Comparators (2 total) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

6.5 Pulse Width Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86.6 Digital Comparators (2 total). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86.7 Serial-to-Parallel / Parallel-to-Serial Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

6.8 Combinatorial Logic LUTs (7 total) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86.9 Logic Storage Devices (3 total). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

7.0 I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

7.1 Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97.2 Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

7.2.1 Open Drain Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107.2.2 Push Pull with Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107.2.3 Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

7.3 Pull Up/Down Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

7.4 I/O Pins Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117.4.1 PIN 2 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117.4.2 PIN 3 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117.4.3 PIN 4 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127.4.4 PIN 6 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127.4.5 PIN 7 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137.4.6 PIN 8 Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

8.0 Digital Comparator (DCMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148.1 DCMP Input Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

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SLG462008.2 DCMP Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148.3 DCMP0 Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148.4 DCMP1 Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

8.5 DCMP0 & DCMP1 Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159.0 Pulse Width Modulator (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

9.1 PWM Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169.2 PWM Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

9.3 PWM Functional Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169.4 PWM Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

9.5 PWM Dead Band Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179.6 PWM Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

10.0 Serial to Parallel / Parallel to Serial Converter (S2P) . . . . . . . . . . . . . . . . . . . . . . 19

10.1 S2P Functional Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1910.2 Serial to Parallel Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1910.3 Serial to Parallel Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2010.4 Parallel to Serial Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2010.5 Parallel to Serial Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

10.6 S2P Notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2010.7 S2P Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

11.0 Analog to Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2211.1 ADC Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

11.2 ADC Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2311.3 ADC 3-bit Programmable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2311.4 ADC 2-Channel Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

11.5 ADC Input Voltage Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2311.6 ADC Reference Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2411.7 ADC Power Down Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

11.8 ADC Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2411.9 ADC Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2511.10 ADC Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

12.0 Analog Comparator (ACMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

12.1 ACMP0 Input Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2712.2 ACMP0 Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2712.3 ACMP1 Input Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2712.4 ACMP1 Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

12.5 ACMP Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2812.6 ACMP 1mA Input Current Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

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SLG4620012.7 ACMP Low Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2812.8 ACMP 50mV Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2912.9 ACMP0 & ACMP1 Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

12.9.1 ACMP0 Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2912.9.2 ACMP1 Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

13.0 Voltage Reference Out (V REF Out). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3113.1 VREF Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3113.2 VREF Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

13.3 VREF Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3113.4 VREF Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

14.0 Power On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

15.0 RC Oscillator (RCO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3415.1 RC Oscillator Functional Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3415.2 RCO Frequency Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

15.3 RCO Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3515.4 RCO Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

16.0 Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3616.1 Counter Functional Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

16.2 Counter Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3616.3 Counter2 as a Finite State Machine (FSM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3716.4 FSM (Counter2) Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3716.5 Counter Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

17.0 Delay Cells (DLY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

17.1 Delay Cells Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4017.2 Delay Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4017.3 4Delay Cells Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

18.0 Combinatorial Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4218.1 2-Bit LUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4218.2 3-Bit LUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

18.3 4-Bit LUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4519.0 Digital Storage Elements (DFFs/Latches) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

19.1 DFF/Latch Functional Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

19.2 DFF/Latch Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4619.3 DFF/Latch Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

20.0 Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4720.1 System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

20.2 Combinatorial Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

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SLG4620020.3 Time Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

21.0 Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4821.1 Software & Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

21.1.1 GreenPAK Designer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4821.1.2 GreenPAK Programmer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4821.1.3 Minimum System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

21.2 Development Kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4821.3 Project Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

22.0 Package Top Marking System Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4923.0 Package Drawing and Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

23.1 8 Lead TDFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5024.0 Tape and Reel Drawing and Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

24.1 Tape and Reel Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5124.2 Tape and Reel Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

25.0 Appendix - SLG46200 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5226.0 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

27.0 Silego Website & Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6027.1 Silego Technology Website . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6027.2 Silego Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

27.2.1 Online Live Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6027.2.2 Contact Your Local Sales Representative . . . . . . . . . . . . . . . . . . . . . . . . . . 60

27.2.3 Contact Silego Directly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6027.3 Other Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

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SLG462001.0 Overview

The SLG46200 provides a small, low power component for commonly used mixed-signal functions. The user creates their circuitdesign by programming the one time Non-Volatile Memory (NVM) to configure interconnect logic, I/O Pins and macro cells of theSLG46200. This highly versatile device allows a wide variety of mixed-signal functions to be designed within a very small, lowpower single integrated circuit. The macro cells in the device include the following:

Pulse Width Modulator (PWM) 8-Bit Successive Approximation Analog to Digital Converter (SAR ADC) Serial to Parallel Converter (S2P) Power-On Reset Device (POR) Voltage Reference (V REF ) RC Oscillator (RC OSC) 3 Counter/Delay Generators (CNT/DLY) 3 D Flip-Flop/Latches (DFF) 2 Digital Comparators (DCMP) 2 Analog Comparators (ACMP) 7 Combinatorial Lookup Tables (LUT) Configurable I/O Pins (Open Drain, Push-Pull, Schmitt Trigger Input, Low Voltage Digital Input and Analog I/O)

The specific functions that can be designed using the SLG46200 include:

Power-On-Reset Generators Signal Delay Elements One-Shot Detection Voltage Level Detectors Voltage Level-Shift Circuits Signal De-Glitches

The PWM and ADC macro cells also support more complex control circuits such fan speed controllers, stepper motor controllersand interface to a wide variety of sensor devices. Traditionally these devices were designed from combinations of low complexitylogic and discrete devices requiring costly board space while having complex testing strategies. Silegos SLG46200 allows thefunctionality of these circuits to be fully tested before being mounted onto a PCB greatly simplifying the system design andtesting procedures.

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SLG462002.0 Pin Description

2.1 Functional Pin Description

2.2 Programming Pin Description

Pin # Pin Name Function1 VDD 3.3V Supply

2 IN_VPP I

3 I/O_RST I/O

4 I/O I/O

5 GND GND

6 I/O_PSO I/O

7 I/O_PSI I/O

8 I/O_PCLK I/O

ExposedBottom Pad GND GND

Pin # Pin Name Programming Description

1 VDD 3.3V Power

2 IN_VPP Program Power Voltage

3 I/O_RST Program Reset

4 I/O N/A

5 GND GND

6 I/O_PSO Program Serial Data Out

7 I/O_PSI Program Serial Data In

8 I/O_PCLK Program Clock In

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SLG462003.0 User Programmability

The SLG46200 is a user programmable device with One-Time-Programmable (OTP) memory elements that are able to constructcombinatorial logic elements. Three of the I/O Pins provide a connection for the bit patterns into the OTP on board memory. Aprogramming development kit allows the user the ability to create initial devices. Once the design is finalized, the hex pattern isforwarded to Silego to integrate into a production process.

Figure 1. Steps to create a custom Silego GreenPAK device

ProductDefinition

Customer Creates their own design inGreenPAK Designer

Program Engineering Samples withGreenPAK Programmer

Customer verifies GreenPAKin system design

E-mail HEX pattern [email protected]

E-mail Product Idea, Definition, Drawing, or Schematic to [email protected]

Silego Applications Engineers will review designspecifications with customer

Samples and Design & CharacterizationReport sent to customer

Customer verifies GreenPAK design

Custom GreenPAK partenters production

GreenPAK Designapproved in system test

GreenPAK Design

approved

GreenPAK Design

approved

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SLG462004.0 Ordering Information

Part Number Type

SLG46200V TDFN-8

SLG46200VTR TDFN-8 - Tape and Reel (3k units)

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SLG462005.0 Electrical Specifications

5.1 Absolute Maximum Conditions

5.2 Electrical Characteristics

Parameter Min. Max. UnitVHIGH to GND -0.3 4.6 V

Voltage at Input Pin -0.3 4.6 V

Current at Input Pin -1.0 1.0 mA

Storage Temperature Range -65 150 C

Junction Temperature -- 150 C

ESD Human Body Model -- 2000 V

ESD Machine Model -- 200 V

Symbol Parameter Condition/Note Min. Typ. Max. Unit

VDD Supply Voltage 3.0 3.3 3.6 V

TA Operating TemperatureGuaranteed by design andcharacterization, not 100%tested in production for cus-tomer specific design.

-40 25 85 C

VO Output Voltage1.0 -- 3.3 V

Voltage range applied to anyoutput in the high-impedance 0 -- VDD V

VPP Programming VoltageChip programming -- 6.5 -- V

Chip reading -- 5.0 -- V

VAIR Analog Input Voltage Range 0 -- 2.2 V

VIH HIGH-Level Input Voltage Logic Input 2.0 -- -- VVIL LOW-Level Input Voltage Logic Input -0.3 -- 0.8 V

VIHYS Input HysteresisDigital Input with BufferedSchmitt Trigger -- 50 -- mV

IIHHIGH-Level Input LeakageCurrent Logic Input Pins; V IN=3.3V -100 -- 100 nA

IILLOW-Level Input LeakageCurrent Logic Input Pins; V IN=0V -100 -- 100 nA

VOH HIGH-Level Output VoltageCMOS Push-Pull, Logic LevelOutputs 2.4 -- 3.3 V

VOL LOW-Level Output VoltageCMOS Push-Pull, Open DrainLogic Level Outputs 0 -- 0.4 V

IOH HIGH-Level Output CurrentPush-Pull Double Current -- 16 -- mAPush Pull -- 8 -- mA

IOL LOW-Level Output Current

1X Open Drain -- 20 -- mA

2X Open Drain -- 40 -- mA

Push-Pull Double Current -- -16 -- mA

Push Pull -- -8 -- mA

TSU Startup Time -- 7 -- ms

TPD Propagation DelaySingle LUT Cellfrom Output Pin to Input Pin -- 25 -- ns

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SLG462005.3 Logic Cell Current Measurements

VDD = 3.3V, T A = 25C (unless otherwise stated)


IVREF VREF Current

VREF -- 15.0 --

A

VREF + 2 Comp -- 32.0 --

VREF + ADC_Single(0V) -- 48.0 --

VREF + ADC_Single(1.75V) -- 75.0 --

VREF + ADC_Single(0V) +Osc(10MHz) -- 230.0 --

VREF + ADC_diff(1V) +Osc(10MHz) -- 250.0 --

VREF + ADC_Single(1.75V) +Osc(10MHz) -- 370.0 --

IPWM PWM [email protected] -- 13.6 --

[email protected] -- 15.9 --

@3.6V -- 18.0 --

IREG Regulator Current

@3.0V -- 0.65 --

[email protected] -- 0.75 --

@3.6V -- 0.8 --

IOSC RC Oscillator Current

@43kHz -- 4.0 --

A

@ 43kHz + V REF -- 19.0 --

@ 85kHz -- 6.0 --

@ 85kHz + V REF -- 21.0 --

@ 128kHz -- 7.5 --@ 128kHz + V REF -- 22.5 --

@ 160kHz -- 9.5 --

@ 160KHz + V REF -- 24.5 --

@ 240kHz -- 12.0 --

@ 240kHz + V REF -- 27.0 --

@ 384kHz -- 15.5 --

@ 384kHz + V REF -- 30.5 --

@ 440kHz -- 20.0 --

@ 440kHz + V REF -- 35.0 --

@ 625kHz -- 24.0 --

@ 625kHz + V REF -- 39.0 --

@ 800kHz -- 45.0 --

@ 800kHz + V REF -- 60.0 --

@ 870kHz -- 36.0 --

@ 870kHz + V REF -- 51.0 --

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SLG46200

5.4 Input Pin Current Measurements

VDD = 3.3V, T A = 25C (unless otherwise stated)

IOSC RC Oscillator Current

@ 950kHz -- 36.0 --

A

@ 950kHz + V REF -- 51.0 --

@ 1290kHz -- 53.0 --

@ 1290kHz + V REF -- 68.0 --

@ 1750kHz -- 73.0 --

@ 1750kHz + V REF -- 88.0 --

@ 2100kHz -- 71.5 --

@ 2100kHz + V REF -- 86.5 --

@ 4800kHz -- 120.5 --

@ 4800kHz + V REF -- 135.5 --

@ 7812kHz -- 181.0 --

@ 7812kHz + V REF -- 196.0 --


IINPUT Digital Input

Digital Input (1MHz) w/outSchmitt Trigger -- 5.5 --

ADigital Input (1MHz) w/outSchmitt Trigger -- 4.0 --

IINPUT

Low Voltage Digital Input Digital Input (1MHz) @ 0.9V -- 7.5 --

ADigital Input (1MHz) @ 1.2V -- 6.5 --

Digital Input (1MHz) @ 1.5V -- 6.5 --Digital Input (1MHz) @ 1.8V -- 6.5 --

IINPUT

Low Voltage Digital Input Digital Input (100KHz) @ 0.9V -- 1.0 --

ADigital Input (100KHz) @ 1.2V -- 0.8 --

Digital Input (100KHz) @ 1.5V -- 0.7 --

Digital Input (100KHz) @ 1.8V -- 0.7 --

IINPUTLow Voltage Digital Input Digital Input (No CLK) @ 0.0V --

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SLG462006.0 Summary of Macro Cell Function

6.1 I/O Pins (6 total)

Digital Input (low voltage or normal voltage, with or without Schmitt Trigger) Open Drain Push-Pull Analog I/O 50k /100k /300k pull-up/pull-down Resistors

6.2 Delays/Counters (3 total)

0.5 s to 380ms (4.5s for Delay1) delay time range Three 14-bit counters (one Finite State Machine counter)

6.3 Analog to Digital Converter

8-bit, 10kHz, Successive Approximation Register ADC

DNL < 1LSB, INL < 2LSB VIN Range: 0 ~ 1.7V Common Mode Voltage Range: V PP /2 ~ V DD /2 3-bit Programmable Gain Amplifier with gain values of (1, 2, 4, 8,16X in differential mode and 0.5, 1, 2, 4, 8X in single-ended

mode) SPI Output Format

6.4 Analog Comparators (2 total)

50mV Hysteresis

6.5 Pulse Width Modulator

8-bit

Clock Frequency 10MHz, with dead band control

6.6 Digital Comparators (2 total)

8-bit Clock Frequency 10MHz

6.7 Serial-to-Parallel / Parallel-to-Serial Converter

Serial-to-Parallel Parallel-to-Serial SPI Format

6.8 Combinatorial Logic LUTs (7 total)

Used to create either standard or custom digital logic cells Two 2-bit Lookup Tables Four 3-bit Lookup Tables One 4-bit Lookup Tables

6.9 Logic Storage Devices (3 total)

D Flip-Flops or Latches

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SLG462007.0 I/O Pins

The SLG46200 has a total of six multi-function I/O Pins which can function as either a user defined Input or Output as well asserve as a programmable function for the one time Non-Volatile Memory to configure interconnect logic.

Normal Mode Pin Definition is as follows:

PIN 2: (input pin only) used for ADC Channel Select PIN 3: Serial Data transfer for either SPI (input & output) or ADC (output) PIN 4: Analog Comparator 0 input, SPI clock input or ADC external clock PIN 6: ADC IN+ PIN 7: ADC IN- or Analog Comparator 1 input PIN 8: ADC & ACMP V REF input & output or V REF output

For the one time programming of a SLG46200 the following pin connections are used:

PIN 2: Voltage for Programming Power PIN 3: Program Reset PIN 6: Program Serial Data Output PIN 7: Program Serial Data Input PIN 8: Program Clock Input

Of the six user defined I/O Pins in the SLG46200, five pins (PINs 3, 4, 6, 7 and 8) can be used for either input or output and onepin (PIN 2) is defined as input only.

7.1 Input Modes

Each input pin can be configured as a Digital Input with/without Buffered Schmitt Trigger, Low Voltage Digital In, or Analog In to

control the user signals that are inputted into the SLG46200. All digital input pins will either have a logic 1 or 0 value inputtedinto the SLG46200, based on the configuration of the input pin which is defined by the user.

Figure 2. I/O Pads Layout

PAD(PIN 2)

PAD(PINS 3, 4, 6, 7, 8)

pad padPIN 2 PIN 3, 4, 6, 7, 8

out out

Digital data toSLG46200

Digital data toSLG46200

in

oe

Digital data fromSLG46200

Push-Pull OutputEnable from matrix

(For PIN 6, OE iscontrolled from reg

instead of frommatrix)

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SLG462007.2 Output Modes

PINs 3, 4, 6, 7 and 8 can be configured as either an open drain output or push-pull output (with Output Enable). Additionally PIN8 can be also be configured as an analog output in the SLG46200 device.

The OE functionality for each of the output pins is controlled by the connection matrix except for PIN 6, which is controlled byreg.

7.2.1 Open Drain Output

The Open Drain Output setting has a 1X current ratio. The open drain output signal from the SLG46200 design will decide theports output state (Hi-Z or ground).

If the signal = 1 , output will be Hi-Z (high impedance)

If the signal = 0 , output will be connected to ground

PINs 4 and 8 have a 2X current sinking option and the current of the output pin will be 40mA.

7.2.2 Push Pull with Output Enable

The Push Pull with Output Enable setting has either a 1X or 2x current ratio and the Output Enable signal will make the output Hi-Z

PIN 4 and PIN 8 have an open drain 2X current sinking option that produces a 16mA current, all other pins only have a 1X currentsinking option that produces an 8mA current.

7.2.3 Analog Output

Analog output functionality is on available on PIN 8 and is configured via the V REF cell

Analog Output = internal signal value

7.3 Pull Up/Down Resistors

All 6 I/O Pins have the option of a 50k/100k/300k pull up/down resistor. Resistors can be used with any of the input or output pinconfigurations previously defined.

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SLG462007.4 I/O Pins Register Settings

7.4.1 PIN 2 Register Settings


Table 1. PIN 2 Register Settings

Signal NameRegister BitAddress Register Definition

PIN 2 Mode Control 00: Digital In without Schmitt Trigger01: Digital In with Schmitt Trigger10: Low Voltage Digital In11: Analog IO

PIN 2 Pull Up/DownResistor ValueSelection

00: Floating01: 50k Resistor10: 100k Resistor11: 300k Resistor

PIN 2 Pull Up/DownResistor Enable

0: Pull Down Resistor enable1: Pull Up Resistor enable



PIN 3 Mode Control 000: Digital In with Schmitt Trigger001: Digital In without Schmitt Trigger010: Low Voltage Digital In without Schmitt Trigger011: Analog IO100: Digital Out (Double Current when OE = 1)101: Open Drain110: Push Pull (Output Tri-State when OE = 0; Output Enable when OE = 1)111: Push Pull (Output Tri-State when OE = 0; Output Enable when OE = 1)





PIN 3 Digital OutSource Selection

00: From Connection Matrix01: From Connection Matrix10: S2P - Serial Output Data11: ADC - Serial Output Data

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SLG462007.4.3 PIN 4 Register Settings







PIN 4 Pull Up/DownResistor Enable 0: Pull Down Resistor enable1: Pull Up Resistor enable

PIN 4 Open Drain 2xEnable

0: Open Drain 2x disable1: Open Drain 2x enable

PIN 4 Digital OutSource Selection

0: From Connection Matrix1: ADC Output Clock



PIN 6 Mode Control 000: Digital In with Schmitt Trigger

001: Digital In without Schmitt Trigger010: Low Voltage Digital In without Schmitt Trigger011: Analog IO100: Digital Out (Double Current when OE = 1)101: Open Drain110: Push Pull (Output Tri-State when OE = 0; Output Enable when OE = 1)111: Push Pull (Output Tri-State when OE = 0; Output Enable when OE = 1)





PIN 6 Output EnableControl

0: OE Disable1: OE Enable

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SLG462007.4.5 PIN 7 Register Settings







PIN 7 Pull Up/DownResistor Enable 0: Pull Down Resistor enable1: Pull Up Resistor enable



PIN 8 Mode Control 000: Digital In with Schmitt Trigger001: Digital In without Schmitt Trigger010: Low Voltage Digital In without Schmitt Trigger011: Analog IO100: Digital Out (Double Current when OE = 1)101: Open Drain

110: Push Pull (Output Tri-State when OE = 0; Output Enable when OE = 1)111: Push Pull (Output Tri-State when OE = 0; Output Enable when OE = 1)





PIN 8 Open Drain 2xEnable

0: Open Drain 2x disable1: Open Drain 2x enable

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SLG462008.0 Digital Comparator (DCMP)

The SLG46200 has two 8-bit digital comparator logic cells available that can operate at up to a frequency of 10MHz. The inputpower for each the two DCMP logic cells is controlled by two register bits, reg for DCMP0 and reg for DCMP1.

8.1 DCMP Input Modes

Both DCMP logic cells have a positive (IN+) and a negative (IN-) input that are compared within the logic cell. The ip signal(connected to the IN+ input) takes the value from a 2:1 mux selection between an 8-bit S2P logic cell output (S2P for DCMP0and S2P for DCMP1) and the output from the SLG46200s ADC Output. The in signal (connected to the IN- input) takesthe value from a 4:1 mux selection between the 8-bit S2P logic cell output (S2P) and one of three 8-bit registers whichcan have a programmed value ranging from 0 to 255.

8.2 DCMP Output Modes

The two 8-bit data inputs from IN+ and IN- are compared within the DCMP logic cells to produce the output and a match signal.

If ip > in , the output is equal to 1, otherwise the output is equal to 0

If ip = in , the match signal is equal to 1, otherwise the match is equal to 0

Both the output and match signals are triggered by the falling edge of the CLK4PWM signal.

8.3 DCMP0 Functional Diagram

Figure 3. DCMP0 Functional Diagram

1

0S2P

reg

ADC

8-bit comparator IN-

IN+

0100

S2Preg

1110

regreg

1

0reg

Connection Matrix output

reg

match

output

in

ip

DCMP0To Connection Matrix input

To Connection Matrix input

reg Power On Select0 = Power Down1 = Power On

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SLG462008.4 DCMP1 Functional Diagram

8.5 DCMP0 & DCMP1 Register Settings

Figure 4. DCMP1 Functional Diagram

Table 7. DCMP0 & DCMP1 Register Settings

Signal FunctionRegister BitAddress Register Definition

DCMP IN- SelectionControl

0: reg for DCMP0, reg for DCMP11: from Connection Matrix Out

DCMP IN- Input Signal 00000000 to 11111111: User defined 8-bit signal inputIN1 for DCMP0 and IN3 for DCMP1



DCMP0 IN- InputSelection from reg

00: from S2P01: from reg10: from reg11: from reg

DCMP0 IN+ InputSelection

0: from S2P1: from ADC Output

DCMP0 & DCMP1Power Down

0: Power Down mode1: Power On mode

DCMP1 IN- Input

Selection from reg

00: from S2P

01: from reg10: from reg11: from reg

DCMP1 IN+ InputSelection

0: from S2P1: from ADC Output

1

0S2P

reg

ADC

8-bit comparator IN-

IN+

0100

S2P

reg 1110

regreg

1

0reg

Connection Matrix output

reg To Connection Matrix input

To Connection Matrix input match

output

in

ip

DCMP1

reg Power On Select0 = Power Down1 = Power On

To PWM in in_out

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SLG462009.0 Pulse Width Modulator (PWM)

The SLG46200 contains a 2-input Pulse Width Modulator with an 8-bit resolution and 10MHz clocking speed. The PWM isdesigned from four logic sections; a 4:1 mux for IN1 selection, an 8-bit Comparator, a Mode Selection cell and a Dead BandControl cell.

9.1 PWM Input Modes

IN1 for the PWM is an 8-bit data string that can be selected from one of four sources; the ADC Output, the S2P, the FiniteState Machine (through the Counter/Delay logic cells) or the DCMP1 logic cell. Reg is used as a 2-bit selection inputto the 4:1 mux with the previously mentioned 8-bit data strings.

IN2s 8-bit data string is sourced from the Counter/Delay logic cell in the SLG46200 device.

The 8-bit comparator logic cell has two control signals; a SET bit and a Power Down signal. Both of these signals come from theSLG46200s Connection Matrix.

If SET = 1 then PWM IN1 = 255, otherwise PWM normal operation If Power Down = 1 then PWM is off, otherwise PWM is on

9.2 PWM Output Modes

The output (OUTp) duty cycle can be set to either 0% to 99.6% or 0.39% to 100%. When both inputs are equal the output signal(match) will go high. The outputs (OUTn and OUTp) are non-overlapping.

9.3 PWM Functional Diagram

Figure 5. PWM Functional Diagram

8-bit comparator IN1

IN2

0100

ADC

From DCMP11110

S2PS2P

match

output

From Connection Matrix output

reg

Q4PWM(8 bits ramp data from counter)


Power On SET

CLK4PWM


ModeSelect

3-bit delaydead band

control

reg reg




outp

outn

out

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SLG462009.4 PWM Mode Select

The PWM Mode Select (reg) is used to control the output duty cycle:

When reg = 0

PWM output duty cycle ranges from 0% to 99.6% and is determined by: Output Duty Cycle = IN1/256 (IN1 = 0: output duty cycle = 0/255 = 0%; IN1 = 255: output duty cycle = 255/256 = 99.6%) Output signals are triggered by the rising edge of CLK4PWM

When reg = 1

PWM output duty cycle ranges from 0.39% to 100% and is determined by Output Duty Cycle = (IN1+1)/256 (IN1 = 0: output duty cycle = 1/256 = 0.39%; IN1=255: output duty cycle = 256/256 = 100%) Output signals are triggered by the falling edge of CLK4PWM

When IN1 = IN2 the match = 1

9.5 PWM Dead Band Control

The dead band interval can be controlled with NVM bits (reg). The typical dead band time starts at 8ns and can go to64ns, increasing by 8ns intervals.

For the Delay dead band control, the dead time control range is;

T D = (dead time + 1) x 8ns

For the Counter dead band control, the maximum clock frequency is 10MHz;

T C = Clock period x (dead time +1)

The total dead band time is the sum of both the Delay and Counter dead band times:

T T = T D + T C .

PWM (out)Reference

outp

outn

Dead time Dead time

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SLG462009.6 PWM Register Settings

Table 8. PWM Register Settings


PWM IN1 SelectionControl

00: from ADC Output01: from S2P 00: from Finite State Machine Counter 00: from DCMP1 Negative Input

PWM Dead BandSelection

000: 8ns 100: 40ns001: 16ns 101: 48ns010: 24ns 110: 56ns011: 32ns 111: 64ns

PWM Output Duty CycleControl

0: 0 ~ 99.6% duty cycle1: 0.39 ~ 100% duty cycle

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SLG4620010.0 Serial to Parallel / Parallel to Serial Converter (S2P)

The Serial to Parallel / Parallel to Serial Converter (S2P) transfers the data between the SLG46200 and the larger system designthrough either the serial to parallel or parallel to serial interface. It has two 16-bit registers (2 bytes) that are used for data transfer.The clock signal comes from PIN 4 and the CSB (Enable Control Signal) comes from the Connection Matrix Out.

S2P uses edge detection from the dly2 signal for capturing Counter1 data.

10.1 S2P Functional Diagram

10.2 Serial to Parallel Operation

For serial to parallel operation (S2P), the serial data in (SDI) comes from PIN 3 of the SLG46200. The S2P will produce a 16-bitparallel data output (PDO) which is used by the PWM, FSM, and the two Digital Comparators (DCMP0 and DCMP1).

Figure 6. S2P Functional Diagram

1

0

Serial toParallel

PIN 4

reg

Parallel toSerial

Serial data from PIN 3

8-bit output from Counter1

S C L K

1

0

ADC_serial_out

reg

8-bit ADC

PIN 6

PIN 7

From Connection Matrix output 1

0From Connection

Matrix output

reg

To PIN 3

PWM

FSM

DCMP0

DCMP1IN-IN+

IN-IN+

dly2 EdgeDetector

reg

C S B

CAPTURE

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SLG4620010.3 Serial to Parallel Timing Diagram

10.4 Parallel to Serial Operation

For parallel to serial operation (P2S), the 8-bit parallel data in (PDI) comes in from either the ADC Output or the Counter1logic cell. PIN 3 is used to output the 8-bit serial data out (SDO) signal.

10.5 Parallel to Serial Timing Diagram

10.6 S2P Notes

Some functions of the S2P Converter share logic cells within the SLG46200, and as a result only one of these functions can beenabled at a time. The logic cells that are shared are:

S2P serial in parallel out/S2P parallel in serial out

S2P parallel in serial out/Delay2

Figure 7. Serial to Parallel Timing Diagram

Figure 8. Parallel to Serial Timing Diagram

SCLK

12SDI MSB 14 1113 810 79 46 35 1 LSB2

CSB

PCLK

PDO PDO

SCLK

SDO MSB 46 35 1 LSB2

CSB

PCLK (load)

PDI PDO , 0, 0, 0, 0, 0, 0, 0, 0

Capture

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SLG4620010.7 S2P Register Settings

Table 9. S2P Register Settings


S2P Clock Enable 0: disable1: enable

S2P Output Sourceselection on PIN 3

10: S2P serial output data11: ADC serial output data

S2P Mode Selection 0: Serial Input (from PIN 3) / Parallel Output1: Parallel Input (from Counter1) / Serial Output

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SLG4620011.0 Analog to Digital Converter (ADC)

The Analog to Digital Converter in the SLG46200 is an 8-bit Successive Approximation Analog to Digital Converter (SAR ADC)which operates at a maximum sampling speed of 10 kHz. User controlled inputs and outputs of the ADC are listed below:

Inputs:

2ch_sel: Single-Ended Mode ADC Selection and Analog Input Mux Control Signal IN+: Single-Ended Mode Input and Differential Mode Positive Input IN-: Differential Mode Negative Input Ext_ref: ADC External Voltage Reference Input Ext_clk: ADC External Clock Input ADC_pd: ADC Power Down Signal

Outputs:

PGA_Out: Output of the 3-bit PGA to Analog Comparator 0 ADC_Series_Out: Single bit ADC serial output to PIN 3 ADC_Parallel_Out: 8-bit ADC parallel data to either the PWM or Digital Comparator 0. ADC Clock Output to PIN 4

11.1 ADC Functional Diagram

Figure 9. ADC Functional Diagram

PGA ADC

Power Down

PGA_Out (To ACOMP0)

ADC_Series_Out

ADC_Parallel_Out

1

0

Ext_clk (PIN 4)

Internal RC Oscillator

reg

VBG (1.796V)

Ext_ref (PIN 8)

VDD *0.547 10

00

01

ADC_pd_sel

ADC ProgrammableGain Amplifier

reg

1

0

PIN 6

PIN 7reg

reg

reg

1 0 reg

2ch_sel (PIN 2) V DD

VREF CLK

IN-

IN+


01

0

1

reg

reg

From ConnectionMatrix output

S2P SPI outputPIN 3

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SLG4620011.2 ADC Operation Modes

The ADC has three operating modes:

Single-Ended ADC operation using IN+ from PIN 6, when ADC_sel (reg ) is 0 Differential ADC operation using IN+ from PIN 6 and IN- from PIN 7, when ADC_sel (reg ) is 1 Pseudo-Differential ADC operation using IN+ from PIN 6 and IN- from PIN 7, when ADC_sel (reg ) and ADC_gndoff_en

(reg ) bits are both set to 1

11.3 ADC 3-bit Programmable Gain Amplifier

The ADC has a 3-bit PGA, with gain values ranging from 0.5X to 16X. The ADC Output is non-buffered only when operating insingle-ended mode and the gain = 0.5X. Single-Ended ADC operation has gain values of (0.5, 1, 2, 4 and 8X), while Differentialmode has gain values of (1, 2, 4, 8 and 16X). The PGA gain is calculated from ADC_gain_control signal (reg ), basedon binary mathematics (see PGA Register Settings Table).

For Pseudo-Differential mode, the PGA gain can only be 1X.

11.4 ADC 2-Channel Selection

When ADC_channel_sel (reg ) is set to 1, the PGA of the ADC will sample either PIN 6 or PIN 7 on the IN+ input, wherethe selection is controlled by PIN 2.

When PIN 2 is set to 0, the ADC will sample PIN 7 When PIN 2 is set to 1, the ADC will sample PIN 6

When ADC_channel_sel (reg ) is set to 0, the PGA of the ADC will sample PIN 6 on the IN+ input

11.5 ADC Input Voltage Definition

The ADCs input voltage (V IN_ADC ) is calculated based on either the single-ended or differential operation modes the logic cell isset to. In single-ended mode V IN_ADC is the sum of the positive input voltage and the gain of the 3-bit PGA. While in differentialmode the V IN_ADC is the difference between the positive and negative input voltages times the gain of the 3-bit PGA plus onehalf of the reference voltage.

Figure 10. ADC 2-Channel Selection

Equation 1. ADC Input Voltage equation

1

0

PIN 6

1 0 reg

2ch_sel (PIN 2) V DD

IN+

PIN 7

u

u

2ref gain pgainin

gain pgainadc in V GV V

GV V

_

_ _

Single-ended mode

Differential mode

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SLG4620011.6 ADC Reference Voltage

The ADCs reference voltage (V REF ) is from a 3-input mux that is controlled by the 2-bit ADC_Vref_sel signal (reg ).The three reference voltage inputs are chosen from the following:

VBG of 1.796V from Internal Source External User Defined Voltage Source (PIN 8) Power Divider of 0.547 * V DD

11.7 ADC Power Down Mode

The ADCs power down is controlled by the connection matrix output 3 where a value of 1 will drive the ADC to power downmode.

11.8 ADC Clock Source

The ADC clock source comes from either the internal RC Oscillator or an external clock from PIN 4. The selection is made fromthe ADC_clk_sel signal via reg where:

The RC Oscillator is used when the ADC_clk_select is 0 An external clock from PIN 4 is used when the ADC_clk_sel is 1

For additional information on the RC Oscillator, see section 15 of this datasheet.

Figure 11. ADC Reference Voltage

Table 10. ADC Reference Voltage.

reg V REF00 V BG (1.796V)

01 External (PIN 8)

10 Power Divider (0.547* V DD)

11 N/A

Figure 12. ADC Clock Source

VBG (1.796V)

Ext_ref (PIN 8)

VDD *0.547 10

00

01

reg

VREF

1

0

Ext_clk (PIN 4)

Internal RC Oscillator

reg

CLK

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SLG4620011.9 ADC Outputs

Both of the ADCs outputs can be shifted out through the S2P logic cell. The ADC_Series_Out produces eight single data bitsover eight individual clock cycles when activated. While the ADC_Parallel_Out produces an 8-bit data string over 16 clock cycles.

Refer to the figures below for examples showing standard output data

Figure 13. ADC Output Timing (power on signal comes from external signal)

Figure 14. ADC Output Timing (power on signal comes from register)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16CLK

D7 D0

ADC_Series_Out

ADC_Parallel_Out

16 cycles

Tri-state

ADC_pd_sel

Tri-state

T_ADC_startup = 10 s

T_out_en = ~100ns

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16CLK

reg : 00000

B7 B0

ADC_Series_Out

ADC_Parallel_Out

16 cycles

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SLG4620011.10 ADC Register Settings

Table 11. ADC Register Settings

Signal Name Signal FunctionRegister BitAddress Register Definition

ADC_pd_sel ADC power downselection

N/A to user

ADC_mux_en ADC analog input muxenable

0: mux disabled1: mux enabled

ADC_clk_sel ADC clock selection 0: internal oscillator1: external clock

ADC_Vref_sel V REF setting 00: V BG (1.796V from internal source)01: external voltage source10: power divider (V DD* 0.547)

ADC_sel ADC mode select 0: single-ended operation using PIN 61: differential mode operation using PIN 6 & PIN 7

ADC_gain_control ADC PGA gain control 000: single-ended (0.5X gain) or differential (N/A)001: single-ended (1X gain) or differential (1x gain)010: single-ended (2X gain) or differential (2X gain)011: single-ended (4X gain) or differential (4X gain)100: single-ended (8X gain) or differential (8X gain)101: single-ended (N/A) or differential (16X gain)

ADC_DAC_Vref ADC reference DACfeedback select

0: normal1: 0.5 gain (use this setting when V REF is externallyselected)

ADC_gndoff_en ADC pseudo diff inputenable under ADC diffmode

0: N/A1: enable

Pin3_dig_out PIN 3 digital outputsource selection

00/01: from connection matrix10: serial data from the S2P11: serial data from the ADC

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SLG4620012.0 Analog Comparator (ACMP)

There are two Analog Comparator (ACMP) macro cells in the SLG46200. In order for the ACMP cells to be used in a GreenPAKdesign the power up signals ( ACMP0_pdb and ACMP1_pdb ) need to be active.

Each of the two ACMP cells have positive and negative input signals that are either created from an internal V REF or provided byway of the external sources.

12.1 ACMP0 Input Modes

ACMP0s positive input (IN+) can be enabled from PIN 4 or ADC/PGA out by the ACMP0_PGA_en signal, reg. The negativeinput (IN-) of the ACMP0 cell can come from the internal V REF macro cell (which will generate a 50mV to 1.5V signal) or from anexternal voltage source that is placed on PIN 8. Selection is made using a 4-bit value from NVM, reg.

12.2 ACMP0 Functional Diagram

12.3 ACMP1 Input Modes

ACMP1s positive input (IN+) comes from PIN 7 with selection gain of 1X or 0.5X (two 50k resistor divider). TheACMP1_0.5gain_en signal (reg) is used as a control signal into a mux which has the 1X and 0.5X signals as inputs.

The negative input (IN-) of the ACMP1 cell can come from the internal V REF macro cell (which will generate a 50mV to 1.5Vsignal) or from an external voltage source that is placed on PIN 8. Selection is made using a 4-bit value from NVM, reg.

Figure 15. ACMP0 Functional Diagram

0.05V

1.5V

ACMP0

reg

1

0PIN 4

reg

reg

reg

IN-

IN+From ADC PGA

Power Down

0.1V

PIN 8

0000

1111

0001

1110

1.3V1101

reg To Connection Matrix input


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SLG4620012.4 ACMP1 Functional Diagram

12.5 ACMP Output Modes

When IN+ has a greater voltage than IN-, the ACMPs output will be 1. Otherwise, that output will be a 0 signal. The ACMP ofthe SLG46200 has an offset voltage of +/- 20mV.

12.6 ACMP 1 A Input Current Option

Both ACMPs can source 1 A on their respected outputs. This feature is controlled by the following signals:

ACMP0_l1u_en , reg for AMCP0

ACMP1_l1u_en , reg for AMCP1

When either of these signals are equal to 1 the output will source a 1 A current.

12.7 ACMP Low Bandwidth

Both ACMPs have a low bandwidth enable feature; this is controlled by the following signals:

ACMP0_low_bw , reg for AMCP0

ACMP1_low_bw , reg for AMCP1

When either of these signals are equal to 1 and the input frequency is more than 200kHz, the output retains its last value

Figure 16. ACMP1 Functional Diagram

0.05V

1.5V

ACMP1

reg

1

0PIN 7

reg

reg

reg

IN-

IN+

Power Down

0.1V

PIN 8

0000

1111

0001

1110

1.3V1101

reg

1X GAIN

0.5X GAIN



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SLG4620012.8 ACMP 50mV Hysteresis

Both ACMPs have a 50mV hysteresis feature, where either the addition or subtraction of 25mV to the IN- signal will change theACMPs output value. The 50mV hysteresis signals are controlled as follows:

ACMP0_hy_en , reg when set to 1 will turn on the hysteresis,

Output from 0 becomes 1 when IN+ IN- + 0.025V Output from 1 becomes 0 when IN+ IN- - 0.025V

ACMP1_hy_en , reg when set to 1 will turn on the hysteresis,

Output from 0 becomes 1 when IN+ IN- + 0.025V Output from 1 becomes 0 when IN+ IN- - 0.025V

12.9 ACMP0 & ACMP1 Register Settings

12.9.1 ACMP0 Register Settings

Table 12. ACMP0 Register Settings


ACMP0_pdb ACMP0 power up N/A to user - set by connecting Power Up node on ACMP0

ACMP0_l1u_en ACMP0 1 A inputcurrent option

0: disable1: enable

ACMP0_low_bw AMCP0 low bandwidthenable

0: disable1: enable

ACMP0_PGA_en PGA gain to ACMP0input enable

0: disabled (IN+ input from PIN 4)1: enabled (IN+ input from ADC PGA Out)

ACMP0_Vref_sel ACMP0 IN+ voltage

select

0000: 50mV 1000: 600mV

0001: 100mV 1001: 700mV0010: 150mV 1010: 800mV0011: 200mV 1011: 900mV0100: 250mV 1100: 1100mV0101: 300mV 1101: 1300mV0110: 400mV 1110: 1500mV0111: 500mV 1111: Ext_Vref (PIN 8)

ACMP0_hy_en AMCP0 50mVhysteresis enable

0: disable1: enable

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SLG4620012.9.2 ACMP1 Register Settings

Table 13. ACMP1 Register Settings


ACMP1_pdb ACMP1 power up N/A to user - set by connecting Power Up node on ACMP1

ACMP1_l1u_en ACMP1 1 A inputcurrent option

0: disable1: enable

ACMP1_low_bw AMCP1 low bandwidthenable

0: disable1: enable

ACMP1_0.5gain_en ACMP1's 0.5 gainenable

0: bypass (1X gain on PIN 7)1: enabled (0.5X gain on PIN 7)

ACMP1_Vref_sel ACMP1 IN+ voltageselect

0000: 50mV 1000: 600mV0001: 100mV 1001: 700mV0010: 150mV 1010: 800mV0011: 200mV 1011: 900mV

0100: 250mV 1100: 1100mV0101: 300mV 1101: 1300mV0110: 400mV 1110: 1500mV0111: 500mV 1111: Ext_Vref (PIN 8)

ACMP1_hy_en AMCP1 50mVhysteresis enable

0: disable1: enable

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SLG4620013.0 Voltage Reference Out (V REF Out)

The V REF macro cell supplies an accurate reference voltage for the SLG46200.

13.1 V REF Output

The output of the V REF cell can be connected to PIN 8 as a buffered or non-buffered output. In order to use the V REF cell withinthe SLG46200, the V REF output enable signal (reg) must be turned on.

When the Output Buffer is enabled through the Vrefo_buf_en signal (reg) the V REF s internal resistance is 1k , otherwisethe internal resistance is 100k and the signal bypasses the Negative Feedback Op Amp within the V REF logic cell.

13.2 V REF Sources

The value of V REF can be set to either use V DD /2 as a voltage source or by setting the ACMP0 to provide the desired voltage(50mV to 1.5V is selectable). The V REF macro cell uses ACMP0s negative input for the desired reference voltage.

13.3 V REF Functional Diagram

Figure 17. V REF Functional Diagram

1

0

VDD/2

ACMP0_VREFPower On

reg

reg

cvref

V r ef o

_ s el

reg

OP1

0

V r ef o

_ b uf _

en

reg

reg Vrefo_en

Vref_in PIN 8

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SLG4620013.4 V REF Register Settings

Table 14. V REF Register Settings


Vrefo_en V REF Output Enable 0: disable V REF output1: enable V REF output

Vref_on V REF Power On 0: ACMP0_Vref off1: force V REF output with ACMP0_Vref power ON

ACMP0_Vref_sel ACMP0 IN+ voltageselect

0000: 50mV 1000: 600mV0001: 100mV 1001: 700mV0010: 150mV 1010: 800mV0011: 200mV 1011: 900mV0100: 250mV 1100: 1100mV0101: 300mV 1101: 1300mV0110: 400mV 1110: 1500mV0111: 500mV 1111: Ext_Vref (PIN 8)

Vrefo_buf_en V REF Output BufferEnable 0: VREF output through buffer1: VREF output not through buffer

Vrefo_sel V REF Output select 0: ACMPO reference voltage1: VDD /2

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SLG4620014.0 Power On Reset (POR)

The Power On Reset (POR) macro cell will produce a 1 signal as an output when the power supply (V DD) rises to 2.5V or greater.This signal (POR4NVM) requires approximately 3ms of delay before it will go from low to high.

When NVM data is ready, the oscillator must be stable at the same time. If the oscillator power on is controlled by auto power onsignals such as delay cells, ADC, or PWM, the oscillator will need a maximum of 5 s to become stable.

Figure 18. Power on Reset Timing Diagram

Figure 19. Stable Oscillator wait time

POR4NVM

VDD

NVM data ready/oscillator stable

2.4V

~3ms

22 s

Oscillator stable s

Oscillator power on control signals

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SLG4620015.0 RC Oscillator (RCO)

The RC Oscillator (RCO) of the SLG46200 provides an internal clock to the ADC, PWM, DLYs and Counters. It has a frequencyrange of 40kHz 10MHz which can be adjusted by setting V REF and I BIAS.

15.1 RC Oscillator Functional Diagram

15.2 RCO Frequency Control

The RCO produces an output timing signal that has a pulse width of 5 or 10ns depending on the clock frequency.

If Clock Frequency > 1MHz, then the pulse width is set to 5ns

If Clock Frequency < 1MHz, then the pulse width is set to 10ns

The frequency is set based on the RCO_Vref_sel , RCO_Ibias_sel and the RCO_fs signals. The following table shows the variousoutput frequencies of the four registers.

Figure 20. RC Oscillator Functional Diagram

RC Oscillator

CLK4ADC ADC

PWM

Delay 0/1/2

Counter 0/2

CLK4PWM

CLK4DLY

CLK

reg

reg

reg

reg

reg

cnt1_cki_ext

F r e

q u en

c y C on

t r ol

RCO_force

RCO_fs

RCO_Ibias_sel

RCO_Vref_sel

RCO_clk_sel

PIN 2

Counter 1CLK

CLK/4CLK/8

CLK/12

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SLG4620015.3 RCO Frequency Selection

15.4 RCO Register Settings

Table 15. RCO Frequency Selection

RCO_Vref_sel RCO_Ibias_sel RCO_fs Frequency(kHz)reg reg reg reg

0 0 0 0 43

0 0 0 1 384

0 0 1 0 85

0 0 1 1 625

0 1 0 0 160

0 1 0 1 950

0 1 1 0 800

0 1 1 1 4800

1 0 0 0 128

1 0 0 1 870

1 0 1 0 240

1 0 1 1 1290

1 1 0 0 440

1 1 0 1 1750

1 1 1 0 2100

1 1 1 1 7812

Table 16. RCO Register Settings

Signal Name Signal Function Register BitAddress Register DefinitionRCO_Ibias_sel Internal OSC Current

Select 00: 0.5 A

01: 1.0 A10: 2.0 A11: 10.0 A

RCO_Vref_sel Internal OSC V REF Select

0: 1.5V1: 0.5V

RCO_force Force Oscillator PowerOn

0: Auto Power On from Delay Cell1: Force Power On

RCO_fs Oscillator FrequencyBand Select

0: Low Frequency1: High frequency

RCO_clk_sel Clock Source Select 0: Internal OSC

1: External Clock

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SLG4620016.0 Counters

There are three configurable 14-bit counters in the SLG46200. Counter2s input can be sourced from the NVM, the ADC, or theS2P, while Counter0 and Counter1s input can be sourced from the connection matrix. The clock can be sourced from either theinternal RC Oscillator (with data divider for Counter1) or from another connection matrix output.

The counters output their data to either the PWM or to the S2P. The supported counter functions include: count UP, count DOWN,KEEP, LOAD ONCE, and LOAD DATA (taken from either ADC or S2P). The three counters can also function as frequencydividers, FSM (Counter2), or PWM ramp (Counter1), while captured data is outputted to S2P.

When in count DOWN mode, the count UP/DOWN, KEEP, and LOAD signals in Counter0 and Counter1 are tied to ground andthe RCO should be forced ON for counter work.

16.1 Counter Functional Diagram

16.2 Counter Timing

Each of the counters behave as a frequency divider, where the output clock (Div_clk_out) is result of the input clock (CLK_IN)being divided by the value of the Counter Control Data (CNTx_d +1).

For Counter0:

div_clk_out0 = F CLK_IN / (reg + 1)

For Counter1:


For Counter2:


And example waveform is shown below where the output clock goes high for only one of the input clocks cycles over a timeperiod that is equal to the Counter Control Data (CNTx_d +1).

Figure 21. Counter Functional Diagram

Figure 22. Counter Behavior

Counter CNTx_cki_ext

CNTx_out_sel

CNTx_en

CNTx_clk_is

CNTx_d

Counter_end To Connection Matrix

CLK4DLY

CLK_IN

OUT

(CNT0_d + 1) CLK_IN cycles

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SLG4620016.3 Counter2 as a Finite State Machine (FSM)

Counter2 can be used as a Finite State Machine, which has features for UP/DOWN/KEEP control and loading data select.

When UP = 1: Counter2 is in up-counting mode, the Q value will count from 0 to 16383. When Q reaches 16383, theDiv_clk_out2 generates a single clock cycle pulse.

When UP = 0: Counter2 is in down-counting mode, the Q value will count from the loaded data value (based on reg+ 1) to 0. When Q reaches 0, the Div_clk_out2 generates a single clock cycle pulse.

When KEEP = 1: Q will stay at its current value. The Loading Data is only used for down-counting mode. When the Div_clk_out2 is high, the data is then loaded in the counter.

16.4 FSM (Counter2) Functional Diagram

Figure 23. FSM (Counter2) Functional Diagram

Figure 24. FSM Behavior

FSM(Counter2)

Counter2_end To Connection Matrix

reg

reg CNT2_en

CNT2_d

reg CNT2_clk_is

reg CNT2_out_sel

From Connection Matrix CNT2_cki_ext

CLK4DLY

LOAD

KEEP

UP

From Connection Matrix



OUT

Q

reg

CNT2_load_en

CNT_fsm_d_is

reg

reg CNT_fsm_load_sel

CLK_IN

OUT

Q 16383

01

1638116382

16383

0

LoadedData N

LoadedData M

23

CLK_IN

OUT

Q

01

N-2N-1

0

21

UP=1 UP=0

16382

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SLG4620016.5 Counter Register Settings

Table 17. Counter Register Settings


CNT_fsm_load_sel Counter2 14-bit inputdata selection for FSM

0: from NVM reg1: 6 most significant bits are tied to 0 and the 8 less sig-nificant bits are sourced from S2P or ADC (controlled byreg)

CNT0_en Counter0 Enable(Force Counter0 poweron)

0: Auto Power On1: Force Power On

CNT1_en Counter1 Enable(Force Counter1 poweron)


CNT2_en Counter2 Enable(Force Counter2 power

on)


CNT0_d Counter0 Control Data 1-16384: (delay time = (counter control data + 1) / freq)



CNT2_load_en Counter2 Load Signal 0: off1: enable

CNT0_clk_is Counter0 Input ClockSource Select

0: from internal oscillator clock1: from matrix


000: internal oscillator clock001: internal oscillator clock divided by 12010: internal oscillator clock divided by 4011: counter 2 over flow signal1X0: from matrix1X1: from matrix divided by 8 and synchronized by internalclock


0: internal oscillator clock1: from Counter 1 output

CNT_fsm_d_is Data Source Select forFSM (Counter 2)

0: from external source (though S2P module)1: from internal ADC output

CNT0_out_sel Counter0 Output Select 0: delay output1: counter output



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SLG4620017.1 Delay Cells Functional Diagram

17.2 Delay Timing

The delay timing of each logic cell is determined by the frequency of the RC Oscillator and the Delay Time Control registers(reg for DLY0, reg for DLY1, reg for DLY2). The formulas below list the timing delay equationsfor each logic cell;

For Delay0:

T Delay0 = (1/F OSC ) * (reg + 1)

For Delay1:

T Delay1 = (1/F OSC ) * (reg + 1)

For Delay2:

T Delay2 = (1/F OSC ) * (reg + 1)

Note: In order for these equations above to be valid the pulse width must be larger than the total rising and falling edge delay times.

Figure 28. Delay Cells Functional Diagram

Delay0

reg

reg

reg

reg

From Connection Matrix Dly_in0

DLY0_dt

DLY0_opath_s

DLY0_mode_s

DLY0_d_mode_s

Dly_out0 To Connection Matrix

Delay1

reg

reg

reg

From Connection Matrix Dly_in1

DLY1_dt

DLY1_opath_s

DLY1_d_mode_s

Dly_out1 To Connection Matrix

Delay2

reg

reg

reg

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SLG4620017.3 Delay Cells Register Settings

Table 18. Delay Cells Register Settings


DLY0_mode_s Delay0 Structure Select 0: structure 11: structure 2

DLY0_dt Delay0 - Delay TimeControl

1 - 16384: (delay time = (counter data + 1)/freq)





DLY0_d_mode_s Delay0 Mode Select 00: delay on both falling and rising edges01: delay on falling edge only10: delay on rising edge only11: no delay on either falling or rising edges



DLY0_opath_s Delay0 Output PathSelect

0: Delay0 Output1: Counter0 Output

DLY1_opath_s Delay1 Output PathSelect

0: Delay1 Output1: Counter1 Output

DLY2_opath_s Delay2 Output PathSelect 0: Delay2 Output1: Counter2 Output

DLY_in_s Delay1 and Delay2 InputSource Enable

0: Disable Delay1 and Delay2 inputs1: Enable Delay1 and Delay2 inputs from connectionmatrix

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SLG4620018.2 3-Bit LUT

The four 3-bit LUTs within the SLG46200 each take in three input signals from the connection matrix and produce a single output.

Figure 30. 3-bit LUTs

3-bit LUT0in1in0 To Connection

Matrix input out

reg



3-bit LUT1in1in0 To Connection

Matrix input out

reg



3-bit LUT2To Connection

Matrix input out

reg

in2From ConnectionMatrix output


in1

in0From ConnectionMatrix output From Connection

Matrix output


3-bit LUT3To Connection

Matrix input out

reg

in1

in0From ConnectionMatrix output From Connection

Matrix output


Table 22. 3-bit LUT0 Truth Table.

in1 in1 in0 out

0 0 0 reg

0 0 1 reg 0 1 0 reg

0 1 1 reg

1 0 0 reg

1 0 1 reg

1 1 0 reg

1 1 1 reg


in1 in1 in0 out

0 0 0 reg 0 0 1 reg

0 1 0 reg

0 1 1 reg

1 0 0 reg

1 0 1 reg

1 1 0 reg

1 1 1 reg


in1 in1 in0 out

0 0 0 reg

0 0 1 reg 0 1 0 reg

0 1 1 reg

1 0 0 reg

1 0 1 reg

1 1 0 reg

1 1 1 reg


in1 in1 in0 out

0 0 0 reg 0 0 1 reg

0 1 0 reg

0 1 1 reg

1 0 0 reg

1 0 1 reg

1 1 0 reg

1 1 1 reg

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SLG46200Each 3-bit LUT uses an 8-bit register signal to define their output functions;

3-Bit LUT0 is defined by reg




The table below shows the register bits for the standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR) that can becreated within each of the four 3-bit LUT logic cells.

Table 26. 3-bit LUT0/LUT1/LUT2/LUT3 Standard Digital Functions.

Function MSB LSB

AND-3 1 0 0 0 0 0 0 0

NAND-3 0 1 1 1 1 1 1 1

OR-3 1 1 1 1 1 1 1 0

NOR-3 0 0 0 0 0 0 0 1

XOR-3 0 1 1 1 1 1 1 0

XNOR-3 1 0 0 0 0 0 0 1

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SLG4620018.3 4-Bit LUT

The one 4-bit LUT within the SLG46200 has takes in four inputsignals from the connection matrix and produces a single out-

put.

The 4-bit LUT uses a 16-bit register signal to define the output function;


The table below shows the register bits for the standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR) that can becreated within the 4-bit LUT logic cell.

Figure 31. 4-bit LUT

4-bit LUT0in1

in0To Connection

Matrix input out

reg






in3 in2 in1 in0 out

0 0 0 0 reg

0 0 0 1 reg

0 0 1 0 reg

0 0 1 1 reg

0 1 0 0 reg

0 1 0 1 reg

0 1 1 0 reg

0 1 1 1 reg

1 0 0 0 reg

1 0 0 1 reg

1 0 1 0 reg

1 0 1 1 reg

1 1 0 0 reg

1 1 0 1 reg

1 1 1 0 reg

1 1 1 1 reg

Table 28. 4-bit LUT0 Standard Digital Functions.

Function MSB LSB

AND-4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NAND-4 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

OR-4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0

NOR-4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

XOR-4 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0

XNOR-4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

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SLG4620019.0 Digital Storage Elements (DFFs/Latches)

There are three DFF/Latches logic cells within the SLG46200 available for design. The source and destination of the inputs andoutputs for the three DFF/Latches are configured from the connection matrix.

The operation of the D Flip-Flop and Latch will following the functional descriptions below:

DFF: CLK is rising edge triggered, then Q = D; otherwise Q will not change

Latch: if CLK = 0, then Q = D

if CLK = 1, then Q will not change

19.1 DFF/Latch Functional Diagram

19.2 DFF/Latch Selection

Each of the three DFF/Latch logic cells has a selection bit that is used to define if the logic cell will be used as a D Flip-Flop or aLatch within the design. Those control bits are shown in the table below.

19.3 DFF/Latch Register Settings

Figure 32. DFF/Latch Functional Diagram

Table 29. DFF/Latch Register Settings


DFF/Latch0 Selection 0: DFF1: Latch



DFF/Latch0

CK

D To ConnectionMatrix input

Q

reg



DFF/Latch1

CK


Q

reg



DFF/Latch2

CK


Q

reg



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SLG4620020.0 Application Examples

20.1 System Reset

In the following application example, a system reset pulse can be generated from a command signal (from a microprocessor) oran external reset push button. The current reset state can be shown by adding a LED into the design. Implementing this functionwithin the SLG46200 requires the use of an input buffer, an open drain LED output driver, a de-glitch filter, and a one-shot circuit.In this example the SLG46200 replaces up to four off-the-shelf components.

20.2 Combinatorial Logic

In this application example one SLG46200 is used to replace three discrete 1G SOT23-5 packaged logic components. TheSLG46200s 2mm X 2mm TDFN packaging of this function will result in significant space savings due to fewer components usedin the final PCB design.

20.3 Time Delay

The SLG46200s independent oscillators and counter chains can be used to generate delays ranging from less than 1ms up toover 100ms. Below is an example in which a trigger on an input pin will appear at the output pin after a 4ms assertion. This canbe implemented by using a 20pF external capacitor to decrease the frequency of the oscillator from 125kHz to 31kHz (or a 32 sdelay) and configuring the associated 14-bit counter to divide by 125. In this example, minor adjustments to the delay can be

made by adjusting the value of the external capacitor.

Figure 33. Example: System Reset

Figure 34. Example: Combinatorial Logic

Figure 35. Example: Time Delay

De-Glitcher

Ext_RST#

uC_RSTART#

3.3V

One-Shot

RSTART#

RST#

IN1

IN2

IN3

IN4

OUT1

OUT2

Delay Adjust

Osc. &Counter

Trigger

Out

20pF

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SLG4620021.0 Development Tools

21.1 Software & Hardware

21.1.1 GreenPAK Designer

At the core of the GreenPAK development software suite is GreenPAK Designer, graphical schematic design tool used to createcircuit designs within the GreenPAK IC. GreenPAK Designer requires no programming language or complier.

GreenPAK Designer Software is available free of charge at http://www.silego.com/ .

21.1.2 GreenPAK Programmer

GreenPAK Programmer is flexible enough and is used on the bench in development and also suitable for factory programming.GreenPAK Programmer operates directly from GreenPAK Designer.

21.1.3 Minimum System Requirements

CPU: 800MHz RAM: 128MB Graphics RAM: 32MB Free Hard Disk Space: 50MB

Both of Silegos GreenPAK Designer and Programmer software is supported in the following operating systems:

32-bit WinXP / Vista / 7 64-bit WinXP / Vista / 7 Apple Mac OS X

21.2 Development Kits

The GreenPAK development kit is sold directly at the Silego Online Store. Please visit at http://store.silego.com/

The GreenPAK Development kit is for prototyping and development with GreenPAK Designer. The kit contains a USB Program-ming stick, USB extension cable and 50 SLG46200 samples. Everything needed for a circuit designer to start prototyping designswith the GreenPAK IC.

21.3 Project Examples

Additional GreenPAK examples designs are available on the Silego website free of charge. These designs can be downloadedand reviewed in the GreenPAK designer as a quick and efficient way to become familiar with the project development.

These examples can be found at http://support.silego.com/

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SLG4620022.0 Package Top Marking System Definition

Part ID Assembly Code

Datecode Lot

Revision

8 7 6 5

1 2 3 4

Part ID Field: identifies the specific device configuration Assembly Code Field: Assembly Location of the device. Date Code Field: Coded date of manufacture Lot Code: Designates Lot # Revision Code: Device Revision

XX ADDLR

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SLG4620023.0 Package Drawing and Dimensions

23.1 8 Lead TDFN Package

D

E

AB

C0.15

C0.15

A 1

A 3

A 2

A

DETAIL A

bC0.10 A BMC0.05 M

DETAIL B

Symbol Min(mm)NOM(mm)

Max(mm)

0.70 0.75 0.80 A0.00 -- 0.05 A1

-- 0.55 -- A2-- 0.20 -- A3

0.20 0.25 0.30b1.90 2.00 2.10D1.50 1.60 1.70D2

1.90 2.00 2.10E0.80 0.90 1.00E2

0.50 BSCe0.20 0.30 0.40L

SEATING PLANE

DETAIL AC0.10

C0.08

C

D2

Pin 10.25x45

L

DETAIL B

E 2

e

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SLG4620024.0 Tape and Reel Drawing and Specifications

24.1 Tape and Reel Specifications

24.2 Tape and Reel Drawing

Package Type # ofPinsNominalPackage

SizeUnits per

Reel

Trailer A Leader B Pocket Tape (mm) ReelDiameter

(mm)Pockets Length(mm) PocketsLength(mm) Width Pitch

8TDFN 8 2x2mm 3,000 42 168 42 168 8 4 178

F ( I I I )

W

E11.75 0.1

P04.00 0.1 (II)

A0P1

P22.00 0.05 (I)D0

1.55 0.05

D11.00 MIN

Y

Y

(I) Measured from centerline of sprocket hole(II) Cumulative tolerance of 10 sprocket holes is 0.20(III) Measured from centerline of sprocket hole to centerline of pocket(IV) Other material available

ALL DIMENSIONS IN MILLIMETERS UNLESS OTHERWISE STATED

2.25 0.1 A02.25 0.1B01.00 0.1K03.50 0.1F4.00 0.1P1

8.00 0.1W

(mm)Symbol

T0.30 0.05

B 0

K0

CL

Crossection Y-Y

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SLG4620025.0 Appendix - SLG46200 Register Definition

Bit Address Definition

reg S2P input csb source selection (out0)reg PWM power down source selection (out1)

reg PWM set source selection (out2)

reg ADC power down source selection (out3)

reg Counter0 external clock source selection (out4)

reg ACMP0 & ACMP1 power down (sig_in_CMP1_pdb) source selection (out5)

reg Counter keep source selection (out6)

reg Counter load source selection (out7)

reg Counter up source selection (out8)

reg Delay0 input selection (out9)

reg Delay1 or digital CMP source control input selection (out10)

reg Delay2 or digital CMP source control input selection (out11)reg I/O PIN 3 input (digital out source) mux A port source selection (out12)

reg I/O PIN 4 input (digital out source) mux A port source selection (out13)

reg I/O PIN 6 input (digital out source) mux A port source selection (out14)

reg I/O PIN 7 digital out source selection (out15)

reg I/O PIN 8 digital out source selection (out16)

reg I/O PIN 3 output enable selection (out17)


reg Counter2 external clock source selection (out19)



reg DFF0/Latch0 data selection (out22)reg DFF0/Latch0 ck selection (out23)

reg DFF1/Latch1 data selection (out24)

reg DFF1/Latch1 ck selection (out25)

reg DFF2/Latch2 data selection (out26)

reg DFF2/Latch2 ck selection (out27)

reg 2-bit LUT0 input0 (less significant bit) selection (out28)

reg 2-bit LUT0 input1 (most significant bit) selection (out29)




reg 3-bit LUT0 input1 selection (out33)reg 3-bit LUT0 input2 (most significant bit) selection (out34)


reg 3-bit LUT1 input1 selection (out36)





reg 3-bit LUT3 input0(less significant bit) selection (out41)

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SLG46200


reg 3-bit LUT3 input2(most significant bit) selection (out43)

reg 4-bit LUT input0(less significant bit) selection (out44)reg 4-bit LUT input1 selection (out45)

reg 4-bit LUT input2 selection (out46)

reg 4-bit LUT input3(most significant bit) selection (out47)

reg 2-bit LUT0 data

reg 2-bit LUT1 data

reg 3-bit LUT0 data

reg 3-bit LUT1 data

reg 3-bit LUT2 data

reg 3-bit LUT3 data

reg 4-bit LUT4 data

reg PIN 6 mode control000: digital in mode with Schmitt trigger001: digital in mode w/o Schmitt trigger010: low voltage digital in mode w/o Schmitt trigger (I/O pad supports input

GreenPAK

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