Graduate Computer Architecture I

Lecture 15: Intro to Reconfigurable Devices

2 - CSE/ESE 560M – Graduate Computer Architecture I

Quick Review Digital Logic

A(Q),B AND OR NAND NOR XOR NOT

0,0 0 0 1 1 0 1

0,1 0 1 1 0 1 1

1,0 0 1 1 0 0 0

1,1 1 1 0 0 1 0

3 - CSE/ESE 560M – Graduate Computer Architecture I

Typical Circuit (Full-Adder)

Input Output

C’ A B S C

0 0 0 0 0

1 0 0 1 0

0 1 0 1 0

1 1 0 0 1

0 0 1 1 0

1 0 1 0 1

0 1 1 0 1

1 1 1 1 1

4 - CSE/ESE 560M – Graduate Computer Architecture I

NAND

5 - CSE/ESE 560M – Graduate Computer Architecture I

Full-Adder Using NAND

Input Output

C’ A B S C

0 0 0 0 0

1 0 0 1 0

0 1 0 1 0

1 1 0 0 1

0 0 1 1 0

1 0 1 0 1

0 1 1 0 1

1 1 1 1 1

A B C’

S

C

6 - CSE/ESE 560M – Graduate Computer Architecture I

VLSI Layout of NAND Full-Adder

7 - CSE/ESE 560M – Graduate Computer Architecture I

Full-Adder Using Array of Logics

Input Output

C’ A B S C

0 0 0 0 0

1 0 0 1 0

0 1 0 1 0

1 1 0 0 1

0 0 1 1 0

1 0 1 0 1

0 1 1 0 1

1 1 1 1 1

C’S

8 - CSE/ESE 560M – Graduate Computer Architecture I

Programmable Logic (PLA/PAL/PLD)

9 - CSE/ESE 560M – Graduate Computer Architecture I

More Complex Programmable Logic

10 - CSE/ESE 560M – Graduate Computer Architecture I

Programmable Logic

Inexpensive One-time Programmable Devices

Complex Programmable Logic DevicesBURN it once and use!

11 - CSE/ESE 560M – Graduate Computer Architecture I

Full Adder Using Memory

Input Output

C’ A B S C

0 0 0 0 0

1 0 0 1 0

0 1 0 1 0

1 1 0 0 1

0 0 1 1 0

1 0 1 0 1

0 1 1 0 1

1 1 1 1 1

8 by 2-bitMemory

Addr

Data

3bit AddressConcat(C’,A,B)

2bit DataConcat(S,C)

12 - CSE/ESE 560M – Graduate Computer Architecture I

Simple Wire Switch (4x4 Crossbar)

Input Ports

Ou

tpu

t Po

rts

13 - CSE/ESE 560M – Graduate Computer Architecture I

Field Programmable Gate Array

14 - CSE/ESE 560M – Graduate Computer Architecture I

Logic Block (Xilinx Virtex 4000)

Registers

SRAM based Logic(4 input Look-up-table)

15 - CSE/ESE 560M – Graduate Computer Architecture I

FPGA Architecture

16 - CSE/ESE 560M – Graduate Computer Architecture I

DESIGN ENTRY

CORE GENERATIONRTL HDL EDITING

RTL HDL-CORESIMULATION

SYNTHESIS

IMPLEMENTATION

TIMING SIMULATION

FPGA PROGRAMMING & IN-CIRCUIT TEST

Design Flow

17 - CSE/ESE 560M – Graduate Computer Architecture I

Language Construct Templates

HDL EDITOR

DESIGN WIZARD LANGUAGE ASSISTANTAccessed within HDL Editor

RTL HDL Files

HDL Module Frameworks

HDL Design Flow

18 - CSE/ESE 560M – Graduate Computer Architecture I

CORE GENERATOR

Select core and specify input parameters

HDL instantiation module for core_name

EDIF netlist for core_name

Other core_name files

IP Core Generation

19 - CSE/ESE 560M – Graduate Computer Architecture I

Compile HDL Files

Waveforms or List Files

Set Up and Map work Library

RTL HDL Files

Test Inputs or Force Files

HDL instantiation module for

core_names

EDIF netlists for core_names

Functional Simulate

Testbench HDL Files

MODELSIM

Functional Simulation

20 - CSE/ESE 560M – Graduate Computer Architecture I

All HDL Files

Gate/Primitive Netlist Files (EDIF or XNF)

Select Top Level

Select Target Device

Edit FPGA Express Synthesis Constraints

Synthesize

Synthesis/Implement-ation Constraints

Synthesis Report Files

EDIF netlists for core_names

FPGA EXPRESS

Synthesis

21 - CSE/ESE 560M – Graduate Computer Architecture I

Model Extraction

Netlist Translation

Map

Place & Route

BIT File

Create Bitstream

Timing Model Gen

Gate/Primitive Netlist Files (XNF or EDN)

Standard Delay Format File

HDL or EDIF for Implemented Design

XILINX DESIGN MANAGER

Implementation

22 - CSE/ESE 560M – Graduate Computer Architecture I

Test Inputs, Force Files

MODELSIM

Compile HDL Files

Waveforms or List Files

Set Up and Map work Directory

Compiled HDL

HDL Simulate

Standard Delay Format FileHDL or EDIF for Implemented Design

Testbench HDL Files

Timing Simulation

23 - CSE/ESE 560M – Graduate Computer Architecture I

Bit File

FPGA

GXSLOAD

GXSPORT

Input Byte

Other Inputs

Outputs

Programming FPGA

24 - CSE/ESE 560M – Graduate Computer Architecture I

Emergence of FPGA

• Great for Prototyping and Testing– Enable logic verification without high cost of fab– Reprogrammable Research and Education– Meets most computational requirements– Options for transferring design to ASIC

• Technology Advances– Huge FPGAs are available

• Up to 200,000 Logic Units

– Above clocking rate of 500 MHz• Competitive Pricing

25 - CSE/ESE 560M – Graduate Computer Architecture I

System on Chip (SoC)

• Large Embedded Memories– Up 10 Megabits of on-chip memories (Virtex 4)– High bandwidth and reconfigurable

• Processor IP Cores– Tons of Soft Processor Cores (some open source)– Embedded Processor Cores

• PowerPC, Nios RISC, and etc. – 450+ MHz– Simple Digital Signal Processing Cores

• Up to 512 DSPs on Virtex 4• Interconnects

– High speed network I/O (10Gbps)– Built-in Ethernet MACs (Soft/Hard Core)

• Security– Embedded 256-bit AES Encryption

26 - CSE/ESE 560M – Graduate Computer Architecture I

Computational Density

Higher number means greater efficiency

27 - CSE/ESE 560M – Graduate Computer Architecture I

Potential Advantages of FPGAs

28 - CSE/ESE 560M – Graduate Computer Architecture I

Summary

• Rapidly changing platform– Ten thousand times in silicon chip capacity– Cost did not increase that much

• Same designs– Von Neuman architecture time-multiplexes– Old processor designs, only smaller– Not much innovations

• Programmable SW/HW Platforms– General Computing Systems do not have to look

like traditional processors– Future?