Government of India Indian Space Research Organization Space … · 2016-09-29 · Microwave Remote...

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REQUEST FOR PROPOSAL (RFP)

FOR

FABRICATION, ASSEMBLY AND TESTING

OF

SOLID STATE RECORDERS

RFP No.: SAC-MRSA-MSDG-SSR-01-2016

May-2016

Government of India Indian Space Research Organization

Space Applications Centre Ahmedabad-380015

INDIA

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DOCUMENT CONTROL AND DATA SHEET

REPORT NO : RFP NO.: SAC-MRSA-MSDG-02-2016

TITLE : REQUEST FOR PROPOSAL (RFP) FOR FABRICATION,

ASSEMBLY AND TESTING OF SOLID STATE RECRODERS

TYPE OF REPORT : TECHNICAL

TOTAL PAGES : 30

PREPARED BY

: MRSA SSR DESIGN TEAM

REVIEWED BY : TECHNICAL REVIEW COMMITTEE

ORIGINATING UNIT : MRSA /SAC

DISTRIBUTION : WITHIN ISRO AND CONCERNED INDUSTRY ONLY

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Contents 1. Introduction ..............................................................................................................................................5

2. Overview of the SSR .................................................................................................................................6

2.1 Technical Description. .......................................................................................................................... 6

2.2 PCB and Component Placement ........................................................................................................... 8

2.3 Bill of Materials of the SSR for Cost Estimation Purposes .................................................................. 10

2.4 Post-Production Testing Requirements for Cost Estimation Purposes. ............................................. 13

3. Scope of work ........................................................................................................................................ 20

4. Schedule of Delivery .............................................................................................................................. 22

4.1 Deliverables. ....................................................................................................................................... 22

4.2 Delivery Period. .................................................................................................................................. 23

4.3 Warranty. ............................................................................................................................................ 23

5. Vendor’s Compliance ............................................................................................................................. 24

6. Schedule of FIM (Free Issue Material) ................................................................................................... 24

7. Responsibilities of SAC and the Vendor ................................................................................................ 26

8. Terms and Conditions ............................................................................................................................ 27

9. Typical sequence of events & guidelines to vendors for submitting the offer ..................................... 28

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ABBREVIATIONS:

AAP: Airborne Application Product

BOM: Bill of material

A-BOM: Approved Bill of Materials

SAC: Space Applications Centre

ISRO: Indian Space Research Organization

RFP : Request For Proposal

SSR : Solid-State Recorder

DSS: Digital Subsystem

PCB: Printed Circuit Board

SMD: Surface Mountable Device

FIM: Free-issue material (Material to be issued free by MRSA-SAC for use in the work of this RFP)

Hi-Rel: High Reliability

MOQ: Minimum Order Quantity

GBP: Ground-Based Product

GBMH : Ground based Mechanical hardware

ME : Mechanical housing/box/enclosure

MRSA: Microwave Remote Sensors Area, an entity inside SAC, Ahmedabad.

1. Introduction

Microwave Remote Sensors Area of Space Applications Centre (SAC, ISRO) is engaged in the

development of a number of state of the art microwave imaging and other remote sensing

payloads for various civilian applications like agriculture, urban and geological studies, soil

moisture studies, disaster monitoring and support and so on.

Microwave remote sensing payloads, which have advantages like day-night operation and ability

to work through cloud-cover, are highly data intensive, both in terms of speed and quantum of

data generated per scene or observation. During the development of the microwave remote

sensing payloads high-speed high-capacity data recorders are routinely necessary from

subsystem level development and testing (Digital Subsystem of DSS) to complete payload testing

characterization and evaluation. Also many airborne payloads like the Airborne synthetic

aperture Radars for Disaster Monitoring need the recorders as part of the payload for data

gathering missions. The programme may feed into space borne applications in the future.

MRSA has developed the solid-state recorder domain for such purposes and proposes to involve

reputed Indian vendors from the Industry having relevant experience for the realization of such

SSRs.

This Request for proposal (RFP) document provides the details of the work involved, mode of

operation, responsibility, delivery schedule, tendering procedures etc.

This is a two-part tender. The Vendor shall submit proposal in two parts

- Technical Proposal

- Commercial Proposal

Two Options of the modus operandi are being considered. In Option I, the PCB and enclosure

form the free-issue material (FIM) from SAC to the successful bidder for carrying out the work,

and procurement of all other components is his responsibility. In Option II, all components

necessary for the work shall be issued by SAC as FIM, and the vendor only performs the

fabrication/assembly work (while taking care any consumables or fabrication materials

necessary). In both cases testing the hardware as pert he provisions of this RFP is Vendor’s

responsibility. Bidders need to quote for both options.

2. Overview of the SSR

2.1 Technical Description.

The SSR in question is a single-board entity on an MLB (12-layer or higher) with a large number

of components. Fig 1 shows a block diagram of the recorder hardware.

The SSR is configured around a Xilinx Virtex-4 FPGA, which acts as the master controller as well

as data highway between the input and the storage medium, a bank of ONFI NAND flash devices.

This FPGA performs the overall coordination, command decoding, distribution of incoming high

speed data to various flash devices and subsequent data retrieval through USB 2.0 port. A total

of 36 NAND flash devices have been used to achieve a sustained data rate of up to 1.0. Figure-1

shows the overall block diagram of this SSR, which operates on a single raw bus supply (9-36)

volts, internally isolated. All power supply conditioning and derivation of different supply voltages

required for the operation of the FPGA and other devices are internally generated from a master

step-down 5V isolated DC/DC convertor using POL power conditioning philosophy .

Fig. 1. A block diagram of the Solid State Recorder

The recorder accepts high-speed data from Serializer-Deserializer (SerDes) on to an interfacing

SERDES part TLK2711 (thorugh two PCB mount SMA connectors for a differential input of 100 Ω

or two 50Ω lines); the output of the SERDES is received in the FPGA, double buffered and then

distributed to multiple flash memories in parallel for writing at a slower speed. Open NAND Flash

Interface (ONFI) protocol has been used for all communication with flash devices. A Windows

XP/7 based Graphical User Interface (GUI) generates all the commands required for end-to-end

operation of the SSR. This SSR board is a dense 12-layer (or higher) PCB comprising of Ball Grid

Array (BGA) FPGA device as well as multiple NAND flash devices. To optimally utilize the PCB area,

18 NAND flash chips have been mounted on the top side of the PCB and same number of chips

has been mounted on the bottom side. These large numbers of NAND flash devices help in

increasing the input data rate handling capability as well as increase the data storage capacity of

the board.

Inputs to the SSR can also be through RS232, 422 and LVDS serial sources, or LVDS 16-bit parallel

sources, and these are interfaced through PCB mount Standard-D type connectors.

Data retrieval from the SSR is through a FTDI USB2.0 interface module which is integrated on to

the main board. This takes in parallel data from the FPGA during data retrieval and pushes it

into a PC through proprietary data retrieval software running in the PC.

Fig. 2. The completed SSR

2.2 PCB and Component Placement

The SSR is built on a multi-layer board (12 Layers or higher, which is part of FIM) of dimensions

150x200mm and has all components mounted on two sides of the PCB. In the picture above, the top

side of the PCB is shown. It may be noted that the image represents a previous version of the SSR

and although very similar, is not an exact replica of the PCB to be used in this contract.

The main logic backbone of the operation, the FPGA a BGA 1148-pin package, is on the top side as

are POL regulator (LGA/PTH packages) generating the various voltages required by the board. The

flash devices (TSOP48) are distributed along the long edges of the PCB; 36 devices are distributed as

4 rows (two on top side, two on bottom side). All connectors are distributed on the two shorter edges

of the PCB on top side only.

Fig. 3. A picture of the mounted PCB of the Parallel SSR

Flash Memory

(TSOP48)

(More on Bottom Side)

Murata Isolated DC/DC

Converter

9 Channel 64 Pin

LVDS Transceivers

FPGA

(1148 BGA)

FTDI USB

Module

EMERSON POL

Fig. 3. Indicative Component Placement Diagram of the SSR; top, Top Layer of the PCB; Bottom,

Bottom Layer of the PCB.

2.3 Bill of Materials of the SSR for Cost Estimation Purposes

All components shall be of industrial grade. If any specific device is not available in industrial grade,

use of commercial grade components can be mutually agreed upon.

Spare components (sufficient to populate 2 cards) shall be procured and delivered along with the

fabricated units.

S.No.

Component Type

Ratings / Value Package Recommended Make

Quantity Per SSR

Remarks

1 Resistors, Chip, 1% Tol, 100ppm or better TC, various values

Values TBD; P=40mW or better

0402 Vishay, Panasonic, Yageo, Murata, Phycomp, Susumu, Bourns

350 or less

2 Resistors, Chip, 1% Tol, 100ppm or better TC, Various Values



25

3 Precision Resistros, Chip, 0.1% Tol, 25ppm or better TC, Various Values,



25

5 Capacitors, ceramic chip, 10% Tol

0.1 / 0.01uF, 25V or more

0402 Kemet, AVX, Murata, EPCOS, Cornell, Johanson Technology, TDK, Vishay, Yageo

350 or less

Decoupling

6 Capacitors, High-frequency ceramic chip

100pF/120pF 0402 Kemet, AVX, Murata, EPCOS, Cornell, Johanson Technology, TDK, Vishay, Yageo

10 High-speed Signal AC Coupling

7 Capacitors, Tantalum

10 to 330uF Case D/E

Kemet, AVX, Murata, EPCOS, Cornell, Johanson

25 or less

Power management

Technology, TDK, Vishay, Yageo

8 Capacitors, ceramic chip

Values TBD, 100V or more

1206 Kemet, AVX, Murata, EPCOS, Cornell, Johanson Technology, TDK, Vishay, Yageo

10 Power management

9 Capacitor, Electrolytic

1000uF 100V or more

Axial Kemet, AVX, Murata, EPCOS, Cornell, Johanson Technology, TDK, Vishay, Yageo

2 Power Management

10 Capcitor ceramic MLC

100uF 10V or more

SMD Kemet, AVX, Murata, EPCOS, Cornell, Johanson Technology, TDK, Vishay, Yageo

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11 Transistors PBSS8110Y SMD NXP 2

12 Transsitors 2N2222 SMD ST,NTE,NXP,SEMELAB, Microsemi, TT, Fairchild

2

13 Transistors 2N3904 SMD ST,NTE,NXP,SEMELAB, Microsemi, TT, Fairchild

2

14 Diodes 1n4007 SMD IR, OnSemi, ST, Microsemi, MCC, DI, Fairchild

4

15 Dides Zener Values TBD SMD IR, OnSemi, ST, Microsemi, MCC, DI, Fairchild

2

16 POL Convertor

PTH04T231W PTH04T241W PTH04T261W

Board-mount Through -hole module

Texas Instrument 4 Pin version

Or

Emerson Power Module LGA10

LGA Emerson 4 SMD LGA package

17 Isolated DC/DC Convertor

UEI30-050-Q12P-C Board Mount through-hole module

Murata 1 Through hole module

18 LVDS transceiver

DS92LV090A TQFP64 Texas Instruments 4

19 Optocoupler

VO221AT or pin-compatible equivalent

Vishay 2

20 SERDES TLK2711 Texas Instrument

1

21 RTC DS3234 Dallas Semiconductor

1

22 Configuration Prom

XCF32P Xilinx 1

23 FPGA Virtex4 XC4VSX55-10FFG1148I

Xilinx 1

24 Flash Memory

MT29F128G08AJAAA

TSOP48 Micron Technology 36

25 Oscillator VCC1-B3F-100M000000

SMD Vectron 1

26 Right-Angled PCB Mount SMA

PCB Mount

4

27 26 Pin High Density D-type Right-angle Male

C115440-0220 PCB Mount

C&K 1

28 78 Pin High Density D-Type Right-angle Male

C115440-0226 PCB Mount

C&K 1

29 LED Indicators, Red, Amber and Green

3mm Panel Mounted

Any Reputed Reliable

4 Three LEDs with standard socket

30 Round-Shell Connector

FC684202 Or Equivalent

Cliff Electronic Components or Reputed alternative

2

31 Push-Button Switches


2 Suitable for Panel Mounting through 8mm circular cut-out

32 Toggle Switches


2 Suitable for Panel Mounting

through 8mm circular cutout

Note 1: This table is indicative; the actual BOM may be slightly different. 2. The number of components of any kind is not likely to exceed the numbers mentioned in this list. 3. Prospective bidders are cautioned about (a) the heterogeneous nature of type of components like SMD and through-hole, LGA, high-density BGA etc. packages. And (b) It may be necessary to mount the components in stages. Please refer the section on recommended fabrication flow.

2.4 Post-Production Testing Requirements for Cost Estimation Purposes.

It may be noted that minor changes may be effected in the steps of these tests and the details

provided to the successful bidder at the time of award of contract shall be followed for the actual

realization process. The details below shall be deemed indicative for cost estimation purposes.

The following tests need to be successfully cleared by each hardware unit to qualify for delivery.

The tests and observations shall be recorded in detail in the corresponding test reports for each

deliverable unit and the test certificates shall form part of delivery. The vendor shall demonstrate

all the tests on randomly selected sample units at vendor’s premises prior to delivery.

List of tests on the SSR units:

Note:

1. At least one PC with I5 or better processor, running Windows-7 with 4GB or more RAM and 1TB hard disk and 2 sparable USB 2.0 ports will be required for the test activity.

2.All interconnect cables required for the test activity is Vendor’s responsibility Including OLMs.

3. The detailed test procedures and necessary software/firmware will be provided by MRSA-SAC.

4. Test Pattern Generator, if any required, will be provided by MRSA-SAC. Test equipment (PC, DSO, Power supply units and other test/measurement equipment) is the responsibility of the vendor.

S.No. Test Hardware Requisites

Software/Firmware Requisites

Remarks

1 SSR Command

Interface Test

Cable Set 1 FPGA Bit File A SAC PC Test Utility

2 SSR USB Connectivity

Test

Cable Set 2 FPGA Bit File B SAC PC Test Utility

3 SSR Memory Modules

Test

Cable Set 2 FPGA Bit File C SAC PC Test Utility

4 SSR Serdes Interface

Test (Internal

Loopback)

Cable Set 2 FPGA Bit File D SAC PC Test Utility

5 SSR Serdes Interface

Test (External

Loopback)

Cable Set 3 FPGA Bit File E SAC PC Test Utility

6 Parallel Data Interface

Test

Cable Set 4 FPGA Bit File F SAC PC Test Utility

The necessary bit files and PC Utilities will be supplied by SAC.

List of Equipment Required for Testing the SSR

1. D.C Power Source–250 Watt (programmable in the range of upto 50 Volts and 5 Amps)

2. Multimeter

3. Digital Oscilloscope, 500 MHz or more, 2 channels or more

4. Magnified inspection equipment on test desk

5. JTAG programmer and downloading cable for Xilinx FPGA/PROM

6. PC/Laptop with Windows 7/XP with at least two USB 2.0 ports

7. USB to COM port convertor, Moxa make (if COM port not available on PC)

8. 78 pin and 26 pin Online Monitor.

9. Cable Harness

a. MF141 with SMA connector – Length 1 metre, Quantity = 02+02(Spare), All cables

should necessarily be of equal length.

b. 24 Gauge Teflon for Power Supply and COM Port connections

c. USB 2.0 cables (Mini B to Type A)

2.4.1 SSR Command Interface Test

The following steps are to be performed for SSR Command Interface Test: -

a) Program the FPGA with the bit file supplied by SAC.

b) Connect the RS 232 port of the SSR to the Laptop/PC. On the SSR GUI, select the connected

COM port no.

c) Issue ‘Open Port’ command. ‘Port Opened Successfully’ message will be displayed. If this

message is not displayed, then issue ‘Close Port’. Check and select the correct Port

number and then issue ‘Open Port’ command again.

d) Issue ‘SSR Reset’ command from GUI and wait for response on the terminal. SSR will

respond with ‘0xF0’ status. This confirms the command link is OK.

2.4.2 SSR USB Connectivity Test

The following steps are to be performed for SSR USB Connectivity Test: -


b) Connect the USB port of SSR to PC/Laptop. Power up the SSR unit. The orange color LED

of the USB module on the SSR will light up indicating Okay status.

c) On the SSR GUI, issue ‘USB Test’ command.

d) SSR will respond the message – ‘One UM232H Device Found’.

2.4.3 SSR Memory Modules Test

The following steps are to be performed for SSR Memory Modules Test: -



COM port no.




d) Issue ‘Reset Memory’ command from GUI and wait for response on the terminal. SSR will

respond with ‘0xF0’ status.

e) Issue ‘Read Flash Devices ID’ command to the SSR. The SSR will respond with the Flash ID

numbers of the memory chips. This completes the SSR Memory modules test.

2.4.4 SSR Serdes Interface Test (Internal Loopback)

The following steps are to be performed for the Serdes Interface Test (Internal Loopback): -



COM port no.




d) Issue ‘Reset FPGA’ command from GUI and wait for response from the SSR. GUI will display

‘Reset applied successfully’.

e) Issue ‘Reset Memory’ command from GUI and wait for response on the terminal. SSR will

respond with ‘0xF0’ status. This confirms the SSR Command link is okay.

f) Issue ‘Read Flash Devices ID’ command to the SSR. The SSR will respond with the Flash ID

numbers of the memory chips. This confirms the SSR Memory modules are okay.

g) In the GUI, enter the Filename and File size as 128MB and press ‘SSR Start’.

h) In the GUI press ‘Files on SSR’ and select the above mentioned Filename and press ‘SSR

Playback’ for downloading data from the SSR. The specified file of 128MB will be created

in specified directory. Open the file in a binary viewer software e.g. Hex Editor and observe

ramp pattern in data

2.4.5 SSR Serdes Interface Test (External Loopback)

The following steps are to be performed for the Serdes Interface Test (External Loopback): -



COM port no.




d) Issue ‘Reset FPGA’ command from GUI and wait for response from the SSR. GUI will display

‘Reset applied successfully’.

e) Issue ‘Reset Memory’ command from GUI and wait for response on the terminal. SSR will

respond with ‘0xF0’ status. This confirms the SSR Command link is okay.

f) Issue ‘Read Flash Devices ID’ command to the SSR. The SSR will respond with the Flash ID

numbers of the memory chips. This confirms the SSR Memory modules are okay.

g) In the GUI, enter the Filename and File size as 128MB and press ‘SSR Start’.

h) In the GUI press ‘Files on SSR’ and select the above mentioned Filename and press ‘SSR

Playback’ for downloading data from the SSR. The specified file of 128MB will be created

in specified directory. Open the file in a binary viewer software e.g. Hex Editor and observe

ramp pattern in data

2.4.6 Parallel Data Interface Test

The following steps are to be performed for the Parallel Data Interface Test: -


b) Connect the 78 pin OLM to 78 pin connector on the SSR.

c) Observe the waveforms on the 72 designated pins of the K2 connector using the OLM.

Check to confirm if the signal is coming on all the 72 pins. Capture the waveforms on the

oscilloscope. This completes the Parallel Data Interface Test.

2.4.1 Post Production Endurance Test

All units delivered are to be subjected to a room-temperature endurance test of 168 hrs (7

days) duration. This test screens the devices for infant mortality of components and

workmanship. The unit will be kept on and a prescribed set of observations, a subset of the

other tests detailed above, taken every day. The test setup will be a subset of what is described

above and there will not be any change in the set up during the period of the test.

3. Scope of work

The scope of work is fabrication of the solid-state recorders from MRSA-SAC supplied

information, and material (FIM) as well as material procured by the vendor (as the case may be),

test the hardware and supply the finished products.

There are two options under consideration:

3.1 Option I

Part of the material (viz, PCB and mechanical enclosure and test software/firmware) necessary

for the fabrication will be provided by MRSA-SAC as FIM (Free-Issue Material); the successful

bidder shall procure all other components and other items (including any necessary consumables)

and fabricate the SSR units. The following presents the details of the scope of work; however it

may be noted that the successful bidder shall be responsible for the realization and delivery of

the tested hardware proper, in material and spirit, notwithstanding any missing steps of the

process in the following.

1. Cross-check the BOM and the PCB layout with reference to every component on the board

and get clarifications if necessary from MRSA-SAC. The BOM shall then be certified by

MRSA-SAC as well as the vendor and serve as the “Approved BOM” (A-BOM)

2. Procure and complete incoming inspection of all electronic components (active, passive etc)

necessary as per the A-BOM.

3. Populate the PCB using proper techniques, materials and applicable vendor’s QC and QA

procedures. MRSA-SAC recommends that the populating of the PCBs shall be done in stages

as shown in the suggested flow of fabrication with intermediate electrical testing schedules.

The first unit shall be fabricated as per the MRSA-SAC supplied flow. However it may be

noted that the vendor is free to combine some or all stages as deemed fit for further units

with the understanding that the responsibility of producing completely tested and

functional units rests with him.

4. Functional Testing at card level after completion of all mounting activity, as per the Schedule

of Card-Level Tests.

5. Wired card assembly in the mechanical enclosures followed by card-level testing (as per the

schedule of Post-Production acceptance) with test report generation.

6. Review of the test reports and giving shipment clearance by MRSA-SAC

7. Delivery of units at SAC with test reports by the vendor.

The vendor shall provide justification at the time of bidding showcasing his capability for carrying out

each of the above activities including the methods of implementation and necessary technical

expertise to build, optimize, test and deliver the products.

Notes.

1. The bill of materials of the SSR provided in this RFP is meant for commercial cost estimation

purposes, and does not constitute the assembly BOM. The assembly BOM may have very

minor variations in the quantities of the components (of passive/low-cost components only),

and the differences are expected to be very marginal and of no significant commercial

consequence.

2. Vendor must have all necessary fabrication facilities, proper equipment, materials/tools for

the assembly, handling and testing.

3. The vendor shall have experience of having worked on digital boards of similar complexity

(high-density FPGAs like the Virtex/Kintex series of Xilinx or equivalent with high serial data

speeds.

4. Any custom test set-ups/jigs and other specific material including cables necessary for the

execution of this work including the testing phase shall be arranged by the vendor. Such

material shall be part of the delivery to SAC at the conclusion of the contract.

5. The detailed specifications in this document may be updated and finalized by SAC before

finalization of the contract. Any changes necessitated during the developmental phases will

be mutually discussed and agreed upon.

6. SAC reserves the right to participate/audit/review the progress of work at defined stage of

development and testing.

7. Free Issue material: Components supplied by SAC should be considered as Free-Issue

Material (FIM) to vendor. Vendor is required to submit a bank guarantee for the FIM supplied

by the SAC The value of the bank guarantee shall be as per SAC purchase procedure against

FIM.

8. Precautions in the Assembly Process

The Board has POL DC/DC convertors whose voltages are dependent on the values of

certain components like resistors on the board. A mistake in any one of these

components may lead to generation and dissemination of harmful supply voltages on

the board leading to extensive damages. Bidders are cautioned against such a

possibility and advised take adequate precautions. Any damage arising out of such an

eventuality will be the vendor’s responsibility.

The assembly process may involve multiple types of soldering processes; consequently

there may be a need for checks in between to make sure the soldering is all right, as

rework may or may not be possible after the subsequent stages of processing – like

for example if a reflow process may not be possible for incremental component

addition. The vendor shall sequence the assembly process accordingly.

A recommended assembly process in which the components are mounted in stages is

presented in Annexure 1. The first unit must be fabricated as per this procedure and

tested. It is not mandatory to follow this process for further units but the successful

bidder may choose to follow the same. However, he may choose to adopt any

sequence suitable for him for the remaining quantity at hand. It shall be reiterated

that the vendor is responsible for any and all issues that arise during the entire

manufacturing process and it is his sole responsibility to supply completed, tested

quality hardware.

3.2 Option II

In Option II, The FIM supplied by SAC will Include all electronic components necessary for

the fabrication of the SSR; the vendors shall not procure any components. However, any

fabrication materials and consumable necessary in the manufacturing process shall be the

vendor’s responsibility in either option.

All the other details remain the same as Option I

4. Schedule of Delivery

4.1 Deliverables-Option I

The following are the deliverables at the completion of this contract in Option I:

1 Duly manufactured and tested Solid-State Recorders as per MRSA-SAC design

15 units

2 Test-jigs, fixtures, cables, other hardware realized for the purpose of testing (if any) including OLMs

2 Sets

3 Spare components Sufficient for 3 Cards

3 Test Reports of the delivered units 15 sets

4.1 Deliverables-Option II

The following are the deliverables at the completion of this contract in Option II:

1 Duly manufactured and tested Solid-State Recorders as per MRSA-SAC design

15 units

2 Test-jigs, fixtures, cables, other hardware realized for the purpose of testing (if any) including OLMs

2 Sets

3 Test Reports of the delivered units 15 sets

4.2 Delivery Period.

Option I: The delivery period shall be 20 weeks from the date of Issue of FIM post

order placement.

Option II: The delivery Period Shall be 8 Weeks from the date of Issue of FIM post

order placement

4.3 Warranty.

The vendor shall furnish a warranty for a period of 1 year from the date of delivery at

SAC for all workmanship related factors in all units supplied.

5. Vendor’s Compliance

The prospective vendors shall indicate their compliance to the following requirements. Prospective bidders

are required to establish compliance by entering in the ‘compliances’ column their responses to the

requirements. Symbolic or single-word entries shall be sufficient grounds for disqualification; the entries shall

carry enough information about the vendor to evolve a decision on the suitability of the vendor or otherwise

for the current contract. Bidders are encouraged to provide as much information as possible against each

requirement to enable informed decision making.

S.no.

Description Requirement Remarks Compliances (Please provide detailed information)

1 The bidder shall possess the requisite technical expertise to execute this fabrication contract.

2 The bidder shall possess the requisite technical infrastructure to execute this fabrication contract.

3 The bidder shall possess the requisite technically qualified man-power to execute this contract

4 The bidder shall possess requisite financial strength to execute this contract

5 The bidder shall comply with the schedule of delivery as specified.

6 The bidder shall have past experience of working with high-density FPGA of Xilinx make like Virtex 4/Kintex / or later (higher) series. The bidder shall specifically mention the work experience and attach relevant information.

6. Schedule of FIM (Free Issue Material)

This RFP is for the realization of Solid-state recorder units in quantities mentioned under the

Schedule of Delivery.

Option I

All components and other necessary items for the manufacture of the hardware and for the test

purposes shall be procured by the vendor, except the following material which will be issued as

Free-Issue material to the vendor.

S.No. Material Description Qty Unit Remarks

Reference Cost

1 Bare PCBs 11 Rs. 50,000/-

The extra unit is meant to serve any test jigs or production related purposes and is to be returned at the completion of contract.

2 Enclosures with necessary mechanical hardware

Rs 15,000/-

Any software/Firmware necessary for the testing process at various stages will be provided by SAC.

Option II

All components necessary for the fabrication of the SSR shall be issued by MRSA-SAC as per the A-BOM as

FIM. The vedors shall not procure any components.

However it may be noted that in either option it is the vendor’s responsibility to take care of the necessity of

fabrication material / consumables which are considered part of the fabrication/assembly work.

7. Responsibilities of SAC and the Vendor

List of activities and the distribution of responsibility are tabulated below.

Table 1: List of Activities

Sr. No.

List of Activities Responsibility

SAC Vendor

1. Necessary design details to carryout fabrication and testing (The vendor is needed to execute an NDA before receipt of this information)

-

2. Test Methodologies and details thereof required to firm up the actual test procedures

-

3. Finalization of the detailed BOM and test procedures

4. Approval for final BOM and Test Procedures

5. Issue of FIM to vendor (As Per Option-I or Option II) -

6. Team and Scheduling -

7.

Procurement of all Components etc as per A-BOM (Option I) -

Procurement of all Components etc as per A-BOM (Option II) -

8. Procurement of consumables, fabrication materials and tools required as per scope of work including any test equipment needed

-

9. Test jigs/set-ups if any required including procurement of components, harness, connectors etc. for the same (Elec.& Mech.)

-

10. Incoming Components quality Inspection -

11. PCB assembly work, Board Level Testing -

12. Post Production Acceptance Testing (including 168hr endurance)

(MRSA-SAC shall have the right to witness the testing process) -

13. Documentation of test results and final report -

14. Tests results review

15. Delivery of the deliverables at SAC

8. Terms and Conditions

1. The successful bidder shall execute a Non-disclosure Agreement (NDA) with SAC/ISRO related

to confidentiality of all the circuits, electronics configuration and other information provided

by SAC as proprietary elements of the work order, and respect the same. Execution of the

NDA is mandatory for issue of the FIM and other technical information including detailed

design data necessary for the manufacture and testing.

2. The technical offers meeting complete scope of work that is fabrication/assembly and testing

will only be considered.

3. If Option I is chosen, all A-BOM components, fabrication consumable material etc. shall be

procured by vendor through authentic, authorized and traceable sources and agents to

ensure quality of the raw material.

4. In case of Option I, if the vendor wishes to use a different equivalent part in the place of what

is suggested, or if the A-BOM specifies a generic part without a part-number, he shall obtain

prior permission and approval from MRSA-SAC for the same. Submission of sample/or

documents like data sheets is necessary for this purpose.

5. Any changes carried out in the design, drawings or documents during the contract tenure,

shall be exclusive property of SAC and shall not be used for any purpose other than what is

agreed upon.

6. All documents supplied by SAC are the exclusive property of SAC and shall not be used for any

purpose other than what is agreed upon.

7. Pre-bid discussions with interested vendors (if required) shall be organized at SAC

Ahmadabad. The date of same shall be communicated in advance. The pre-bid

discussions/meeting with Vendors at SAC, Ahmedabad is planned to clarify/resolve queries of

vendors. However a pre-bid discussion is not mandatory for bidding or carrying out the work.

8. The vendor shall fabricate the first unit as per the suggested flow of Annexure I, and submit the same

to MRSA-SAC for review. After obtaining the go-ahead he can fabricate the rest of the units. It is not

mandatory, though recommendable, for the vendor to follow the exact same fabrication sequence for

the rest of the deliveries. It may be noted that the vendor is responsible for completing the delivery

in all respects.

9. Typical sequence of events & guidelines to vendors for submitting the offer

The typical sequence of events in regard to this tendered requirement leading to the placement of

Purchase Order / Contract on the successful bidder is as follows:

1. Tendering of requirements by SAC.

2. Interested vendors to assess their technical capability, facility & infrastructure, manpower skill

levels & infrastructure required to carry out the work specified in this RFP.

3. Pre-bid discussions, if required, may be organized at SAC Ahmadabad, and if so the date of the

same will be communicated in advance. The pre-bid discussions/meeting with prospective

vendors at SAC, Ahmedabad is meant for clarifying/resolving queries of vendors. However pre-

bid discussions are not mandatory for either bidding, qualifying or for the placement of contract

on a successful bidder.

4. Submission of final bids in two parts as per advertisement & RFP. Bids should be submitted to

Space Applications Centre (SAC), Ahmadabad before due date.

5. Bid shall be submitted in two parts (for both Option I and Option 2) as per below.

Part-1: Technical proposal; including the following:

i) Point by point compliance to all the requirements in Section 5 (Vendor’s compliance).

ii) In case vendor envisages outsourcing partial fabrication / testing work it should be

indicated clearly. Details of such out-sourcing agency shall be included in the bid.

Part-2: Commercial offer

i) Quote for the deliverable as per the schedule of delivery

ii) Applicable taxes, levies etc

6. Opening of Technical Proposal bids at SAC as per procedures

7. The evaluation of Technical proposal submitted by vendors by the SAC. The vendors may be

asked to make technical presentation to the committee at SAC Ahmedabad during the process

of evaluation.

8. Recommendation to open commercial offers from vendors found technically suitable.

9. Opening of Price Bids of technically qualified vendors and preparation of Comparative

Statement by SAC as per procedures.

10. Issuing the PO/Contract to the vendor.

11. Acceptance of PO/Contract by Vendor and execution of NDA

12. Release of FIM (Either Option I or Option II) and Other information by SAC for the

manufacturing process.

13. Completion of the manufacturing and testing activity by the Vendor.

14. Delivery of the deliverables to SAC.

Annexure I Recommended Fabrication/Testing Procedure

Brief Description of the Tests of Lot1 to Lot 4 mounting are given in the next page.

Test for Lot 1 of Components After mounting of Lot 1 components (power supply section), the test involves providing 28V Raw DC power and a 5V level on/off command, followed by checking of supply voltages at 10 points. If any voltage does not meet the allowed range, the same needs to be debugged and rectified.

Test for Lot 2 of Components

After mounting of Lot 2 components (FPGA and capacitors), the test involves programming the FPGA with the provided bit file and then probing test points on the PCB to observe waveform patterns on DSO and compare with expected waveforms. Test for Lot 3 of Components

After mounting of Lot 3 components (Memory modules), the test involves programming the FPGA with the bit file provided for testing the Lot 3 components and verifying the Id of the memory modules through SAC supplied Test Utility Software. Test for Lot 4 of Components

After mounting of Lot 4 components (Serdes and Level translators), the test involves programming the FPGA with the bit file provided for testing the Lot 4 components and testing the completely mounted board through Test Utility Software.

The details of Lot 1 to Lot 4 components and all test details and specifications will be provided at the time of award of the contract to the successful bidder.

Government of India Indian Space Research Organization Space … · 2016-09-29 · Microwave Remote...

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